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Publication years (Num. hits)
1976-1991 (17) 1992-1995 (22) 1996-1997 (21) 1998-1999 (22) 2000-2002 (18) 2003-2005 (17) 2006-2007 (19) 2008-2009 (22) 2010-2011 (17) 2012-2015 (15) 2016-2019 (22) 2020-2022 (18) 2023 (10)
Publication types (Num. hits)
article(66) inproceedings(170) phdthesis(4)
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Found 240 publication records. Showing 240 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
140Hai Zhou 0001 Retiming and resynthesis with sweep are complete for sequential transformation. Search on Bibsonomy FMCAD The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
132Yu Hu 0002, Victor Shih, Rupak Majumdar, Lei He 0001 FPGA area reduction by multi-output function based sequential resynthesis. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF FPGA, logic synthesis, SAT, resynthesis
95Kai-Hui Chang, Igor L. Markov, Valeria Bertacco Fixing Design Errors With Counterexamples and Resynthesis. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
95Jie-Hong Roland Jiang, Wei-Lun Hung Inductive equivalence checking under retiming and resynthesis. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
80Nikolaos D. Liveris, Hai Zhou 0001, Prithviraj Banerjee Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
80Jie-Hong Roland Jiang, Robert K. Brayton Retiming and Resynthesis: A Complexity Perspective. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
80Jie-Hong Roland Jiang On Some Transformation Invariants Under Retiming and Resynthesis. Search on Bibsonomy TACAS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
65Demetrios Cantzos, Athanasios Mouchtaris, Chris Kyriakakis Enhanced Multichannel Audio Resynthesis Through Residual Processing and Features Alignment. Search on Bibsonomy ICME The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
65Irith Pomeranz, Sudhakar M. Reddy Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
65R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
58Kai-Hui Chang, Igor L. Markov, Valeria Bertacco Fixing Design Errors with Counterexamples and Resynthesis. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF simulation-based verification, digital design errors, error-correction framework, resynthesis techniques, goal-directed search, entropy-guided search, counterexamples, digital designs, combinational equivalence-checking
58Srivaths Ravi 0001, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits. Search on Bibsonomy J. Electron. Test. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF controller resynthesis, test synthesis, high-level testing
52Kai-Hui Chang, Igor L. Markov, Valeria Bertacco Safe Delay Optimization for Physical Synthesis. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF safe delay optimization, SafeResynth, safe resynthesis technique, immediately-measurable delay improvement, circuit timing, route length, physical synthesis, electronic design automation, route congestion, circuit delay
50Martin Heckmann, Claudius Gläser, Miguel Vaz, Tobias Rodemann, Frank Joublin, Christian Goerick Listen to the parrot: Demonstrating the quality of online pitch and formant extraction via feature-based resynthesis. Search on Bibsonomy IROS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
50Yu Hu 0002, Zhe Feng 0002, Lei He 0001, Rupak Majumdar Robust FPGA resynthesis based on fault-tolerant Boolean matching. Search on Bibsonomy ICCAD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
50Srimat T. Chakradhar, Sujit Dey Resynthesis and retiming for optimum partial scan. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
50Christopher K. Lennard, A. Richard Newton On estimation accuracy for guiding low-power resynthesis. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
50Heinz-Josef Eikerling, Ralf Hunstock, Raul Camposano Optimization of hierarchical designs using partitioning and resynthesis. Search on Bibsonomy ICCAD The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
50Kaushik De, Prithviraj Banerjee PREST: a system for logic partitioning and resynthesis for testability. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
45Athanasios Mouchtaris, Shrikanth S. Narayanan, Chris Kyriakakis Multichannel audio synthesis by subband-based spectral conversion and parameter adaptation. Search on Bibsonomy IEEE Trans. Speech Audio Process. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
43Angela Krstic, Kwang-Ting Cheng Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability. Search on Bibsonomy J. Electron. Test. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF resynthesis for testability, timing defects, delay testing, path delay faults, VLSI testing
43Alex Kondratyev, Michael Kishinevsky, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis. Search on Bibsonomy ASYNC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF combinational decomposition, sequential decomposition, monotonous cover, signal insertion, factorization, hazards, resynthesis, Speed-independent circuit
43Samir Lejmi, Bozena Kaminska, Bechir Ayari Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF segmentation cells, segmentation edges, logic testing, partitioning, timing, sequential circuits, sequential circuits, iterative methods, circuit analysis computing, retiming, iterative algorithm, circuit optimisation, logic partitioning, logic optimization, resynthesis, synchronous circuits, pseudo-exhaustive testing
37Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour Towards automated ECOs in FPGAs. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF pst, optimization, fpga, boolean satisfiability, resynthesis
37W. Knox Carey, Daniel B. Chuang, Sheila S. Hemami Regularity-Preserving Image Interpolation. Search on Bibsonomy ICIP (1) The full citation details ... 1997 DBLP  DOI  BibTeX  RDF regularity-preserving image interpolation, continuous signal, continuous derivatives, instantaneous luminance transitions, oversmoothed edges, wavelet-based interpolation method, wavelet transform coefficients decay, image resynthesis, average PSNR improvement, bicubic techniques, bilinear techniques, algorithm, image processing, natural images
37Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev Decomposition and technology mapping of speed-independent circuits using Boolean relations. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Boolean decomposition, decomposed logic sharing, design library, library matching, logic decomposition, logic resynthesis, signal insertion, two-input combinational gate, two-input sequential gate, optimization, technology mapping, circuit CAD, speed-independent circuits, netlist, complex gates, Boolean relations
37Dominik Stoffel, Wolfgang Kunz Record & play: a structural fixed point iteration for sequential circuit verification. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF circuit resynthesis, circuit retiming, combinational verification techniques, instruction queue, iterative circuit array, local circuit transformation, sequential circuit verification, sequential logic equivalence checking, structural fixed point iteration, time frame equivalence, logic testing, finite state machine, logic design
36Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang Scalable don't-care-based logic optimization and resynthesis. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF fpga, interpolation, windowing, technology mapping, boolean satisfiability, logic optimization
36Suresh Raman, Mike Lubyanitsky Cone Resynthesis ECO Methodology for Multi-Million Gate Designs. Search on Bibsonomy VLSI Design The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
36Murtaza Bulut, Sungbok Lee, Shrikanth S. Narayanan Recognition for synthesis: Automatic parameter selection for resynthesis of emotional speech from neutral speech. Search on Bibsonomy ICASSP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Smita Krishnaswamy, Stephen Plaza, Igor L. Markov, John P. Hayes Enhancing design robustness with reliability-aware resynthesis and logic simulation. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
36Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou Incremental physical resynthesis for timing optimization. Search on Bibsonomy FPGA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF FPGA, placement, logic synthesis, timing optimization
36Tiberiu Chelcea, Steven M. Nowick Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
36Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
36Priyank Kalla, Maciej J. Ciesielski Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence. Search on Bibsonomy DATE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
36Srivaths Ravi 0001, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Respecification, Synthesis for Testability, Don't Cares, High Level Testing
36Subhrajit Bhattacharya, Franc Brglez, Sujit Dey Transformations and resynthesis for testability of RT-level control-data path specifications. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
36Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
36Sujit Dey, Franc Brglez, Gershon Kedem Corolla Based Circuit Partitioning and Resynthesis. Search on Bibsonomy DAC The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
30Jason Cong, Kirill Minkovich Improved SAT-based Boolean matching using implicants for LUT-based FPGAs. Search on Bibsonomy FPGA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF logic synthesis, SAT, implicant, boolean matching, FPGA lookup table
30L.-M. Reissell, Dinesh K. Pai High Resolution Analysis of Impact Sounds and Forces. Search on Bibsonomy WHC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
30Milenko Drinic, Darko Kirovski Behavioral synthesis via engineering change. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF engineering change, scheduling, transformations, register assignment
30Enrique San Millán, Luis Entrena, José Alberto Espejo On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization. Search on Bibsonomy DSD The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
30Huiqun Liu, Martin D. F. Wong Network-flow-based multiway partitioning with area and pin constraints. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
30Chris J. Myers, Peter A. Beerel, Teresa H.-Y. Meng Technology mapping of timed circuits. Search on Bibsonomy ASYNC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF gate library, C-elements, ATACS, timing, logic design, logic CAD, asynchronous circuits, asynchronous circuits, timing information, AND gates, synthesis tool, OR gates, timed circuits
30Carl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton Multi-level synthesis for safe replaceability. Search on Bibsonomy ICCAD The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
22Dominic Wist, Mark Schäfer, Walter Vogler, Ralf Wollowski STG Decomposition: Internal Communication for SI Implementability. Search on Bibsonomy ACSD The full citation details ... 2010 DBLP  DOI  BibTeX  RDF CSC, decomposition, STG, resynthesis, speed independent
22Iris Hui-Ru Jiang, Hua-Yu Chang, Liang-Gi Chang, Huang-Bi Hung Matching-based minimum-cost spare cell selection for design changes. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF spare cells, matching, physical synthesis, resynthesis, ECO
22Hosung (Leo) Kim, John Lillis A framework for layout-level logic restructuring. Search on Bibsonomy ISPD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF logic resynthesis, timing optimization
22Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown FPGA technology mapping: a study of optimality. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF resynthesis optimization, FPGA, boolean satisfiability, lookup table, cone
22Stephen A. Edwards Making cyclic circuits acyclic. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF acyclic circuits, cyclic circuits, constructiveness, resynthesis
22François R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Michel Boyer Optimal design of synchronous circuits using software pipelining techniques. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF software pipelining, retiming, Resynthesis
22Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija CMOS Combinational Circuit Sizing by Stage-wise Tapering. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF tapering, Transistor sizing, resynthesis
22Irith Pomeranz, Sudhakar M. Reddy On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Lower bound on test set size, pipelining, multipliers, path delay faults, resynthesis
22Roman Kuznar, Franc Brglez PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF optimization, FPGA, partitioning, resynthesis, critical path delay
22Demetri Terzopoulos, Keith Waters Analysis and Synthesis of Facial Image Sequences Using Physical and Anatomical Models. Search on Bibsonomy IEEE Trans. Pattern Anal. Mach. Intell. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF expressions resynthesis, facial image sequences, graphics workstation, physics-based synthetic facial tissue, anatomically motivated facial muscle actuators, dynamical facial muscle contractions, expressive human faces, deformable contour models, image sequences, computer animation, facial animation, video sequences, snakes, biomechanics, biomechanics, face model, anatomical models
21Siang-Yun Lee, Giovanni De Micheli Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
21Ünal Ege Gaznepoglu, Nils Peters Evaluation of the Speech Resynthesis Capabilities of the VoicePrivacy Challenge Baseline B1. Search on Bibsonomy CoRR The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
21Navin Raj Prabhu, Nale Lehmann-Willenbrock, Timo Gerkmann In-the-wild Speech Emotion Conversion Using Disentangled Self-Supervised Representations and Neural Vocoder-based Resynthesis. Search on Bibsonomy CoRR The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
21Tu Anh Nguyen, Wei-Ning Hsu, Antony D'Avirro, Bowen Shi, Itai Gat, Maryam Fazel-Zarandi, Tal Remez, Jade Copet, Gabriel Synnaeve, Michael Hassid, Felix Kreuk, Yossi Adi, Emmanuel Dupoux EXPRESSO: A Benchmark and Analysis of Discrete Expressive Speech Resynthesis. Search on Bibsonomy CoRR The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
21Arianne Meijer-van de Griend Towards a generic compilation approach for quantum circuits through resynthesis. Search on Bibsonomy CoRR The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
21Felipe Almeida, Levent Aksoy, Quang-Linh Nguyen, Sophie Dupuis, Marie-Lise Flottes, Samuel Pagliarini Resynthesis-based Attacks Against Logic Locking. Search on Bibsonomy CoRR The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
21Wei-Ning Hsu, Tal Remez, Bowen Shi, Jacob Donley, Yossi Adi ReVISE: Self-Supervised Speech Resynthesis with Visual Input for Universal and Generalized Speech Regeneration. Search on Bibsonomy CVPR The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
21Felipe Almeida, Levent Aksoy, Quang-Linh Nguyen, Sophie Dupuis, Marie-Lise Flottes, Samuel Pagliarini Resynthesis-based Attacks Against Logic Locking. Search on Bibsonomy ISQED The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
21Görkem Gök, Özgül Salor, Müslüm Cengiz Taplamacioglu An Electric Arc Furnace Model Based on Resynthesis Using Frequency Spectrum Distributions of EAF Currents. Search on Bibsonomy IAS The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
21Tianji Liu, Evangeline F. Y. Young Rethinking AIG Resynthesis in Parallel. Search on Bibsonomy DAC The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
21Federico Simonetta, Federico Avanzini, Stavros Ntalampiras A perceptual measure for evaluating the resynthesis of automatic music transcriptions. Search on Bibsonomy Multim. Tools Appl. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
21Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich SCAR: Security Compliance Analysis and Resynthesis of Reconfigurable Scan Networks. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
21Federico Simonetta Music Interpretation Analysis. A Multimodal Approach To Score-Informed Resynthesis of Piano Recordings. Search on Bibsonomy CoRR The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
21Federico Simonetta, Federico Avanzini, Stavros Ntalampiras A Perceptual Measure for Evaluating the Resynthesis of Automatic Music Transcriptions. Search on Bibsonomy CoRR The full citation details ... 2022 DBLP  BibTeX  RDF
21Wei-Ning Hsu, Tal Remez, Bowen Shi, Jacob Donley, Yossi Adi ReVISE: Self-Supervised Speech Resynthesis with Visual Input for Universal and Generalized Speech Enhancement. Search on Bibsonomy CoRR The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
21Heinz Riener, Siang-Yun Lee, Alan Mishchenko, Giovanni De Micheli Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis. Search on Bibsonomy ASP-DAC The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
21Adam Polyak, Yossi Adi, Jade Copet, Eugene Kharitonov, Kushal Lakhotia, Wei-Ning Hsu, Abdelrahman Mohamed, Emmanuel Dupoux Speech Resynthesis from Discrete Disentangled Self-Supervised Representations. Search on Bibsonomy CoRR The full citation details ... 2021 DBLP  BibTeX  RDF
21Siang-Yun Lee, Heinz Riener, Giovanni De Micheli Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition. Search on Bibsonomy DDECS The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
21Adam Polyak, Yossi Adi, Jade Copet, Eugene Kharitonov, Kushal Lakhotia, Wei-Ning Hsu, Abdelrahman Mohamed, Emmanuel Dupoux Speech Resynthesis from Discrete Disentangled Self-Supervised Representations. Search on Bibsonomy Interspeech The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
21Jitka Kocnová, Zdenek Vasícek Resynthesis of logic circuits using machine learning and reconvergent paths. Search on Bibsonomy DSD The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
21Milos Ajcevic, Agostino Accardo, Maria Pia Francescato Modeling of glycogen resynthesis according to insulin concentration: towards a system for prevention of late-onset exercise-induced hypoglycemia in Type 1 diabetes patients. Search on Bibsonomy KES The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
21Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich Testability-Enhancing Resynthesis of Reconfigurable Scan Networks. Search on Bibsonomy ITC The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
21Wenting Dai, Marius Erdt, Alexei Sourin Anomaly Detection and Segmentation Based on Defect Repaired Image Resynthesis. Search on Bibsonomy CW The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
21Hao Shi, Wei Dong 0006, Rui Li 0050, Wanwei Liu Controller Resynthesis for Multirobot System When Changes Happen. Search on Bibsonomy Computer The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
21Jitka Kocnová, Zdenek Vasícek EA-based resynthesis: an efficient tool for optimization of digital circuits. Search on Bibsonomy Genet. Program. Evolvable Mach. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
21Jeongwoo Heo, Taewhan Kim Lightening Asynchronous Pipeline Controller Through Resynthesis and Optimization. Search on Bibsonomy ASP-DAC The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
21Soumi Maiti, Michael I. Mandel Speaker Independence of Neural Vocoders and Their Effect on Parametric Resynthesis Speech Enhancement. Search on Bibsonomy ICASSP The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
21Natalia Lylina, Ahmed Atteya, Chih-Hao Wang, Hans-Joachim Wunderlich Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks. Search on Bibsonomy ITC The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
21Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
21Soumi Maiti, Michael I. Mandel Speaker independence of neural vocoders and their effect on parametric resynthesis speech enhancement. Search on Bibsonomy CoRR The full citation details ... 2019 DBLP  BibTeX  RDF
21Soumi Maiti, Michael I. Mandel Speech denoising by parametric resynthesis. Search on Bibsonomy CoRR The full citation details ... 2019 DBLP  BibTeX  RDF
21Soumi Maiti, Michael I. Mandel Parametric Resynthesis with neural vocoders. Search on Bibsonomy CoRR The full citation details ... 2019 DBLP  BibTeX  RDF
21Krzysztof Lis, Krishna K. Nakka, Pascal Fua, Mathieu Salzmann Detecting the Unexpected via Image Resynthesis. Search on Bibsonomy CoRR The full citation details ... 2019 DBLP  BibTeX  RDF
21Krzysztof Lis, Krishna Kanth Nakka, Pascal Fua, Mathieu Salzmann Detecting the Unexpected via Image Resynthesis. Search on Bibsonomy ICCV The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
21Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines. Search on Bibsonomy DATE The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
21Soumi Maiti, Michael I. Mandel Parametric Resynthesis With Neural Vocoders. Search on Bibsonomy WASPAA The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
21Soumi Maiti, Michael I. Mandel Speech Denoising by Parametric Resynthesis. Search on Bibsonomy ICASSP The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
21Christopher Beckham, Sina Honari, Vikas Verma, Alex Lamb, Farnoosh Ghadiri, R. Devon Hjelm, Yoshua Bengio, Chris Pal On Adversarial Mixup Resynthesis. Search on Bibsonomy NeurIPS The full citation details ... 2019 DBLP  BibTeX  RDF
21Rafael Trapani Possignolo, Jose Renau SMatch: Structural Matching for Fast Resynthesis in FPGAs. Search on Bibsonomy DAC The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
21Hsin-Ho Huang, Huimei Cheng, Chris Chu, Peter A. Beerel Area Optimization of Timing Resilient Designs Using Resynthesis. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
21Soumi Maiti, Joey Ching, Michael I. Mandel Large Vocabulary Concatenative Resynthesis. Search on Bibsonomy INTERSPEECH The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
21Ali Raza Syed, Viet Anh Trinh, Michael I. Mandel Concatenative Resynthesis with Improved Training Signals for Speech Enhancement. Search on Bibsonomy INTERSPEECH The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
21Alexander L. Stempkovskiy, Dmitry V. Telpukhov, Vladislav Nadolenko Development of Resynthesis Flow for Improving Logical Masking Features of Combinational Circuits. Search on Bibsonomy EWDTS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
21Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli Improvements to boolean resynthesis. Search on Bibsonomy DATE The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
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