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Found 9752 publication records. Showing 9752 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
131Jin Li, Chuan-lin Wu A modular growth architecture for an ATM switch. Search on Bibsonomy ICCCN The full citation details ... 1995 DBLP  DOI  BibTeX  RDF modular growth architecture, growable ATM switch architecture, large scale ATM switch, switch size, nonuniform modular growth ATM switch, knockout switch, internal traffic, nonuniform concentration, connection pattern, performance, delay, throughput, telecommunication traffic
106Hyoung-Il Lee, Seung-Woo Seo Matching output queueing with a multiple input/output-queued switch. Search on Bibsonomy IEEE/ACM Trans. Netw. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF combined input/output-queued (CIOQ) switch, multiple input/output-queued (MIOQ) switch, output queueing emulation, parallel switching architecture
96Hongbing Fan, Yu-Liang Wu, Ray Chak-Chung Cheung, Jiping Liu Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF reconfigurable interconnection network, switch block, hyperuniversal, FPGA, universal, switch box
89Cheng-Shang Chang, Duan-Shin Lee, Ching-Ming Lien Load balanced Birkhoff-von Neumann switches with resequencing. Search on Bibsonomy SIGMETRICS Perform. Evaluation Rev. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
88Michael Shyu, Yu-Dong Chang, Guang-Ming Wu, Yao-Wen Chang Generic Universal Switch Blocks. Search on Bibsonomy ICCD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF HFPGA, logic block, switch block, programmable switch, universal switch block, dimension constraint, FPGA, routing, flexibility, routability
80Sundar Iyer, Nick McKeown Analysis of the parallel packet switch architecture. Search on Bibsonomy IEEE/ACM Trans. Netw. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF output queueing, load balancing, packet switch, Clos network, inverse multiplexing
79Deng Pan, Yuanyuan Yang 0001 FIFO-Based Multicast Scheduling Algorithm for Virtual Output Queued Packet Switches. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF virtual output queued (VOQ) switch, head of line (HOL) blocking, scheduling, Multicast, crossbar switch, multicast switch
78Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Birkhoff-von Neumann symmetric TDM switch IC, SERDES interfaces, load-balanced TDM switch IC, digital TDM switch, 8B10B CODEC, analog SERDES I/O interfaces, dual-mode SERDES, half-rate architectures, all static CMOS gates, wide-band CML buffer, PMOS active load scheme, 20 Gbit/s, high speed networking, CMOS technology, low power consumption, 0.18 micron
78Sushil Aryal, James S. Meditch Design of a large ATM switch with trunk grouping. Search on Bibsonomy ICCCN The full citation details ... 1995 DBLP  DOI  BibTeX  RDF load throughput value, dense VLSI implementation, large ATM switch with trunk grouping, LAST switch, IBSS, ideal bit by bit self routing switch, delay, topology, throughput, interconnections, communication complexity, modules, circuit complexity, cell loss
73Aditya Agrawal, Anand Raju, Sachidanand Varadarajan, Magdy A. Bayoumi A scalable shared buffer ATM switch architecture. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF electronic switching systems, field effect transistor switches, scalable shared buffer ATM switch architecture, memory bandwidth requirement, maximum crosspoint switch size, buffer memory size, access time reduction, multiple buffer memories, 8/spl times/8 switch, 1 mum, 622 Mbit/s, asynchronous transfer mode, asynchronous transfer mode, shared memory systems, buffer storage, CMOS technology, CMOS digital integrated circuits, B-ISDN, B-ISDN, switching circuits, parallel access
73Cheng-Shang Chang, Duan-Shin Lee, Ying-Ju Shih, Chao-Lin Yu Mailbox switch: a scalable two-stage switch architecture for conflict resolution of ordered packets. Search on Bibsonomy IEEE Trans. Commun. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
72Hagit Attiya, David Hay, Isaac Keslassy Packet-mode emulation of output-queued switches. Search on Bibsonomy SPAA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF CIOQ switch, output-queued, packet-mode scheduling, switch emulation, packet switching, queuing delay
72Hongbing Fan, Yu-Liang Wu Crossbar based design schemes for switch boxes and programmable interconnection networks. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF switch matrix, FPGA, routing, interconnection network, layout, crossbar, switch box
70Hongbing Fan, Jiping Liu, Yu-Liang Wu General Models and a Reduction Design Technique for FPGA Switch Box Designs. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2003 DBLP  DOI  BibTeX  RDF hyper-universal, FPGA, global routing, detailed routing, reduction technique, optimum design, switch box
69Byoung-Seok Park, Sung-Chun Kim Design and Analysis of a New Fast Packet Switching Fabric Supporting Multimedia Traffic. Search on Bibsonomy LCN The full citation details ... 1996 DBLP  DOI  BibTeX  RDF fast packet switching fabric, ATM switch architecture, output queueing, switch analysis, FAB Banyan switching fabrics, Batcher sorter, double shuffle network, packet distributors, FAB networks, output buffer modules, compressed video data, performance evaluation, throughput, packet switching, hardware implementation, voice, multimedia traffic, packet delay, switch design, packet loss probability, text data
68Guang-Ming Wu, Yao-Wen Chang Switch-matrix architecture and routing for FPDs. Search on Bibsonomy ISPD The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
68Parimal Patel, Saad Zahid Design Considerations in an ATM Switch Design. Search on Bibsonomy ICCCN The full citation details ... 1998 DBLP  DOI  BibTeX  RDF ATM switch design, packet switching, ATM Switch, Switch architecture
68Chao-Ju Hou, Ching-Chih Han, Wun-Chun Chau Priority-based high-speed switch scheduling for ATM networks. Search on Bibsonomy LCN The full citation details ... 1995 DBLP  DOI  BibTeX  RDF iterated switching networks, priority-based high-speed switch scheduling, AN2 switch, parallel iterative matching algorithm, maximal input-output matching, priority lists, input/output pairs, probability analysis, switch size, high QoS requirements, simulation, scheduling, parallel algorithms, computational complexity, asynchronous transfer mode, probability, local area networks, iterative methods, time complexity, ATM networks, iterations, switches, high-performance distributed computing
67Jin Li, Chuan-lin Wu A novel architecture for an ATM switch. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF multicast function, shared-buffer ATM switch, first-in and first-out shared buffer, FIFO address queue, cell-loss performance, performance evaluation, asynchronous transfer mode, ATM switch, B-ISDN, control logic, buffer utilization
65Abdel Ejnioui, N. Ranganathan Routing on Switch Matrix Multi-FPGA Systems. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF switch routing, Field programmable arrays, Multi-FPGA systems, Global routing, FPGA architecture, Interconnection structure
64Mingyao Yang, Lionel M. Ni Design of Scalable and Multicast Capable Cut-Through Switches for High-Speed LANs. Search on Bibsonomy ICPP The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Intra-switch interconnect, Switch packaging, Multicast, Deadlock-free routing, Switch architecture, Cut-through switching
63Yao-Wen Chang, D. F. Wong 0001, C. K. Wong Universal switch modules for FPGA design. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
62Jin Li An output-shared buffer ATM switch. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF buffer ATM switch, output-shared, lower bandwidth, asynchronous transfer mode, ATM switch, buffer utilization
60Ron Gabor, Shlomo Weiss, Avi Mendelson Fairness enforcement in switch on event multithreading. Search on Bibsonomy ACM Trans. Archit. Code Optim. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF SOE, Switch on Event multithreading, coarse-grained multithreading, weighted speedup, performance, fairness, throughput, multithreading
60Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. Panda 0001 Implementing Multidestination Worms in Switch-Based Parallel Systems: Architectural Alternatives and Their Impact. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF switch/router architecture, performance evaluation, multicast, interconnection networks, broadcast, collective communication, wormhole switching, Parallel computer architecture, cut-through switching
59Hakyong Kim, Kiseon Kim Performance analysis of the multiple input-queued packet switch with the restricted rule. Search on Bibsonomy IEEE/ACM Trans. Netw. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Multiple input queueing (MIQ), free rule, restricted rule
59Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung On optimal hyperuniversal and rearrangeable switch box designs. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
59Michael Shyu, Guang-Ming Wu, Yu-Dong Chang, Yao-Wen Chang Generic Universal Switch Blocks. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF design, architecture, Analysis, digital, programmable logic array, gate array
57Hongbing Fan, Jiping Liu, Yu-Liang Wu, C. K. Wong Reduction design for generic universal switch blocks. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF FPGA architecture design, routing requirement, switch module, universal switch block, routing, decomposition
57Latha A. Kant, William H. Sanders Loss process analysis of the knockout switch using stochastic activity networks. Search on Bibsonomy ICCCN The full citation details ... 1995 DBLP  DOI  BibTeX  RDF loss process analysis, knockout switch, fast packet switches, consecutive cell losses, tagged port, telecommunication switch design, quality of service, performance, asynchronous transfer mode, asynchronous transfer mode, Markov processes, ATM networks, bursty traffic, B-ISDN, stochastic activity networks, cell loss probability
55Fang Liu, Fei Guo, Yan Solihin, Seongbeom Kim, Abdulaziz Eker Characterizing and modeling the behavior of context switch misses. Search on Bibsonomy PACT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF context switch misses, stack distance profiling, prefetching, analytical model
55Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang 0011, Michael Orshansky Architecting a reliable CMP switch architecture. Search on Bibsonomy ACM Trans. Archit. Code Optim. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF CMP switch, reliability, defect-tolerance
55Man Chi Chan, Tony T. Lee Statistical performance guarantees in large-scale cross-path packet switch. Search on Bibsonomy IEEE/ACM Trans. Netw. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF cross-path switch, exponential bounded burstiness (EBB) processes, path switching, semioptical network, statistical performance guarantees, token assignment algorithm, quality of service (QoS), clos network, service curves
55Yao-Wen Chang, D. F. Wong 0001, C. K. Wong Design and analysis of FPGA/FPIC switch modules. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF FPGA/FPIC switch modules, routing resources, FPIC, network-flow techniques, field programmable interconnect chip, field programmable gate arrays, FPGA, field programmable gate arrays, logic design, heuristic algorithm, programmable logic arrays, routability
54Minsik Ahn, Chang-Ho Lee, Joy Laskar CMOS High Power SPDT Switch using Multigate Structure. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
54Yao-Wen Chang, Kai Zhu 0001, Guang-Ming Wu, D. F. Wong 0001, C. K. Wong Analysis of FPGA/FPIC switch modules. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF FPIC, FPGA, synthesis, layout, Computer-aided design of VLSI
54Herman Schmit, Vikas Chandra FPGA switch block layout and evaluation. Search on Bibsonomy FPGA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF VLSI layout, FPGA interconnect
53Robert R. Henry 0002 A multicast ATM switch with slotted ring fabric. Search on Bibsonomy ICCCN The full citation details ... 1997 DBLP  DOI  BibTeX  RDF multicast ATM switch, slotted ring fabric, slotted ring ATM switch architecture, optical fiber switch, deterministic performance analysis equations, delay performance, zero blocking performance, 150 Mbit/s, asynchronous transfer mode, switching fabric
53Syed Sohel Hussain, Yih-Chyun Jenq Analysis and Optimization of a Banyan-Based ATM Switch by Simulations. Search on Bibsonomy LCN The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Banyan based ATM switch, switch optimization, switch analysis, delay variance, performanc analysis, uniform traffic, three-state model, nonblocking first stage, packet blocking, enhanced priority scheme, single buffer Banyan network, double buffer switching element, delay sensitive voice packet, asynchronous transfer mode, asynchronous transfer mode, delay, throughput, bandwidth, simulation results, voice traffic, data traffic
53Yao-Wen Chang, D. F. Wong 0001, C. K. Wong FPGA global routing based on a new congestion metric. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF FPGA global routing, congestion metric, routing capacity, switch block, switch-block capacity, congestion-control metric, global router, channel densities, field programmable gate arrays, congestion control, logic design, programmable logic arrays, circuit layout CAD, graph modeling
52Y. Chang, Nada Golmie, David H. Su Study of interoperability between EFCI and ER switch mechanisms for ABR traffic in an ATM network. Search on Bibsonomy ICCCN The full citation details ... 1995 DBLP  DOI  BibTeX  RDF ABR traffic, rate-based flow control, transmission rate control, feedback information, resource management cells, network switching nodes, ATM Forum Traffic Management Specification, network switch mechanism, ATM switch vendor, bandwidth allocation fairness, explicit forward congestion indication, explicit rate mechanism, end system behavior, congestion notification, algorithms, interoperability, asynchronous transfer mode, asynchronous transfer mode, ATM network, simulation results, network performance, simulation study, performance characteristics, available bit rate, destination nodes
51Bin Wu 0002, Kwan L. Yeung, Mounir Hamdi, Xin Li 0028 Minimizing internal speedup for performance guaranteed switches with optical fabrics. Search on Bibsonomy IEEE/ACM Trans. Netw. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF optical switch fabric, performance guaranteed switching, reconfiguration overhead, scheduling, speedup
51Daqing Xu, Hisao Kameda Friend Pointer Registration Strategy and Its Scheme for Mobile Location Management. Search on Bibsonomy AINA Workshops (2) The full citation details ... 2007 DBLP  DOI  BibTeX  RDF mobile tracking, mobile locating, old switch, new switch, home switch, friend switch, friend pointer, friend node and neighborhood, FPRMP
50Vincent W. S. Wong 0001, Mark E. Lewis, Victor C. M. Leung Stochastic control of path optimization for inter-switch handoffs in wireless ATM networks. Search on Bibsonomy IEEE/ACM Trans. Netw. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF connection rerouting, inter-switch bandoff, path optimization, wireless ATM
50Rajeev Sivaram, Ram Kesavan, Dhabaleswar K. Panda 0001, Craig B. Stunkel Where to Provide Support for Efficient Multicasting in Irregular Networks: Network Interface or Switch? Search on Bibsonomy ICPP The full citation details ... 1998 DBLP  DOI  BibTeX  RDF cut-through routing, performance evaluation, multicast, broadcast, collective communication, Parallel computer architecture, irregular networks, switch-based networks
50Youngbok Choi, Hideki Tode, Hiromi Okada, Hiromasa Ikeda A Large Capacity Photonic ATM Switch for Wavelength Division Multiplexing Networks. Search on Bibsonomy ICCCN The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Electronic Control, WDM Optical Buffer, ATM Switching, WDM Optical Networks, Photonic Switch
49Alexander Kesselman, Kirill Kogan, Michael Segal 0001 Best Effort and Priority Queuing Policies for Buffered Crossbar Switches. Search on Bibsonomy SIROCCO The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
49Josef Giglmayr All-optical multi-layer switching architectures: (I) MxN-gon prism switches. Search on Bibsonomy ICCCN The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Optical waveguide, 2x2-switch, directional coupler, Mach-Zehnder interferometer, cycle structure, logical switch architecture, physical switch, all-optical 3-D grid, grid size, mapping, connectivity, multi-layer
49Chih-Hao Liu, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yarsun Hsua Multi-mode message passing switch networks applied for QC-LDPC decoder. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
49Ron Gabor, Shlomo Weiss, Avi Mendelson Fairness and Throughput in Switch on Event Multithreading. Search on Bibsonomy MICRO The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
49Chia-Lung Liu, Woei Lin, Chin-Chi Wu Speedup Requirements for Output Queuing Emulation with a Sliding-Window Parallel Packet Switch. Search on Bibsonomy International Conference on Computational Science (4) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
49Ding-Jyh Tsaur, Hsuan-Kuei Cheng, Chia-Lung Liu, Woei Lin A Study of Matching Output Queueing with a 3D-VOQ Switch. Search on Bibsonomy ICOIN The full citation details ... 2006 DBLP  DOI  BibTeX  RDF output queueing emulation, 3D-VOQ, QoS, switching system
49Donghyun Kim, Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip. Search on Bibsonomy ISCAS (3) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
49Abhijit M. Lele, S. K. Nandy 0001 Architecture of Reconfigurable a Low Power Gigabit AT Switch. Search on Bibsonomy VLSI Design The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
49Terry Bearly, Jagan P. Agrawal A split input sunshine switch architecture. Search on Bibsonomy IPCCC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
49Jin Li, Chuan-lin Wu Design and implementation of a multicast-buffer ATM switch. Search on Bibsonomy ICNP The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
48Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi Using the inter- and intra-switch regularity in NoC switch testing. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
48Eiji Oki, Zhigang Jing, Roberto Rojas-Cessa, H. Jonathan Chao Concurrent round-robin-based dispatching schemes for Clos-network switches. Search on Bibsonomy IEEE/ACM Trans. Netw. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Clos-network switch, throughput, packet switch, arbitration, dispatching
48Byoung Seob Park, Sung Chun Kim FBSF: a new fast packet switching fabric based-on multistage interconnection network with multiple outlets. Search on Bibsonomy ISPAN The full citation details ... 1996 DBLP  DOI  BibTeX  RDF packet switching fabric, FBSF, multiple outlets, ATM switch architecture, FAB Banyan Switching Fabrics, Batcher sorter, radix-r double shuffle network, r-packet distributors, parallel architectures, packet switching, multistage interconnection networks, multistage interconnection network, switch fabrics
48Nabanita Das 0001, Jayasree Dattagupta A fault location technique and alternate routing in Benes network. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF fault location technique, single switch fault, recirculation, source-destination path, routing technique, exact locations, multiple switch fault detection, one bit test vectors, equivalent fault set, fault diagnosis, fault tolerant computing, reconfiguration, reconfigurable architectures, multistage interconnection networks, multistage interconnection networks, network routing, Benes network, rearrangeable network, alternate routing
47Steven E. Butner, David A. Skirmont Architecture and design of a 40 gigabit per second ATM switch. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF ATM links, buffering scheme, 40 Gbit/s, asynchronous transfer mode, multiprocessor interconnection networks, optical interconnections, ATM switch, optical communication, switch architecture
46Rajeev Sivaram, Ram Kesavan, Dhabaleswar K. Panda 0001, Craig B. Stunkel Architectural Support for Efficient Multicasting in Irregular Networks. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF cut-through routing, performance evaluation, multicast, broadcast, collective communication, Parallel computer architecture, irregular networks, switch-based networks
45Gaspar Mora, José Flich, José Duato, Pedro López 0001, Elvira Baydal, Olav Lysne Towards an efficient switch architecture for high-radix switches. Search on Bibsonomy ANCS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF arbiter efficiency, partitioned crossbar, switch organization
45Hongbing Fan, Yu-Liang Wu, Chak-Chung Cheung, Jiping Liu On Optimal Irregular Switch Box Designs. Search on Bibsonomy FPL The full citation details ... 2004 DBLP  DOI  BibTeX  RDF FPGA, Configurable computing, on-chip network, switch box
45Ali Reza Ejlali, Seyed Ghassem Miremadi Switch-level emulation. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF FPGA chips, gate-level models, emulation, switch-level models
45Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. Panda 0001 HIPIQS: A High-Performance Switch Architecture Using Input Queuing. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF switch/router design, interconnection networks, parallel architectures, networks of workstations, high-speed interconnects
45Ram Kesavan, Dhabaleswar K. Panda 0001 Efficient Multicast on Irregular Switch-Based Cut-Through Networks with Up-Down Routing. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF cut-through routing, multicast, broadcast, wormhole routing, collective communication, networks of workstations, Parallel computer architecture, irregular networks, switch-based networks
45Joseph Kee-Yin Ng, Shibin Song, Wei Zhao 0001 Integrated delay analysis of regulated ATM switch. Search on Bibsonomy RTSS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF integrated delay analysis, regulated ATM switch, worst case delay, hard real-time connection, real-time connection traffic, arrival functions, priority driven scheduling, FIFO scheduling, admission probability, cell delay estimation, performance, asynchronous transfer mode, deadline, simulation experiments, service functions, piecewise linear functions
45Michael Jurczyk Performance and Implementation Aspects of Higher Order Head-of-Line Blocking Switch Boxes. Search on Bibsonomy ICPP The full citation details ... 1997 DBLP  DOI  BibTeX  RDF central memory buffering, higher order blocking effects, multistage cube network, nonuniform traffic patterns, switch box implementation
44Cheng-Shang Chang, Jay Cheng, Duan-Shin Lee, Chi-Feung Wu Quasi-Output-Buffered Switches. Search on Bibsonomy INFOCOM The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
44Aditya Dua, Benjamin Yolken, Nicholas Bambos Power Managed Packet Switching. Search on Bibsonomy ICC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
44Ching-Te Chiu, Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
44Herman Schmit, Vikas Chandra Layout techniques for FPGA switch blocks. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
44Ching-Te Chiu, Chun-Chieh Chang, Shih-Min Chen, Hou-Cheng Tzeng, Ming-Chang Du, Yu-Ho Hsu, Jen-Ming Wu, Kai-Ming Feng A 20 Gbps Scalable Load-Balanced TDM Switch with CODEC for High Speed Networking Applications. Search on Bibsonomy IWSOC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
44Satyen Sukhtankar, Diana Hecht, Warren Rosen A Novel Switch Architecture for High-Performance Computing and Signal Processing Networks. Search on Bibsonomy NCA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
44Gagan Aggarwal, Rajeev Motwani 0001, Devavrat Shah, An Zhu Switch Scheduling via Randomized Edge Coloring. Search on Bibsonomy FOCS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
44Seyed Ghassem Miremadi, Ali Reza Ejlali Switch Level Fault Emulation. Search on Bibsonomy FPL The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
44Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung On Optimum Designs of Universal Switch Blocks. Search on Bibsonomy FPL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
44Tamaree Nalin, Isobe Takashi, Hiroaki Morino, Hitoshi Aida, Tadao Saito A Scalable and High Capacity Router on Multi-Dimension Crossbar Switch Principle. Search on Bibsonomy LCN The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
44Thai Thach Bao, Hiroaki Morino, Hitoshi Aida, Tadao Saito Distributed Input and Deflection Routing Based Packet Switch Using Shuffle Pattern Network. Search on Bibsonomy NETWORKING The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
44Shinichiro Mutoh, Satoshi Shigematsu, Yoshinori Gotoh, Shinsuke Konaka Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs. Search on Bibsonomy ASP-DAC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
44Craig B. Stunkel, Rajeev Sivaram, Dhabaleswar K. Panda 0001 Implementing Multidestination Worms in Switch-Based Parallel Systems: Architectural Alternatives and their Impact. Search on Bibsonomy ISCA The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
43Xiaoliang Wang 0001, Xiaohong Jiang 0001, Susumu Horiguchi CBX-1 Switch: An Effective Load Balanced Switch. Search on Bibsonomy PDCAT The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
42Erol Basturk, Alexander Birman, G. Delp, Roch Guérin, R. Haas, Sanjay Kamat, Dilip D. Kandlur, P. Pan, Dimitrios E. Pendarakis, Vinod G. J. Peris, Raju Rajan, Debanjan Saha, Doug Williams Design and implementation of a QoS capable switch-router. Search on Bibsonomy ICCCN The full citation details ... 1997 DBLP  DOI  BibTeX  RDF QoS capable switch-router, core ATM switch fabric, intelligent adapters, RSVP signalling, prototype network, UNIX hosts, network performance measurements, Internet, Internet, design, architecture, resource management, implementation, service differentiation, high throughput, IETF, control engine
42Wilbert H. F. J. Körver A universal formalization of the effects of threshold voltages for discrete switch-level circuit models. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF field effect transistor switches, threshold voltage effects, discrete switch-level circuit models, universal formalization, switch imperfection, CMOS design, demolition degree, CMOS digital integrated circuits, state transitions, integrated circuit modelling, switching circuits
41Isaac Keslassy, Murali S. Kodialam, T. V. Lakshman, Dimitrios Stiliadis On guaranteed smooth scheduling for input-queued switches. Search on Bibsonomy IEEE/ACM Trans. Netw. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF scheduling, router, switch, jitter
41Laxmi N. Bhuyan, Ravi R. Iyer 0001, Hu-Jun Wang, Akhilesh Kumar Impact of CC-NUMA Memory Management Policies on the Application Performance of Multistage Switching Networks. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Memory management, shared-memory multiprocessor, wormhole routing, scientific applications, execution-driven simulation, switch design
40Chuanpeng Li, Chen Ding 0001, Kai Shen Quantifying the cost of context switch. Search on Bibsonomy Experimental Computer Science The full citation details ... 2007 DBLP  DOI  BibTeX  RDF context switch, cache interference
40Wenjie Li, Bin Liu 0001, Yang Xu 0010, Heng Liao Parallel Switch System with QoS Guarantee for Real-Time Traffic. Search on Bibsonomy J. Comput. Sci. Technol. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF QoS, load-balancing, parallel, priority, switch system
40Simon Jolly, Atanas N. Parashkevov, Tim McDougall Automated equivalence checking of switch level circuits . Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF MOS circuits, custom design, switch level analysis, formal verification, VLSI design, equivalence checking
40Marius Pirvu, Nan Ni, Laxmi N. Bhuyan Exploring the Switch Design Space in a CC-NUMA Multiprocessor Environment. Search on Bibsonomy IPDPS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF input buffer management, CC-NUMA multiprocessors, performance evaluation, arbitration, execution driven simulation, switch design
40Chris Plate, Jack Tan Performance Analysis of a Fault-Tolerant B-Tree ATM Switch. Search on Bibsonomy LCN The full citation details ... 1996 DBLP  DOI  BibTeX  RDF fault-tolerant B-tree ATM switch, ATM switching fabrics, buffering methods, simulation, performance analysis, asynchronous transfer mode, asynchronous transfer mode, routing algorithm, ATM networks, traffic models, multiplexing, real-time traffic, computer industry, telecommunications industry, data packets
40Gee-Swee Poo, Yinzhu Zhou A, new multicast wavelength assignment algorithm in wavelength-routed WDM networks. Search on Bibsonomy IEEE J. Sel. Areas Commun. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
40Hongyun Zheng, Yongxiang Zhao, Changjia Chen Design and Implementation of Switches in Network Simulator (ns2). Search on Bibsonomy ICICIC (1) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
40Xiaoming Liu 0003, Robbert van Renesse Fast protocol transition in a distributed environment (brief announcement). Search on Bibsonomy PODC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
39Qixin Wang, Sathish Gopalakrishnan, Xue Liu 0001, Lui Sha A Switch Design for Real-Time Industrial Networks. Search on Bibsonomy IEEE Real-Time and Embedded Technology and Applications Symposium The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
39Hoa Le Minh, Fary Ghassemlooy, Wai Pang Ng An Ultrafast with High Contrast Ratio 12 All-optical Switch based on Tri-arm Mach-Zehnder employing All-optical Flip-flop. Search on Bibsonomy ICC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
39Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew Soft Error Mitigation in Switch Modules of SRAM-based FPGAs. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
39David Marche, Yves Gagnon, Yvon Savaria . A new switch compensation technique for inverted R-2R ladder DACs. Search on Bibsonomy ISCAS (1) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi Probabilistic Analysis of Fault Tolerance of FPGA Switch Block Array. Search on Bibsonomy IPDPS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF fault tolerance, FPGA, routing, testing
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