Search results for "TSPC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
122	B. Le Chapelain, A. Mechain, Yvon Savaria, Guy Bois	Development of a high performance TSPC library for implementation of large digital building blocks.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
96	Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska	Design and performance of CMOS TSPC cells for high speed pseudo random testing.	VTS	1996	DBLP DOI BibTeX RDF	CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists
84	João Navarro Jr., Wilhelmus A. M. Van Noije	Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
84	Andreas Wassatsch, Dirk Timmermann	Scalable counter architecture for a pre-loadable 1 GHz@0.6 um/5V pre-scaler in TSPC.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
77	Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije	A 4.1 GHz prescaler using double data throughput E-TSPC structures.	SBCCI	2007	DBLP DOI BibTeX RDF	TSPC, high speed digital circuit, prescaler
76	Frank Grassert, Dirk Timmermann	Dynamic single phase logic with self-timed stages for power reduction in pipeline circuit designs.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
69	Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije	A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35m CMOS technology.	SBCCI	2004	DBLP DOI BibTeX RDF	TSPC, high speed digital circuit, low power, prescaler
65	Johnny Pihl	Design automation with the TSPC circuit technique: a high-performance wave digital filter.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
57	Ching-Hwa Cheng	Design Scan Test Strategy for Single Phase Dynamic Circuits.	DFT	2003	DBLP DOI BibTeX RDF
46	Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije	A 4.1 GHz Dual Modulus Prescaler Using the E-TSPC Technique and Double Data Throughput Structures.	ISCAS	2007	DBLP DOI BibTeX RDF
46	Xiaopeng Yu, Manh Anh Do, Jianguo Ma, Kiat Seng Yeo	A New Phase Noise Model for TSPC based divider.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
46	Bill Pontikakis, Mohamed Nekili	A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
27	Premananda B. S., Abdur Rehman, P. Megha	Area and Power Efficient AVLS-TSPC-Based Diffused Bit Generator for Key Generation.	Circuits Syst. Signal Process.	2024	DBLP DOI BibTeX RDF
27	Zisong Wang, Peiyi Zhao, Tom Springer, Congyi Zhu, Jaccob Mau, Andrew Wells, Yinshui Xia, Lingli Wang	Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
27	Khaled Humood, Alexander Serb, Shiwei Wang 0001, Themis Prodromakis	Power, Performance and Area Optimization of Parallel Load Counters through Logic Minimization and TSPC-FF Utilization.	ICECS	2023	DBLP DOI BibTeX RDF
27	Md. Sazzad Hossain, Mateus Bernardino Moreira, Francois Sandrez, Francois Rivet, Hervé Lapuyade, Yann Deval	Low Power Frequency Dividers using TSPC logic in 28nm FDSOI Technology.	LASCAS	2022	DBLP DOI BibTeX RDF
27	Fei Yuan 0005	Metastability Correction Techniques for TSPC-DFF with Applications in Vernier TDC.	ISCAS	2022	DBLP DOI BibTeX RDF
27	K. Lakshmi BhanuPrakash Reddy, K. B. Dheeraj Kumar, Vikramkumar Pudi	Design of Energy-Efficient TSPC based D Flip-flop for CNTFET Technology.	VDAT	2021	DBLP DOI BibTeX RDF
27	Oliver Schrape, Marko S. Andjelkovic, Anselm Breitenreiter, Alexey Balashov, Milos Krstic	Design Concept for Radiation-Hardening of Triple Modular Redundancy TSPC Flip-Flops.	DSD	2020	DBLP DOI BibTeX RDF
27	Wen-Cheng Lai, Sheng-Lyang Jang, Joseph Demferlee Tatel	Super-Regenerative Receiver with TSPC Divide-by-8 Frequency Pulse for Multi-sensor Applications.	ICPS	2019	DBLP DOI BibTeX RDF
27	Ludovic Moreau, Rémi Dekimpe, David Bol	A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells.	ISCAS	2019	DBLP DOI BibTeX RDF
27	Shubhanshu Gupta, Joycee Mekie	Soft Error Resilient and Energy Efficient Dual Modular TSPC Flip-Flop.	VLSID	2019	DBLP DOI BibTeX RDF
27	François Stas, David Bol	Integration of level shifting in a TSPC flip-flop for low-power robust timing closure in dual-Vdd ULV circuits.	ISCAS	2017	DBLP DOI BibTeX RDF
27	Sayyaparaju Sagar Varma, Arvind Kumar Sharma, Bulusu Anand	An efficient methodology to characterize the TSPC flip flop setup time for static timing analysis.	SMACD	2016	DBLP DOI BibTeX RDF
27	Wen-rui Zhu, Haigang Yang, Tongqiang Gao, Fei Liu 0011, Tao Yin, Dandan Zhang, Hongfeng Zhang	A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
27	Manthena Vamshi Krishna, Anil Jain, Nasir Abdul Quadir, Paul D. Townsend, Peter Ossieur	A 1V 2mW 17GHz multi-modulus frequency divider based on TSPC logic using 65nm CMOS.	ESSCIRC	2014	DBLP DOI BibTeX RDF
27	Xifan Tang, Jian Zhang 0067, Pierre-Emmanuel Gaillardon, Giovanni De Micheli	TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs.	ISCAS	2014	DBLP DOI BibTeX RDF
27	Hyunchol Shin	A 1-V TSPC Dual Modulus Prescaler with Speed Scalability Using Forward Body Biasing in 0.18 µm CMOS.	IEICE Trans. Electron.	2012	DBLP DOI BibTeX RDF
27	Jerry Lam, Calvin Plett	Modified TSPC clock dividers for higher frequency division by 3 and lower power operation.	NEWCAS	2012	DBLP DOI BibTeX RDF
27	João Navarro Jr., Gustavo Campos Martins	Design of high speed digital circuits with E-TSPC cell library.	SBCCI	2011	DBLP DOI BibTeX RDF
27	Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo	Low power semi-static TSPC D-FFs using split-output latch.	ISOCC	2011	DBLP DOI BibTeX RDF
27	Seungsoo Kim, Jaewook Shin, Hyunchol Shin	On-the-fly speed and power scaling of an E-TSPC dual modulus prescaler using forward body bias in 0.25 μm CMOS.	ISCAS	2010	DBLP DOI BibTeX RDF
27	Yingbo Hu, Runde Zhou	Low Clock-Swing TSPC Flip-Flops for Low-Power Applications.	J. Circuits Syst. Comput.	2009	DBLP DOI BibTeX RDF
27	João Paulo Carmo, Paulo Mateus Mendes, José Higino Correia	A 4.2 mW 5.7-GHz frequency synthesizer with dynamic-logic (TSPC) frequency divider.	ICT	2009	DBLP DOI BibTeX RDF
27	Abhijit R. Asati, Chandrashekhar	An improved high speed fully pipelined 500 MHz 8×8 baugh wooley multiplier design using 0.6 μm CMOS TSPC logic design style.	ICIIS	2008	DBLP DOI BibTeX RDF
27	Kuo-Hsing Cheng, Shun-Wen Cheng, Wen-Shiuan Lee	64-bit Pipeline Carry Lookahead Adder Using all-n-transistor Tspc Logics.	J. Circuits Syst. Comput.	2006	DBLP DOI BibTeX RDF
27	Frank Grassert, Frank Sill, Claas Cornelius, Dirk Timmermann	Verlustleistungsreduzierung bei dynamischen TSPC-Schaltungstechniken.	GI Jahrestagung (1)	2005	DBLP BibTeX RDF
27	Hung-Pin Chen 0001, James B. Kuo	A 0.8 V CMOS TSPC adiabatic DCVS logic circuit with the bootstrap technique for low-power VLSI.	ICECS	2004	DBLP DOI BibTeX RDF
27	Jinn-Shyan Wang, Po-Hui Yang, Duo Sheng	Design of a 3-V 300-MHz low-power 8-b×8-b pipelined multiplier using pulse-triggered TSPC flip-flops.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
27	Joao Navarro Soares, Wilhelmus A. M. Van Noije	The Use of Extended TSPC CMOS Structures to Build Circuits with Doubled Input/Output Data Throughput.	SBCCI	2000	DBLP BibTeX RDF
27	Joao Navarro Soares, Wilhelmus A. M. Van Noije	A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC).	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
27	Johnny Pihl, Einar J. Aas	4300 Megasamples/s Wave Digital Filter Implementation In Bit-parallel Tspc Circuit Technique.	ISSPA	1996	DBLP DOI BibTeX RDF
27	R. Pereira, Juan A. Michell, José M. Solana	Fully pipelined TSPC barrel shifter for high-speed applications.	IEEE J. Solid State Circuits	1995	DBLP DOI BibTeX RDF
27	Patrik Larsson, Christer Svensson	Impact of clock slope on true single phase clocked (TSPC) CMOS circuits.	IEEE J. Solid State Circuits	1994	DBLP DOI BibTeX RDF
27	P. Zhou, J. C. Czilli, Graham A. Jullien, William C. Miller	Current Input TSPC Latch for High Speed, Complex Switching Trees.	ISCAS	1994	DBLP DOI BibTeX RDF
19	Arash Talebi, Witold A. Krzymien	Multiple-Antenna Multiple-Relay Cooperative Communication System with Beamforming.	VTC Spring	2008	DBLP DOI BibTeX RDF
19	Rangakrishnan Srinivasan, Didem Zeliha Turker, Sang Wook Park, Edgar Sánchez-Sinencio	A Low-Power Frequency Synthesizer with Quadrature Signal Generation for 2.4 GHz Zigbee Transceiver Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
19	S. M. Rezaul Hasan	A PMOS-diode Differential Body-driven Offset compensated 0.5V.	VLSI Design	2007	DBLP DOI BibTeX RDF
19	Shweta Srivastava, Jaijeet S. Roychowdhury	Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition Equations.	DAC	2007	DBLP DOI BibTeX RDF
19	I-Chyn Wey, Lung-Hao Chang, You-Gang Chen, Shih-Hung Chang, An-Yeu Wu	A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
19	Bibhudatta Sahoo 0002, Keshab K. Parhi	A Low Power Correlator for CDMA Wireless Systems.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	low-power, correlator, CDMA, incrementer
19	Frank Grassert, Dirk Timmermann	Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	redundant numbers, self-timed logic, single-rail logic, low power, dynamic logic
19	Rolando Ramírez Ortiz, John P. Knight	Compatible cell connections for multifamily dynamic logic gates.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
19	Hong Jo Ahn, Mohammed Ismail 0001	GHz programmable dual-modulus prescaler for multi-standard wireless applications.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
19	Fabrizio Viglione, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni	A 50 Mbit/s Iterative Turbo-Decoder.	DATE	2000	DBLP DOI BibTeX RDF
19	Bibhudatta Sahoo 0002, Martin Kuhlmann, Keshab K. Parhi	A low-power correlator.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
19	Won Hyo Lee, Jun Dong Cho, Sung Dae Lee	A High Speed and Low Power Phase-Frequency Detector and Charge - pump.	ASP-DAC	1999	DBLP DOI BibTeX RDF