Search results for "VLSI-SoC"

Hits ?▲	Authors	Title	Venue	Year	Link
70	Ricardo Reis 0001, Manfred Glesner	VLSI-SoC: An Enduring Tradition.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
61	Victor Grimblatt, Chip-Hong Chang, Ricardo Reis 0001, Anupam Chattopadhyay, Andrea Calimera (eds.)	VLSI-SoC: Technology Advancement on SoC Design - 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, October 4-8, 2021, Revised and Extended Selected Papers	VLSI-SoC (Selected Papers)	2022	DBLP DOI BibTeX RDF
61	Moreno Bragaglio, Samuele Germiniani, Graziano Pravadelli	Exploiting Program Slicing and Instruction Clusterization to Identify the Cause of Faulty Temporal Behaviours at System Level.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
61	Zhao Han, Gabriel Rutsch, Deyan Wang, Bowen Li, Sebastian Siegfried Prebeck, Daniela Sanchez Lopera, Keerthikumara Devarajegowda, Wolfgang Ecker	Transformative Hardware Design Following the Model-Driven Architecture Vision.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
61	Ming Ming Wong, Lu Chen, Anh Tuan Do	An Improved Deterministic Stochastic MAC (SC-MAC) for High Power Efficiency Design.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
61	Thiago Santos Copetti, Tobias Gemmeke, Letícia Maria Bolzani Pöhls	A DfT Strategy for Detecting Emerging Faults in RRAMs.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
61	Sarah Azimi, Corrado De Sio, Andrea Portaluri, Luca Sterpone	Design and Mitigation Techniques of Radiation Induced SEEs on Open-Source Embedded Static RAMs.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
61	Julie Roux, Katell Morin-Allory, Vincent Beroulle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier, Régis Leveugle	FMEA on Critical Systems: A Cross-Layer Approach Based on High-Level Models.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
61	Matthieu Couriol, Patsy Cadareanu, Edouard Giacomin, Pierre-Emmanuel Gaillardon	A First Approach in Using Super-Steep-Subthreshold-Slope Field-Effect Transistors in Ultra-Low Power Analog Design.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
61	Shubham Rai, Nishant Gupta, Abhiroop Bhattacharjee, Ansh Rupani, Michael Raitza, Jens Trommer, Thomas Mikolajick, Akash Kumar 0001	END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
61	J. Gasquez, Bastien Giraud, P. Boivin, Y. Moustapha-Rabault, Vincenzo Della Marca, Jean-Michel Walder, Jean-Michel Portal	A Regulated Sensing Solution Based on a Self-reference Principle for PCM + OTS Memory Array.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
61	Parya Zolfaghari, Sébastien Le Beux	Design of a Reconfigurable Optical Computing Architecture Using Phase Change Material.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
61	Francesco Daghero, Alessio Burrello, Chen Xie, Luca Benini, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari	Low-Overhead Early-Stopping Policies for Efficient Random Forests Inference on Microcontrollers.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
61	Luca Mocerino, Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Enrico Macii	On the Efficiency of AdapTTA: An Adaptive Test-Time Augmentation Strategy for Reliable Embedded ConvNets.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
61	Christian Piguet, Ricardo Reis 0001, Dimitrios Soudris (eds.)	VLSI-SoC: Design Methodologies for SoC and SiP - 16th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2008, Rhodes Island, Greece, October 13-15, 2008, Revised Selected Papers	VLSI-SoC (Selected Papers)	2010	DBLP DOI BibTeX RDF
61	Laura Frigerio, Kellie Marks, Argy Krikelis	Timed Coloured Petri Nets for Performance Evaluation of DSP Applications: The 3GPP LTE Case Study.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
61	Alessandro Cilardo, Nicola Mazzocca	Time Efficient Dual-Field Unit for Cryptography-Related Processing.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
61	Ian O'Connor, Ilham Hassoune, David Navarro	Fine-Grain Reconfigurable Logic Cells Based on Double-Gate MOSFETs.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
61	Vincenzo Rana, David Atienza, Marco D. Santambrogio, Donatella Sciuto, Giovanni De Micheli	A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
61	Kostas Siozios, Dimitrios Soudris	A Temperature-Aware Placement and Routing Algorithm Targeting 3D FPGAs.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
61	Tilo Meister, Jens Lienig, Gisbert Thomke	Universal Methodology to Handle Differential Pairs during Pin Assignment.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
61	Andre Guntoro, Manfred Glesner	A Lifting-Based Discrete Wavelet Transform and Discrete Wavelet Packet Processor with Support for Higher Order Wavelet Filters.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
61	Enrico Dallago, Daniele Miatton, Giuseppe Venchi, Valeria Bottarel, Giovanni Frattini, Giulio Ricotti, Monica Schipani	Comparison of Two Autonomous AC-DC Converters for Piezoelectric Energy Scavenging Systems.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
61	Vasilis F. Pavlidis, Eby G. Friedman	Physical Design Issues in 3-D Integrated Technologies.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
61	Nikolas Kroupis, Dimitrios Soudris	Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
61	Christophe Escriba, Remy Fulcrand, Philippe Artillan, David Jugieu, Aurélien Bancaud, Ali Boukabache, Anne Marie Gué, Jean-Yves Fourniols	Trapping Biological Species in a Lab-on-Chip Microsystem: Micro Inductor Optimization Design and SU8 Process.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
61	Vassilios Vonikakis, Chryssanthi Iakovidou, Ioannis Andreadis	Real-Time Biologically-Inspired Image Exposure Correction.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
61	Andreas Floros, Yiorgos Tsiatouhas, Xrysovalantis Kavousianos	Timing Error Detection and Correction by Time Dilation.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
61	Vasilios Kalenteridis, Konstantinos Papathanasiou, Stylianos Siskos	Analysis and Design of Charge Pumps for Telecommunication Applications.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
61	Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re	On the Comparison of Different Number Systems in the Implementation of Complex FIR Filters.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
51	Andrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Ricardo Reis 0001 (eds.)	VLSI-SoC: Design Trends - 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
51	Carolina Metzler, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Carlos Silva Cárdenas, Ricardo Reis 0001 (eds.)	VLSI-SoC: New Technology Enabler - 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco, Peru, October 6-9, 2019, Revised and Extended Selected Papers	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
51	Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung Kyu Lim, Arijit Raychowdhury	Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
51	Tannu Sharma, Sumanth Kolluru, Kenneth S. Stevens	Learning Based Timing Closure on Relative Timed Design.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
51	Amin Aghighi, Behrouz Farhang-Boroujeny, Armin Tajalli	Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
51	Tutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K. Cherivirala, Kyumin Kwon, Shourya Gupta, Wenbo Duan, Jeongsup Lee, Chien-Hen Chen, Mehdi Saligane, Dennis Sylvester, David T. Blaauw, Ronald Dreslinski Jr., Benton H. Calhoun, David D. Wentzloff	Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
51	Samuele Germiniani, Moreno Bragaglio, Graziano Pravadelli	From Informal Specifications to an ABV Framework for Industrial Firmware Verification.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
51	Josie Esteban Rodriguez Condia, Matteo Sonza Reorda	Modular Functional Testing: Targeting the Small Embedded Memories in GPUs.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
51	Shanshan Dai, Caleb R. Tulloss, Xiaoyu Lian, Kangping Hu, Sherief Reda, Jacob K. Rosenstein	Low Power Current-Mode Relaxation Oscillators for Temperature and Supply Voltage Monitoring.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
51	Jonas Gava, Ricardo Reis 0001, Luciano Ost	RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation Technique.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
51	Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon	3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
51	Adi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky	abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
51	Alessandro Veronesi, Davide Bertozzi, Milos Krstic	Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
51	Yinghua Hu, Kaixin Yang, Shahin Nazarian, Pierluigi Nuzzo 0002	SANSCrypt: Sporadic-Authentication-Based Sequential Logic Encryption.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
51	Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury	Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
51	Arnaud Poittevin, Chhandak Mukherjee, Ian O'Connor, Cristell Maneux, Guilhem Larrieu, Marina Deng, Sébastien Le Beux, François Marc, Aurélie Lecestre, Cédric Marchand 0002, Abhishek Kumar	3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
51	Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek	SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
51	David Cordova, Wim Cops, Yann Deval, François Rivet, Hervé Lapuyade, Nicolas Nodenot, Yohan Piccin	Low-Power High-Speed ADCs for ADC-Based Wireline Receivers in 22 nm FDSOI.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
51	Michail Maniatakos, Ibrahim Abe M. Elfadel, Matteo Sonza Reorda, H. Fatih Ugurdag, José Monteiro 0001, Ricardo Reis 0001 (eds.)	VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things - 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017, Revised and Extended Selected Papers	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
51	Nicola Bombieri, Graziano Pravadelli, Masahiro Fujita, Todd M. Austin, Ricardo Reis 0001 (eds.)	VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, Revised and Extended Selected Papers	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
51	Solon Falas, Charalambos Konstantinou, Maria K. Michael	Hardware-Enabled Secure Firmware Updates in Embedded Systems.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
51	Y. Serhan Gener, Furkan Aydin, Sezer Gören 0001, H. Fatih Ugurdag	Semi- and Fully-Random Access LUTs for Smooth Functions.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
51	Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis 0001	Process Variability Impact on the SET Response of FinFET Multi-level Design.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
51	László Szilágyi, Jan Plíva, Ronny Henker	Offset-Compensation Systems for Multi-Gbit/s Optical Receivers.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
51	Atishay, Ankit Gupta 0010, Rashmi Sonawat, Helik Kanti Thacker, Prasanth B	A Statistical Wafer Scale Error and Redundancy Analysis Simulator.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
51	Michelangelo Grosso, Matteo Sonza Reorda, Salvatore Rinaudo	Software-Based Self-Test for Delay Faults.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
51	Longfei Wang, Soner Seçkiner, Selçuk Köse	Reliability Enhanced Digital Low-Dropout Regulator with Improved Transient Performance.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
51	Leonardo B. Moraes, Alexandra Lackmann Zimpeck, Cristina Meinhardt, Ricardo A. L. Reis	Robust FinFET Schmitt Trigger Designs for Low Power Applications.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
51	Patsy Cadareanu, Ganesh Gore, Edouard Giacomin, Pierre-Emmanuel Gaillardon	A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
51	João Vieira, Edouard Giacomin, Yasir Mahmood Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon	Accelerating Inference on Binary Neural Networks with Digital RRAM Processing.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
51	Chen-Ying Hsieh, Ardalan Amiri Sani, Nikil D. Dutt	Exploiting Heterogeneous Mobile Architectures Through a Unified Runtime Framework.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
51	Rafael B. Schvittz, Denis Teixeira Franco, Leomar S. da Rosa, Paulo F. Butzen	An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
51	Vitor V. Bandeira, Felipe Rosa 0001, Ricardo Reis 0001, Luciano Ost	Efficient Soft Error Vulnerability Analysis Using Non-intrusive Fault Injection Techniques.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
51	Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik	On Test Generation for Microprocessors for Extended Class of Functional Faults.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
51	Bruno Forlin, Cezar Reinbrecht, Johanna Sepúlveda	Security Aspects of Real-Time MPSoCs: The Flaws and Opportunities of Preemptive NoCs.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
51	Valentino Peluso, Andrea Calimera	Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
51	Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada	A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
51	Md. Adnan Zaman, Rajeev Joshi, Srinivas Katkoori	Optimizing Performance and Energy Overheads Due to Fanout in In-Memory Computing Systems.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
51	Anna Bernasconi 0001, Antonio Boffa, Fabrizio Luccio, Linda Pagli	The Connection Layout in a Lattice of Four-Terminal Switches.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
51	Luca Stornaiuolo, Marco Rabozzi, Marco D. Santambrogio, Donatella Sciuto, Catalin Bogdan Ciobanu, Giulio Stramondo, Ana Lucia Varbanescu	Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
51	Swagata Mandal, Yaswanth Tavva, Debjyoti Bhattacharjee, Anupam Chattopadhyay	ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
51	Víctor H. Champac, Andres F. Gomez, Freddy Forero, Kaushik Roy 0001	Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
51	Xiaorui Liu, Anastasis Keliris, Charalambos Konstantinou, Marios Sazos, Michail Maniatakos	Assessment of Low-Budget Targeted Cyberattacks Against Power Systems.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
51	Francesco Barchi, Gianvito Urgese, Enrico Macii, Andrea Acquaviva	Mapping Spiking Neural Networks on Multi-core Neuromorphic Platforms: Problem Formulation and Performance Analysis.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
51	Tim Fritzmann, Thomas Schamberger, Christoph Frisch, Konstantin Braun, Georg Maringer, Johanna Sepúlveda	Efficient Hardware/Software Co-design for NTRU.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
51	Shahzad Muzaffar, Ibrahim Abe M. Elfadel	An Instruction Set Architecture for Secure, Low-Power, Dynamic IoT Communication.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
51	Riccardo Cantoro, Sara Carbonara, Andrea Floridia, Ernesto Sánchez 0001, Matteo Sonza Reorda, Jan-Gerd Mess	Improved Test Solutions for COTS-Based Systems in Space Applications.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
51	Utkarsh Gupta, Irina Ilioaea, Vikas Rao, Arpitha Srinath, Priyank Kalla, Florian Enescu	Rectification of Arithmetic Circuits with Craig Interpolants in Finite Fields.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
51	Thomas Hollstein, Jaan Raik, Sergei Kostin, Anton Tsertov, Ian O'Connor, Ricardo Reis 0001 (eds.)	VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability - 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, Revised Selected Papers	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
51	Wala Saadeh, Muhammad Awais Bin Altaf	A Wearable Neuro-Degenerative Diseases Classification System Using Human Gait Dynamics.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
51	Kimiyoshi Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, Hideharu Amano	Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
51	Thiago Santos Copetti, Guilherme Cardoso Medeiros, Letícia Maria Bolzani Poehls, Tiago R. Balen	Evaluating the Impact of Resistive Defects on FinFET-Based SRAMs.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
51	Markus Stefan Wamser, Georg Sigl	Pushing the Limits Further: Sub-Atomic AES.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
51	Daniele Cesarini, Andrea Bartolini, Luca Benini	Modeling and Evaluation of Application-Aware Dynamic Thermal Control in HPC Nodes.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
51	Sukarn Agarwal, Hemangee K. Kapoor	Lifetime Enhancement of Non-Volatile Caches by Exploiting Dynamic Associativity Management Techniques.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
51	Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Jun Zhou 0017	On the Efficiency of Early Bird Sampling (EBS) an Error Detection-Correction Scheme for Data-Driven Voltage Over-Scaling.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
51	Vivek Nautiyal, Lalit Gupta, Gaurav Singla, Jitendra Dasani, Sagar Dwivedi, Martin Kinkade	Self-timed Power-on Reset Circuit for Pseudo Dual/Two Port SRAM Used in Low-Voltage IoT Applications.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
51	Stefano Aldegheri, Nicola Bombieri	Integrating Simulink, OpenVX, and ROS for Model-Based Design of Embedded Vision Applications.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
51	Shahzad Muzaffar, Ibrahim Abe M. Elfadel	Pulsed Decimal Encoding for IoT Single-Channel Dynamic Signaling.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
51	Matthias Thiele, Steve Bigalke, Jens Lienig	Electromigration Analysis of VLSI Circuits Using the Finite Element Method.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
51	Youngsoo Shin, Chi-Ying Tsui, Jae-Joon Kim, Kiyoung Choi, Ricardo Reis 0001 (eds.)	VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected Papers	VLSI-SoC (Selected Papers)	2016	DBLP DOI BibTeX RDF
51	Maedeh Hemmat, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram	Robust Hybrid TFET-MOSFET Circuits in Presence of Process Variations and Soft Errors.	VLSI-SoC (Selected Papers)	2016	DBLP DOI BibTeX RDF
51	Guillaume Plassan, Hans-Jörg Peter, Katell Morin-Allory, Shaker Sarwary, Dominique Borrione	Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings.	VLSI-SoC (Selected Papers)	2016	DBLP DOI BibTeX RDF
51	Xueqing Li, Kaisheng Ma, Sumitha George, John Sampson, Vijaykrishnan Narayanan	Enabling Internet-of-Things with Opportunities Brought by Emerging Devices, Circuits and Architectures.	VLSI-SoC (Selected Papers)	2016	DBLP DOI BibTeX RDF
51	Nimrod Wald, Elad Amrani, Avishay Drori, Shahar Kvatinsky	Logic with Unipolar Memristors - Circuits and Design Methodology.	VLSI-SoC (Selected Papers)	2016	DBLP DOI BibTeX RDF
51	Yanzhe Li, Kai Huang 0002, Luc Claesen	A Novel Hardware-Oriented Stereo Matching Algorithm and Its Architecture Design in FPGA.	VLSI-SoC (Selected Papers)	2016	DBLP DOI BibTeX RDF
51	Alexander W. Rath, Sebastian Simon, Volkan Esen, Wolfgang Ecker	Earth Mover's Distance as a Comparison Metric for Analog Behavior.	VLSI-SoC (Selected Papers)	2016	DBLP DOI BibTeX RDF
51	Valentino Peluso, Roberto Giorgio Rizzo, Andrea Calimera, Enrico Macii, Massimo Alioto	Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping.	VLSI-SoC (Selected Papers)	2016	DBLP DOI BibTeX RDF
51	Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino	Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits.	VLSI-SoC (Selected Papers)	2016	DBLP DOI BibTeX RDF
51	Paolo Bernardi, Alberto Bosio, Giorgio Di Natale, Andrea Guerriero, Ernesto Sánchez 0001, Federico Venini	Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs.	VLSI-SoC (Selected Papers)	2016	DBLP DOI BibTeX RDF