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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 89 occurrences of 58 keywords
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Results
Found 67 publication records. Showing 67 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
52 | Amit Laknaur, Sai Raghuram Durbha, Haibo Wang 0005 |
Built-In-Self-Testing Techniques for Programmable Capacitor Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(4-6), pp. 449-462, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
programmable capacitor array, built-in-self-testing, analog testing, field programmable analog array |
45 | Krishnendu Chakrabarty, John P. Hayes |
Balance testing and balance-testable design of logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 8(1), pp. 71-86, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
built-in self testing, design for testability, fault detection, fault coverage, testing methods |
37 | Nur A. Touba, Edward J. McCluskey |
Applying two-pattern tests using scan-mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 393-399, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
scan-mapping, combinational mapping logic, logic testing, built-in self test, built-in self-testing, fault coverage, delay faults, pseudo-random testing, deterministic testing, two-pattern tests |
32 | Amit Laknaur, Haibo Wang 0005 |
Built-In-Self-Testing Techniques for Programmable Capacitor Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 434-439, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Kwanghyun Kim, Dong Sam Ha, Joseph G. Tront |
On using signature registers as pseudorandom pattern generators in built-in self-testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(8), pp. 919-928, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
32 | Sandeep K. Venishetti, Ali Akoglu, Rahul Kalra |
Hierarchical Built-in Self-testing and FPGA Based Healing Methodology for System-on-a-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), August 5-8, 2007, University of Edinburgh, Scotland, United Kingdom, pp. 717-724, 2007, IEEE Computer Society, 0-7695-2866-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Imtiaz P. Shaik, Michael L. Bushnell |
Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming . ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 393-399, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
low overhead delay-fault BIST, constrained quadratic 0-1 programming, built-in self testing model, weighted signed graph balancing problem, VLSI, logic testing, delays, built-in self test, integrated circuit testing, logic design, automatic testing, integrated circuit design, quadratic programming, circuit design, digital integrated circuits, hazards and race conditions |
30 | Imtiaz P. Shaik, Michael L. Bushnell |
A graph approach to DFT hardware placement for robust delay fault BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 177-182, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI |
29 | Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya |
Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 205-, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Built-in self-test, TPG, delay faults, robust testing, two-pattern tests |
27 | Jianxun Liu, Wen-Ben Jone |
An efficient routing method for pseudo-exhaustive built-in self-testing of high-speed interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 360-367, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Shambhu J. Upadhyaya, Kewal K. Saluja |
A new approach to the design of built-in self-testing PLAs for high fault coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1), pp. 60-67, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
27 | S. B. Tan, K. Totton, Keith Baker, Prab Varma, R. Porter |
A Fast Signature Simulation Tool for Built-In Self-Testing Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 17-25, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
24 | Marco Balboni, Davide Bertozzi |
Transparent lifetime built-in self-testing of networks-on-chip through the selective non-concurrent testing of their communication channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AISTECS@HiPEAC ![In: Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC 2017, Stockholm, Sweden, January 25, 2017, pp. 12-17, 2017, ACM, 978-1-4503-5226-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Kim T. Le, Kewal K. Saluja |
A Novel Approach for Testing Memories Using a Built-In Self Testing Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1986, Washington, D.C., USA, September 1986, pp. 830-839, 1986, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP BibTeX RDF |
|
23 | Nicola Caselli, Alessandro Strano, Daniele Ludovici, Davide Bertozzi |
Cooperative Built-in Self-Testing and Self-Diagnosis of NoC Bisynchronous Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MCSoC ![In: IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2012, Fukushima, Japan, September 20-22, 2012, pp. 159-166, 2012, IEEE Computer Society, 978-1-4673-2535-6. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
23 | Pinaki Mazumder |
An Integrated Built-In Self-Testing and Self-Repair of VLSI/WSI Hexagonal Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1992, Discover the New World of Test and Design, Baltimore, Maryland, USA, September 20-24, 1992, pp. 968-977, 1992, IEEE Computer Society, 0-7803-0760-7. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
23 | Josep Altet, André Ivanov, A. Wong |
Thermal Testing of Analogue Integrated Circuits: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(3), pp. 353-357, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
test of analogue ICs, thermal analysis of ICs, built-in self-testing, CMOS technology, thermal testing |
23 | Josep Altet, Antonio Rubio 0001, Wilfrid Claeys, Stefan Dilhaire, Emmanuel Schaub, Hideo Tamamoto |
Differential Thermal Testing: An Approach to its Feasibility. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(1-2), pp. 57-66, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
test of integrated circuits, built-in self testing, thermal testing, thermal sensors |
23 | Mohamed Soufi, Yvon Savaria, F. Darlay, Bozena Kaminska |
Producing Reliable Initialization and Test of Sequential Circuits with Pseudorandom Vectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 44(10), pp. 1251-1256, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
full reset, initialization of sequential circuits, modelization of sequential circuits, Markov chain processes, Built-in self-testing, pseudorandom testing, testability measures, partial reset |
23 | C. L. Chen |
Exhaustive Test Pattern Generation Using Cyclic Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(2), pp. 225-228, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
exhaustive test pattern generation, punctured cyclic codes, VLSI, logic testing, built-in self testing, automatic testing, codes, linear feedback shift registers, VLSI circuits |
23 | Kozo Kinoshita, Kewal K. Saluja |
Built-In Testing of Memory Using an On-Chip Compact Testing Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(10), pp. 862-870, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
weight-sensitive faults, random- access memory (RAM), Built-in self-testing (BIST), stuck-at faults, built-in testing (BIT), pattern-sensitive faults, hardware complexity |
20 | Krishnendu Chakrabarty, John P. Hayes |
Cumulative balance testing of logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(1), pp. 72-83, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Jürgen Maier 0002, Andreas Steininger |
Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2006.04577, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
19 | Chunmei Hu, Zhenyang Zhang, Yang Guo, Jingyan Xu |
A Implementation for Built-in Self-Testing of RapidIO by JTAG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 13th IEEE International Conference on ASIC, ASICON 2019, Chongqing, China, October 29 - November 1, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-0735-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Szu Huat Goh, Y. H. Chan, Zhao Lin, Jeffrey Lam |
Concurrent built-in self-testing under the constraint of shared test resources and its test time reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 59, pp. 198-205, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
19 | Gabriele Miorandi, Alberto Celin, Michele Favalli, Davide Bertozzi |
A built-in self-testing framework for asynchronous bundled-data NoC switches resilient to delay variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Tenth IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016, Nara, Japan, August 31 - September 2, 2016, pp. 1-8, 2016, IEEE, 978-1-4673-9030-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
19 | Jürgen Maier 0002, Andreas Steininger |
Online test vector insertion: A concurrent built-in self-testing (CBIST) approach for asynchronous logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, Warsaw, Poland, 23-25 April, 2014, pp. 33-38, 2014, IEEE Computer Society, 978-1-4799-4560-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
19 | Alessandro Strano, Nicola Caselli, Simone Terenzi, Davide Bertozzi |
Optimising pseudo-random built-in self-testing of fully synchronous as well as multisynchronous networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 7(2), 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Alessandro Strano, Davide Bertozzi, Arnaud Grasset, Sami Yehia |
Exploiting structural redundancy of SIMD accelerators for their built-in self-testing/diagnosis and reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2011, Santa Monica, CA, USA, Sept. 11-14, 2011, pp. 141-148, 2011, IEEE Computer Society, 978-1-4577-1291-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Sunil R. Das, Altaf Hossain, Satyendra Biswas, Emil M. Petriu, Mansour H. Assaf, Wen-Ben Jone, Mehmet Sahinoglu |
On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 57(10), pp. 2146-2168, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Miguel Angel DomÃnguez, José L. AusÃn, J. Francisco Duque-Carrillo, Guido Torelli |
A high-quality sine-wave oscillator for analog built-in self-testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Vinod Narayanan, Swaroop Ghosh, Wen-Ben Jone, Sunil R. Das |
A built-in self-testing method for embedded multiport memory arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 54(5), pp. 1721-1738, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Omar I. Khan, Michael L. Bushnell |
Spectral Analysis for Statistical Response Compaction During Built-In Self-Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 67-76, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni |
Programmable built-in self-testing of embedded RAM clusters in system-on-chip architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Commun. Mag. ![In: IEEE Commun. Mag. 41(9), pp. 90-97, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Sunil R. Das, Made Sudarma, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Krishnendu Chakrabarty, Mehmet Sahinoglu |
Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 52(5), pp. 1363-1380, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Krishnendu Chakrabarty, Shivakumar Swaminathan |
Built-in self testing of high-performance circuits using twisted-ring counters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, pp. 72-75, 2000, IEEE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray |
Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 16th IEEE VLSI Test Symposium (VTS '98), 28 April - 1 May 1998, Princeton, NJ, USA, pp. 418-423, 1998, IEEE Computer Society, 0-8186-8436-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | O. A. Petlin, Stephen B. Furber |
Built-In Self-Testing of Micropipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands, pp. 22-29, 1997, IEEE Computer Society, 0-8186-7922-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Built-in self-test, Design for test, Asynchronous design, Micropipelines |
19 | Krishnendu Chakrabarty, Jian Liu, Minyao Zhu, Brian T. Murray |
Test Width Compression for Built-In Self Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1997, Washington, DC, USA, November 3-5, 1997, pp. 328-337, 1997, IEEE Computer Society, 0-7803-4209-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Krishnendu Chakrabarty |
Test response compaction for built-in self testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1995 |
RDF |
|
19 | Mashkuri Yaacob, Ibrahim Abubakr |
A Built-in Self-Testing Bit Slice Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Applied Informatics ![In: The 12st IASTED International Conference on Applied Informatics, May 18-20, 1994, Annecy, France, pp. 177-179, 1994, IASTED/ACTA Press, 0-88986-190-0. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
19 | Franc Novak, Nenad Sutanovac, Roman Trobec |
Built-in self testing of communications systems using ASIC technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 17(8), pp. 475-480, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Scott Chiu, Christos A. Papachristou |
A Built-In Self-Testing Approach for Minimizing Hardware Overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '91, Cambridge, MA, USA, October 14-16, 1991, pp. 282-285, 1991, IEEE Computer Society, 0-8186-2270-9. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
19 | Manoj Franklin, Kewal K. Saluja |
Built-in Self-testing of Random-Access Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 23(10), pp. 45-56, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
19 | Kewal K. Saluja, Siew H. Sng, Kozo Kinoshita |
Built-In Self-Testing RAM: A Practical Alternative. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 4(1), pp. 42-51, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
19 | R. Kh. Latypov |
Built-in Self-testing of Logic Circuits Using Imperfect Duplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCT ![In: Fundamentals of Computation Theory, International Conference FCT'87, Kazan, USSR, June 22-26, 1987, Proceedings, pp. 279-283, 1987, Springer, 3-540-18740-5. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
19 | Sunil K. Jain, Charles E. Stroud |
Built-in Self Testing of Embedded Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 3(5), pp. 27-37, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
17 | R. P. van Riessen, Hans G. Kerkhoff, A. Kloppenburg |
Designing and Implementing an Architecture with Boundary Scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 7(1), pp. 9-19, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
15 | Wen-Ben Jone, Anita Gleason |
Analysis of Hamming count compaction scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(4), pp. 373-384, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
index vector, spectral coefficients, Built-in self test, compaction, syndrome |
15 | Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis |
Built-in sequential fault self-testing of array multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(3), pp. 449-460, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Kanad Chakraborty, Pinaki Mazumder |
A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 330-334, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
12 | Sunil R. Das, Chuan Jin, Liwu Jin, Mansour H. Assaf, Emil M. Petriu, Mehmet Sahinoglu |
Altera Max Plus II Development Environment in Fault Simulation and Test Implementation of Embedded Cores-Based Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWDC ![In: Distributed Computing - IWDC 2004, 6th International Workshop, Kolkata, India, December 27-30, 2004, Proceedings, pp. 353-360, 2004, Springer, 3-540-24076-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Wen-Ben Jone, Sunil R. Das |
A Stochastic Method for Defect Level Analysis of Pseudorandom Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 382-, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
defect level analysis, differential equation, VLSI testing, pseudorandom testing |
10 | Emil Gizdarski |
Detection of Delay Faults in Memory Address Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(4), pp. 381-387, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Built-In Self-Test, delay testing, stuck-open faults, RAM testing |
10 | Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray |
Deterministic Built-in Pattern Generation for Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 15(1-2), pp. 97-114, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Comma coding, pattern decoding, statistical encoding, BIST, Huffman coding, run-length encoding, embedded-core testing, sequential circuit testing |
10 | N. R. Shnidman, William H. Mangione-Smith, Miodrag Potkonjak |
On-line fault detection for bus-based field programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(4), pp. 656-666, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
10 | Dimitrios Kagaris, Spyros Tragoudas |
Avoiding linear dependencies in LFSR test pattern generators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(2), pp. 229-241, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
ATPG, BIST, LFSR, characteristic polynomials, pseudo-random testing |
10 | Shambhu J. Upadhyaya, John A. Thodiyil |
BIST PLAs, Pass or Fail - A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 724-727, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
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7 | Hari Vijay Venkatanarayanan, Michael L. Bushnell |
A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 581-588, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
7 | Omar I. Khan, Michael L. Bushnell |
Aliasing Analysis of Spectral Statistical Response Compaction Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 801-806, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
7 | Mansour H. Assaf, Rami S. Abielmona, Payam Abolghasem, Sunil R. Das, Emil M. Petriu, Voicu Groza, Mehmet Sahinoglu |
Implementation of Embedded Cores-Based Digital Devices in JBits Java Simulation Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: Intelligent Information Technology, 7th International Conference on Information Technology, CIT 2004, Hyderabad, India, December 20-23, 2004, Proceedings, pp. 315-325, 2004, Springer, 3-540-24126-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
7 | Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee |
An efficient BIST method for distributed small buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(4), pp. 512-515, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
7 | Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee |
An Efficient BIST Method for Small Buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 246-251, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
7 | Krishnendu Chakrabarty |
Zero-aliasing space compaction using linear compactors with bounded overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(5), pp. 452-457, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
7 | Karim Arabi, Bozena Kaminska |
Parametric and Catastrophic Fault Coverage of Analog Circuits in Oscillation-Test Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 166-171, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Oscillation-Test Method, Parametric Fault Coverage, Analog Testing, Mixed-Signal Circuits |
7 | Krishnendu Chakrabarty, John P. Hayes |
Test response compaction using multiplexed parity trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(11), pp. 1399-1408, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
7 | Wen-Ben Jone, Christos A. Papachristou |
A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(3), pp. 374-384, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
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