Search results for "built-in-self-testing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
52	Amit Laknaur, Sai Raghuram Durbha, Haibo Wang 0005	Built-In-Self-Testing Techniques for Programmable Capacitor Arrays.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	programmable capacitor array, built-in-self-testing, analog testing, field programmable analog array
45	Krishnendu Chakrabarty, John P. Hayes	Balance testing and balance-testable design of logic circuits.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	built-in self testing, design for testability, fault detection, fault coverage, testing methods
37	Nur A. Touba, Edward J. McCluskey	Applying two-pattern tests using scan-mapping.	VTS	1996	DBLP DOI BibTeX RDF	scan-mapping, combinational mapping logic, logic testing, built-in self test, built-in self-testing, fault coverage, delay faults, pseudo-random testing, deterministic testing, two-pattern tests
32	Amit Laknaur, Haibo Wang 0005	Built-In-Self-Testing Techniques for Programmable Capacitor Arrays.	ISQED	2005	DBLP DOI BibTeX RDF
32	Kwanghyun Kim, Dong Sam Ha, Joseph G. Tront	On using signature registers as pseudorandom pattern generators in built-in self-testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
32	Sandeep K. Venishetti, Ali Akoglu, Rahul Kalra	Hierarchical Built-in Self-testing and FPGA Based Healing Methodology for System-on-a-Chip.	AHS	2007	DBLP DOI BibTeX RDF
30	Imtiaz P. Shaik, Michael L. Bushnell	Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming .	VTS	1995	DBLP DOI BibTeX RDF	low overhead delay-fault BIST, constrained quadratic 0-1 programming, built-in self testing model, weighted signed graph balancing problem, VLSI, logic testing, delays, built-in self test, integrated circuit testing, logic design, automatic testing, integrated circuit design, quadratic programming, circuit design, digital integrated circuits, hazards and race conditions
30	Imtiaz P. Shaik, Michael L. Bushnell	A graph approach to DFT hardware placement for robust delay fault BIST.	VLSI Design	1995	DBLP DOI BibTeX RDF	graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI
29	Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya	Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults.	VLSI Design	1998	DBLP DOI BibTeX RDF	Built-in self-test, TPG, delay faults, robust testing, two-pattern tests
27	Jianxun Liu, Wen-Ben Jone	An efficient routing method for pseudo-exhaustive built-in self-testing of high-speed interconnects.	ICCD	2007	DBLP DOI BibTeX RDF
27	Shambhu J. Upadhyaya, Kewal K. Saluja	A new approach to the design of built-in self-testing PLAs for high fault coverage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
27	S. B. Tan, K. Totton, Keith Baker, Prab Varma, R. Porter	A Fast Signature Simulation Tool for Built-In Self-Testing Circuits.	DAC	1987	DBLP DOI BibTeX RDF
24	Marco Balboni, Davide Bertozzi	Transparent lifetime built-in self-testing of networks-on-chip through the selective non-concurrent testing of their communication channels.	AISTECS@HiPEAC	2017	DBLP DOI BibTeX RDF
24	Kim T. Le, Kewal K. Saluja	A Novel Approach for Testing Memories Using a Built-In Self Testing Technique.	ITC	1986	DBLP BibTeX RDF
23	Nicola Caselli, Alessandro Strano, Daniele Ludovici, Davide Bertozzi	Cooperative Built-in Self-Testing and Self-Diagnosis of NoC Bisynchronous Channels.	MCSoC	2012	DBLP DOI BibTeX RDF
23	Pinaki Mazumder	An Integrated Built-In Self-Testing and Self-Repair of VLSI/WSI Hexagonal Arrays.	ITC	1992	DBLP DOI BibTeX RDF
23	Josep Altet, André Ivanov, A. Wong	Thermal Testing of Analogue Integrated Circuits: A Case Study.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	test of analogue ICs, thermal analysis of ICs, built-in self-testing, CMOS technology, thermal testing
23	Josep Altet, Antonio Rubio 0001, Wilfrid Claeys, Stefan Dilhaire, Emmanuel Schaub, Hideo Tamamoto	Differential Thermal Testing: An Approach to its Feasibility.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	test of integrated circuits, built-in self testing, thermal testing, thermal sensors
23	Mohamed Soufi, Yvon Savaria, F. Darlay, Bozena Kaminska	Producing Reliable Initialization and Test of Sequential Circuits with Pseudorandom Vectors.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	full reset, initialization of sequential circuits, modelization of sequential circuits, Markov chain processes, Built-in self-testing, pseudorandom testing, testability measures, partial reset
23	C. L. Chen	Exhaustive Test Pattern Generation Using Cyclic Codes.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	exhaustive test pattern generation, punctured cyclic codes, VLSI, logic testing, built-in self testing, automatic testing, codes, linear feedback shift registers, VLSI circuits
23	Kozo Kinoshita, Kewal K. Saluja	Built-In Testing of Memory Using an On-Chip Compact Testing Scheme.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	weight-sensitive faults, random- access memory (RAM), Built-in self-testing (BIST), stuck-at faults, built-in testing (BIT), pattern-sensitive faults, hardware complexity
20	Krishnendu Chakrabarty, John P. Hayes	Cumulative balance testing of logic circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
19	Jürgen Maier 0002, Andreas Steininger	Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic.	CoRR	2020	DBLP BibTeX RDF
19	Chunmei Hu, Zhenyang Zhang, Yang Guo, Jingyan Xu	A Implementation for Built-in Self-Testing of RapidIO by JTAG.	ASICON	2019	DBLP DOI BibTeX RDF
19	Szu Huat Goh, Y. H. Chan, Zhao Lin, Jeffrey Lam	Concurrent built-in self-testing under the constraint of shared test resources and its test time reduction.	Integr.	2017	DBLP DOI BibTeX RDF
19	Gabriele Miorandi, Alberto Celin, Michele Favalli, Davide Bertozzi	A built-in self-testing framework for asynchronous bundled-data NoC switches resilient to delay variations.	NOCS	2016	DBLP DOI BibTeX RDF
19	Jürgen Maier 0002, Andreas Steininger	Online test vector insertion: A concurrent built-in self-testing (CBIST) approach for asynchronous logic.	DDECS	2014	DBLP DOI BibTeX RDF
19	Alessandro Strano, Nicola Caselli, Simone Terenzi, Davide Bertozzi	Optimising pseudo-random built-in self-testing of fully synchronous as well as multisynchronous networks-on-chip.	IET Comput. Digit. Tech.	2013	DBLP DOI BibTeX RDF
19	Alessandro Strano, Davide Bertozzi, Arnaud Grasset, Sami Yehia	Exploiting structural redundancy of SIMD accelerators for their built-in self-testing/diagnosis and reconfiguration.	ASAP	2011	DBLP DOI BibTeX RDF
19	Sunil R. Das, Altaf Hossain, Satyendra Biswas, Emil M. Petriu, Mansour H. Assaf, Wen-Ben Jone, Mehmet Sahinoglu	On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing.	IEEE Trans. Instrum. Meas.	2008	DBLP DOI BibTeX RDF
19	Miguel Angel Domínguez, José L. Ausín, J. Francisco Duque-Carrillo, Guido Torelli	A high-quality sine-wave oscillator for analog built-in self-testing.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Vinod Narayanan, Swaroop Ghosh, Wen-Ben Jone, Sunil R. Das	A built-in self-testing method for embedded multiport memory arrays.	IEEE Trans. Instrum. Meas.	2005	DBLP DOI BibTeX RDF
19	Omar I. Khan, Michael L. Bushnell	Spectral Analysis for Statistical Response Compaction During Built-In Self-Testing.	ITC	2004	DBLP DOI BibTeX RDF
19	Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni	Programmable built-in self-testing of embedded RAM clusters in system-on-chip architectures.	IEEE Commun. Mag.	2003	DBLP DOI BibTeX RDF
19	Sunil R. Das, Made Sudarma, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Krishnendu Chakrabarty, Mehmet Sahinoglu	Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets.	IEEE Trans. Instrum. Meas.	2003	DBLP DOI BibTeX RDF
19	Krishnendu Chakrabarty, Shivakumar Swaminathan	Built-in self testing of high-performance circuits using twisted-ring counters.	ISCAS	2000	DBLP DOI BibTeX RDF
19	Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray	Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets.	VTS	1998	DBLP DOI BibTeX RDF
19	O. A. Petlin, Stephen B. Furber	Built-In Self-Testing of Micropipelines.	ASYNC	1997	DBLP DOI BibTeX RDF	Built-in self-test, Design for test, Asynchronous design, Micropipelines
19	Krishnendu Chakrabarty, Jian Liu, Minyao Zhu, Brian T. Murray	Test Width Compression for Built-In Self Testing.	ITC	1997	DBLP DOI BibTeX RDF
19	Krishnendu Chakrabarty	Test response compaction for built-in self testing.		1995	RDF
19	Mashkuri Yaacob, Ibrahim Abubakr	A Built-in Self-Testing Bit Slice Microprocessor.	Applied Informatics	1994	DBLP BibTeX RDF
19	Franc Novak, Nenad Sutanovac, Roman Trobec	Built-in self testing of communications systems using ASIC technology.	Microprocess. Microsystems	1993	DBLP DOI BibTeX RDF
19	Scott Chiu, Christos A. Papachristou	A Built-In Self-Testing Approach for Minimizing Hardware Overhead.	ICCD	1991	DBLP DOI BibTeX RDF
19	Manoj Franklin, Kewal K. Saluja	Built-in Self-testing of Random-Access Memories.	Computer	1990	DBLP DOI BibTeX RDF
19	Kewal K. Saluja, Siew H. Sng, Kozo Kinoshita	Built-In Self-Testing RAM: A Practical Alternative.	IEEE Des. Test	1987	DBLP DOI BibTeX RDF
19	R. Kh. Latypov	Built-in Self-testing of Logic Circuits Using Imperfect Duplication.	FCT	1987	DBLP DOI BibTeX RDF
19	Sunil K. Jain, Charles E. Stroud	Built-in Self Testing of Embedded Memories.	IEEE Des. Test	1986	DBLP DOI BibTeX RDF
17	R. P. van Riessen, Hans G. Kerkhoff, A. Kloppenburg	Designing and Implementing an Architecture with Boundary Scan.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
15	Wen-Ben Jone, Anita Gleason	Analysis of Hamming count compaction scheme.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	index vector, spectral coefficients, Built-in self test, compaction, syndrome
15	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Built-in sequential fault self-testing of array multipliers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
15	Kanad Chakraborty, Pinaki Mazumder	A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs.	ED&TC	1997	DBLP DOI BibTeX RDF
12	Sunil R. Das, Chuan Jin, Liwu Jin, Mansour H. Assaf, Emil M. Petriu, Mehmet Sahinoglu	Altera Max Plus II Development Environment in Fault Simulation and Test Implementation of Embedded Cores-Based Sequential Circuits.	IWDC	2004	DBLP DOI BibTeX RDF
12	Wen-Ben Jone, Sunil R. Das	A Stochastic Method for Defect Level Analysis of Pseudorandom Testing.	VLSI Design	1998	DBLP DOI BibTeX RDF	defect level analysis, differential equation, VLSI testing, pseudorandom testing
10	Emil Gizdarski	Detection of Delay Faults in Memory Address Decoders.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	Built-In Self-Test, delay testing, stuck-open faults, RAM testing
10	Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray	Deterministic Built-in Pattern Generation for Sequential Circuits.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	Comma coding, pattern decoding, statistical encoding, BIST, Huffman coding, run-length encoding, embedded-core testing, sequential circuit testing
10	N. R. Shnidman, William H. Mangione-Smith, Miodrag Potkonjak	On-line fault detection for bus-based field programmable gate arrays.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
10	Dimitrios Kagaris, Spyros Tragoudas	Avoiding linear dependencies in LFSR test pattern generators.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	ATPG, BIST, LFSR, characteristic polynomials, pseudo-random testing
10	Shambhu J. Upadhyaya, John A. Thodiyil	BIST PLAs, Pass or Fail - A Case Study.	DAC	1990	DBLP DOI BibTeX RDF
7	Hari Vijay Venkatanarayanan, Michael L. Bushnell	A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits.	VLSI Design	2008	DBLP DOI BibTeX RDF
7	Omar I. Khan, Michael L. Bushnell	Aliasing Analysis of Spectral Statistical Response Compaction Techniques.	VLSI Design	2006	DBLP DOI BibTeX RDF
7	Mansour H. Assaf, Rami S. Abielmona, Payam Abolghasem, Sunil R. Das, Emil M. Petriu, Voicu Groza, Mehmet Sahinoglu	Implementation of Embedded Cores-Based Digital Devices in JBits Java Simulation Environment.	CIT	2004	DBLP DOI BibTeX RDF
7	Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee	An efficient BIST method for distributed small buffers.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
7	Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee	An Efficient BIST Method for Small Buffers.	VTS	1999	DBLP DOI BibTeX RDF
7	Krishnendu Chakrabarty	Zero-aliasing space compaction using linear compactors with bounded overhead.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
7	Karim Arabi, Bozena Kaminska	Parametric and Catastrophic Fault Coverage of Analog Circuits in Oscillation-Test Methodology.	VTS	1997	DBLP DOI BibTeX RDF	Oscillation-Test Method, Parametric Fault Coverage, Analog Testing, Mixed-Signal Circuits
7	Krishnendu Chakrabarty, John P. Hayes	Test response compaction using multiplexed parity trees.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
7	Wen-Ben Jone, Christos A. Papachristou	A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF