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Publication years (Num. hits)
1957-1987 (16) 1988-1992 (17) 1993-1995 (35) 1996-1997 (27) 1998-1999 (36) 2000 (16) 2001 (20) 2002 (21) 2003 (33) 2004 (32) 2005 (44) 2006 (42) 2007 (42) 2008 (34) 2009 (29) 2010 (17) 2011-2012 (33) 2013-2014 (34) 2015 (22) 2016-2017 (26) 2018 (20) 2019 (16) 2020-2021 (26) 2022 (21) 2023-2024 (14)
Publication types (Num. hits)
article(213) incollection(3) inproceedings(452) phdthesis(5)
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Found 673 publication records. Showing 673 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
102Kuan-Ta Chen, Polly Huang, Chun-Ying Huang, Chin-Laung Lei The impact of network variabilities on TCP clocking schemes. Search on Bibsonomy INFOCOM The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
94Sanjukta Bhanja, Sudeep Sarkar Thermal Switching Error Versus Delay Tradeoffs in Clocked QCA Circuits. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
81Baris Taskin, Bo Hong Improving Line-Based QCA Memory Cell Design Through Dual Phase Clocking. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
81Sanghyeon Baeg Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
81Gill A. Pratt, John Nguyen Distributed Synchronous Clocking. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
79Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki Safe clocking for the setup and hold timing constraints in datapath synthesis. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF ordered clocking, register assignment, datapath synthesis
79Gill A. Pratt, John Nguyen Distributed synchronous clocking. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF distributed synchronous clocking, hardware clock, synchronous processor, distributed error correction algorithm, global phase alignment, mode lock, k-ary Cartesian meshes, scalability, graph theory, timing, synchronisation, error correction, clocks, phase locked loops, digital systems, clock signals
77Kei-Yong Khoo, Alan N. Willson Jr. Single-transistor transparent-latch clocking. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF transparent-latch clocking, single-phase clocking scheme, CMOS VLSI designs, single NMOS transistor, allowable width, clock driver, dynamic buffer, architecture-driven voltage scaling, pipelining latches, latch-intensive architectures, filter structures, transposed-form FIR filter, VLSI, flip-flops, clocks, integrated circuit design, digital filters, FIR filters, power dissipation, CMOS digital integrated circuits
70Ganesh Venkataraman, Jiang Hu, Frank Liu 0001, Cliff C. N. Sze Integrated placement and skew optimization for rotary clocking. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
70Young-Jun Lee, Jong-Jin Lim, Yong-Bin Kim A Novel Clocking Strategy for Dynamic Circuits. Search on Bibsonomy ISQED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
68N. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar A VLSI array architecture with dynamic frequency clocking. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF VLSI array architecture, dynamic frequency clocking, linear VLSI array processor, DFLAP, power requirements, image processing, VLSI, throughput
60Vamsi Vankamamidi, Marco Ottavi, Fabrizio Lombardi Two-Dimensional Schemes for Clocking/Timing of QCA Circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
60Ganesh Venkataraman, Jiang Hu, Frank Liu 0001 Integrated Placement and Skew Optimization for Rotary Clocking. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
60Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner 42% power savings through glitch-reducing clocking strategy in a hearing aid application. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
60Irith Pomeranz, Sudhakar M. Reddy SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
58Saraju P. Mohanty, N. Ranganathan Energy-efficient datapath scheduling using multiple voltages and dynamic clocking. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF dynamic frequency clocking, low-power datapath synthesis, multiple voltage scheduling, time-constrained scheduling, High-level synthesis, resource-constrained scheduling
58Ahmed El-Amawy Clocking Arbitrarily Large Computing Structures Under Constant Skew Bound. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF constant skew bound, arbitrarily large computing structures, communicating cells, skew upper bound, maximum clocking rate, 2-D mesh framework, node design, nonplanar structures, parallel architectures, stability, hypercubes, network topology, synchronisation, hypercube networks, clocks, clock skew, global synchronization
56Stephen H. Unger, Chung-Jen Tan Clocking Schemes for High-Speed Digital Systems. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1986 DBLP  DOI  BibTeX  RDF clock pulses, edge-triggered flip-flops, edge tolerances, one-phase clocking, delays, timing, Clocking, digital systems, skew, latches, synchronous circuits
52Vamsi Vankamamidi, Marco Ottavi, Fabrizio Lombardi A Serial Memory by Quantum-Dot Cellular Automata (QCA). Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2008 DBLP  DOI  BibTeX  RDF memory architecture, emerging technologies, QCA
52Vamsi Vankamamidi, Marco Ottavi, Fabrizio Lombardi Tile-based design of a serial memory in QCA. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF quantum computing, memory architecture, emerging technologies, QCA
50Baris Taskin, Joseph Demaio, Owen Farell, Michael Hazeltine, Ryan Ketner Custom topology rotary clock router with tree subnetworks. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Resonant rotary clocking, clock network design, multiphase synchronization, clock skew
50Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi Simultaneous peak and average power minimization during datapath scheduling for DSP processors. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF average power, datapath scheduling, dynamic frequency clocking, high-level synthesis, peak power, multiple voltages
50William L. Bradley, Ranga Vemuri Transformations for functional verification of synthesized designs. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF low-level functional verification, synthesized designs, clocking mechanisms, provably equivalent model, hierarchical network of modules, reduced state set, de-phase transform, align transform, algorithm, formal verification, transforms, transforms, logic CAD, clocks, hierarchical system, reachable states
49Vinayak Honkote, Baris Taskin Zero clock skew synchronization with rotary clocking technology. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
49Lin Zhang, Aaron Carpenter, Berkehan Ciftcioglu, Alok Garg, Michael C. Huang 0001, Hui Wu Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
49Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications. Search on Bibsonomy PATMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
49Christos A. Papachristou, Mehrdad Nourani, Mark Spining A multiple clocking scheme for low-power RTL design. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
49Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
49Marios D. Dikaiakos, Kenneth Steiglitz Comparison of tree and straight-line clocking for long systolic arrays. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
49Nohbyung Park, Alice C. Parker Synthesis of optimal clocking schemes. Search on Bibsonomy DAC The full citation details ... 1985 DBLP  DOI  BibTeX  RDF
47Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy 0001 Low-power process-variation tolerant arithmetic units using input-based elastic clocking. Search on Bibsonomy ISLPED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF elastic clocking, process tolerant, low power
47Erland Nilsson, Johnny Öberg Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking. Search on Bibsonomy CODES+ISSS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF hot-potato, pseudochronous, network on chip, mesh, clocking, GALS, GPLS
42Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson Synchronization of pipelines. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
40Vinayak Honkote, Baris Taskin PEEC based parasitic modeling for power analysis on custom rotary rings. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF resonant clocking, simulation, modeling, interconnect
40Sultan Al-Hinai, Lynn Margaret Batten, Bernard D. Colbert, Kenneth Koon-Ho Wong Algebraic Attacks on Clock-Controlled Stream Ciphers. Search on Bibsonomy ACISP The full citation details ... 2006 DBLP  DOI  BibTeX  RDF irregular clocking, stream cipher, linear feedback shift register, algebraic attack, clock control
40Hans M. Jacobson Improved clock-gating through transparent pipelining. Search on Bibsonomy ISLPED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF adaptive pipeline depth, dynamic pipeline scaling, optimal pipeline clocking, pipeline stage unification, transparent pipeline, low power, high performance, microarchitecture, circuits, clock gating
40Eric Filiol Decimation Attack of Stream Ciphers. Search on Bibsonomy INDOCRYPT The full citation details ... 2000 DBLP  DOI  BibTeX  RDF sequence decimation, multiple clocking, Stream cipher, linear feedback shift register, correlation attack, fast correlation attack
39Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki Safe clocking register assignment in datapath synthesis. Search on Bibsonomy ICCD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
39Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner Two-phase resonant clocking for ultra-low-power hearing aid applications. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
39Nikola Nedovic, Vojin G. Oklobdzija Dual-edge triggered storage elements and clocking strategy for low-power systems. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39Min-Gyu Kim, Gil-Cho Ahn, Un-Ku Moon An improved algorithmic ADC clocking scheme. Search on Bibsonomy ISCAS (1) The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
39Joycee Mekie, Supratik Chakraborty, Dinesh K. Sharma Evaluation of pausible clocking for interfacing high speed IP cores in GALS Framework. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
39Ramalingam Sridhar System-on-Chip (SoC): Clocking and Synchronization Issues. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
39Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy 0001 Energy recovery clocking scheme and flip-flops for ultra low-energy applications. Search on Bibsonomy ISLPED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF flip-flop, clock, clock tree, energy recovery, adiabatic
39Saraju P. Mohanty, N. Ranganathan, Vamsi Krishna Datapath Scheduling using Dynamic Frequency Clocking. Search on Bibsonomy ISVLSI The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
39Oswaldo Cadenas, Graham M. Megson A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs. Search on Bibsonomy FPL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
39Piet van Remortel, Tom Lenaerts, Bernard Manderick The Robustness of Small Developped SBlock Circuits Using Different Clocking Schemes. Search on Bibsonomy Evolvable Hardware The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
39Claude Arm, Jean-Marc Masgonty, Christian Piguet Double-Latch Clocking Scheme for Low-Power I.P. Cores. Search on Bibsonomy PATMOS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
39Young-Su Kwon, Bong-Il Park, In-Cheol Park, Chong-Min Kyung A New Single-Clock Flip-Clop for Half-Swing Clocking. Search on Bibsonomy ASP-DAC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
39Vamsi Krishna, N. Ranganathan, Narayanan Vijaykrishnan Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages. Search on Bibsonomy VLSI Design The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
39Mohamed Nekili, Guy Bois, Yvon Savaria Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
39Kenneth Y. Yun, Ryan P. Donohue Pausible Clocking: A First Step Toward Heterogeneous Systems. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
37Rajeswari Devadoss, Kolin Paul, M. Balakrishnan Clocking-Based Coplanar Wire Crossing Scheme for QCA. Search on Bibsonomy VLSI Design The full citation details ... 2010 DBLP  DOI  BibTeX  RDF Quantum Cellular Automata, Wire Crossing, Coplanar, Low Power, Clocking, Crossover, QCA, Quantum-dot Cellular Automata
37Michael T. Niemier, M. Alam, Xiaobo Sharon Hu, Gary H. Bernstein, Wolfgang Porod, M. Putney, J. DeAngelis Clocking structures and power analysis for nanomagnet-based logic devices. Search on Bibsonomy ISLPED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF magnetic logic, nanotechnology, clocking, QCA
37Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija Conditional pre-charge techniques for power-efficient dual-edge clocking. Search on Bibsonomy ISLPED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF clocked storage elements, dual edge-triggered flip-flop, power consumption, clocking, clock distribution
37Luis F. G. Sarmenta, Gill A. Pratt, Stephen A. Ward Rational clocking [digital systems design]. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF rational clocking, independently-clocked digital subsystems, finite probability, phase relationship, delays, delays, logic design, logic design, synchronisation, clocks, minimisation of switching nets, digital systems design, synchronization failure
37Nohbyung Park, Alice C. Parker Theory of Clocking for Maximum Execution Overlap of High-Speed Digital Systems. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1988 DBLP  DOI  BibTeX  RDF maximum execution overlap, high-speed digital systems, performance evaluation, data dependencies, clocking, clocks, digital systems, branching, resource conflicts
36Fahim U. Rahman, Visvesh Sathe 0001 Quasi-Resonant Clocking: Continuous Voltage-Frequency Scalable Resonant Clocking System for Dynamic Voltage-Frequency Scaling Systems. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
36David Trachtenherz AutoFocus Stream Processing for Single-Clocking and Multi-Clocking Semantics. Search on Bibsonomy Arch. Formal Proofs The full citation details ... 2011 DBLP  BibTeX  RDF
36Joseph N. Kozhaya, Phillip J. Restle, Haifeng Qian Myth busters: Microprocessor clocking is from Mars, ASICs clocking is from Venus. Search on Bibsonomy ICCAD The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
36Hirotsugu Kojima, Satoshi Tanaka, Katsuro Sasaki Half-swing clocking scheme for 75% power saving in clocking circuitry. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
31Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero, Alexander V. Veidenbaum Power-aware load balancing of large scale MPI applications. Search on Bibsonomy IPDPS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
31Xiaojun Ma, Jing Huang 0001, Fabrizio Lombardi A model for computing and energy dissipation of molecular QCA devices and circuits. Search on Bibsonomy ACM J. Emerg. Technol. Comput. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF thermodynamic analysis, emerging technology, reversible computing, QCA
31Vinayak Honkote, Baris Taskin Custom rotary clock router. Search on Bibsonomy ICCD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
31Zhenxin Sun, Weng-Fai Wong, Yongxin Zhu 0001, Santhosh Kumar Pilakkat Design of clocked circuits using UML. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
31Zachary D. Patitz, Nohpill Park, Minsu Choi, Fred J. Meyer QCA-Based Majority Gate Design under Radius of Effect-Induced Faults. Search on Bibsonomy DFT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
31Oswaldo Cadenas, Graham M. Megson Improving mW/MHz Ratio in FPGAs Pipelined Designs. Search on Bibsonomy DSD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
31Xiaohong Jiang 0001, Susumu Horiguchi Optimization of Wafer Scale H-Tree Clock Distribution Network Based on a New Statistical Skew Model. Search on Bibsonomy DFT The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
31Mohit Aron, Peter Druschel Soft timers: efficient microsecond software timer support for network processing. Search on Bibsonomy SOSP The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
31Maheshwar Umasankar, Ahmed El-Amawy Generalized Algorithms for Systematic Synthesis of Branch-and-Combine Clock Networks for Meshes, Tori, and Hypercubes. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF skew bound, Branch-and-Combine, feature cycle length, hypercube, mesh, tile, torus, Clock skew, clock network
29Keisuke Inoue, Mineo Kaneko A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF ordered clocking, resource assignment, datapath synthesis
29Baris Taskin, Andy Chiu, Jonathan Salkind, Daniel Venutolo A shift-register-based QCA memory architecture. Search on Bibsonomy ACM J. Emerg. Technol. Comput. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF clocking, Quantum-dot cellular automata, memory design
29Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi ILP models for simultaneous energy and transient power minimization during behavioral synthesis. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF average power, cycle difference power, datapath scheduling, dynamic frequency clocking, multicycling, multiple supply voltages, peak power differential, Peak power
29Hao Jiang, Constantinos Dovrolis Why is the internet traffic bursty in short time scales? Search on Bibsonomy SIGMETRICS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF ON-OFF model, TCP pacing, TCP self-clocking, wavelet-based multiresolution analysis, traffic modeling, burstiness
29Slobodan Petrovic, Amparo Fúster-Sabater Clock Control Sequence Reconstruction in the Ciphertext Only Attack Scenario. Search on Bibsonomy ICICS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Irregular clocking, Cryptanalysis, Edit distance, Correlation attack, Directed search
29Kevin Chen, Leonie Ruth Simpson, Matthew Henricksen, William Millan, Ed Dawson A Complete Divide and Conquer Attack on the Alpha1 Stream Cipher. Search on Bibsonomy ICISC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Alpha1, irregular clocking, divide and conquer attack, Cryptanalysis, stream cipher
29Jovan Dj. Golic Correlation Analysis of the Shrinking Generator. Search on Bibsonomy CRYPTO The full citation details ... 2001 DBLP  DOI  BibTeX  RDF unconstrained irregular clocking, Stream ciphers, fast correlation attacks, posterior probabilities
29Chih-Tung Chen, Kayhan Küçükçakar High-level scheduling model and control synthesis for a broad range of design applications. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF multi-phase clocking, relative scheduling, architectural power optimization, high-level synthesis, pipelining, multi-threading, behavioral synthesis, control synthesis, architectural synthesis, scheduling model
29Joe G. Xi, Wayne Wei-Ming Dai Jitter-tolerant clock routing in two-phase synchronous systems. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Deferred-Merge Embedding framework, clock jitter, clock tree cost, jitter-tolerance, jitter-tolerant clock routing, near-zero skew, nonoverlapping interval, safety margin, system operating conditions, two-phase clocking, two-phase jitter-tolerant useful-skew tree, two-phase synchronous systems, simulated annealing, manufacturing, jitter, zero skew
29Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin Design tradeoffs in high speed multipliers and FIR filters. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF high speed multipliers, high speed FIR filters, modified Booth recoding, pipeline granularity, transistor count, activity factor reduction, guarded evaluation, gate-level pipelining, half-bit level pipelining, bit-level pipelining, delay, clocking, digital filters, FIR filters, multiplying circuits, power dissipation, design tradeoffs, pipeline arithmetic, operation speed
29Manish Pandey, Alok Jain, Randal E. Bryant, Derek L. Beatty, Gary York, Samir Jain Extraction of finite state machines from transistor netlists by symbolic simulation. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF finite state machine extraction, transistor netlists, clock level finite state machines, gate level representation, circuit clocking, output timing, simulation patterns, next state, output function, equivalent FSM, static storage structures, time multiplexed inputs, time multiplexed outputs, finite state machines, logic design, logic CAD, circuit analysis computing, FSMs, symbolic simulation, symbolic simulator, Ordered Binary Decision Diagrams
29Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray Concurrent timing optimization of latch-based digital systems. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF concurrent timing optimization, latch-based digital systems, digital system timing, intentional clock skew, latch-based designed systems, multi-phase clocking, resynchronization, latches insertion, optimisation, timing, logic design, flip-flops, retiming, mixed integer linear program, race conditions, integrated framework, wave pipelining, hazards and race conditions, clock period
29W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron
28Flavio Carbognani, Luca Henzen Cross-over current suppressing latch compared to state-of-the-art for low-power low-frequency applications with resonant clocking. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF flipflops, low power design, clock, digital circuits, adiabatic
28Krister Jacobsson, Lachlan L. H. Andrew, Ao Tang, Karl Henrik Johansson, Håkan Hjalmarsson, Steven H. Low ACK-Clocking Dynamics: Modelling the Interaction between Windows and the Network. Search on Bibsonomy INFOCOM The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
28Chih-Yu Wen, Robin D. Morris, William A. Sethares Distance Estimation Using Bidirectional Communications Without Synchronous Clocking. Search on Bibsonomy IEEE Trans. Signal Process. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
28Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud Thermally robust clocking schemes for 3D integrated circuits. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
28Chunsheng Liu, Vikram Iyengar Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
28Chunsheng Liu, Vikram Iyengar, Dhiraj K. Pradhan Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking. Search on Bibsonomy VTS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
28Mahdi Nazm Bojnordi, Nariman Moezzi Madani, Mehdi Semsarzadeh, Ali Afzali-Kusha An Efficient Clocking Scheme for On-Chip Communications. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
28Scott Fairbanks, Simon W. Moore Self-Timed Circuitry for Global Clocking. Search on Bibsonomy ASYNC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
28Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression. Search on Bibsonomy Asian Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
28Wei Ling, Yvon Savaria Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
28Chunsheng Liu, Vikram Iyengar, Jiangfan Shi, Érika F. Cota Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking. Search on Bibsonomy VTS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
28Kirti Joshi, Eric W. MacDonald Reduction of Instantaneous Power by Ripple Scan Clocking. Search on Bibsonomy VTS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
28Shih-Chang Hsia A High Speed Multi -Input Comparator with Clocking-Charge Based for Low-Power Systems. Search on Bibsonomy IWSOC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
28Vojin G. Oklobdzija Clocking and Clocked Storage Elements in Multi-GHz Environment. Search on Bibsonomy PATMOS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
28Arindam Mukherjee 0001, Kai Wang 0011, Lauren Hui Chen, Malgorzata Marek-Sadowska Sizing Power/Ground Meshes for Clocking and Computing Circuit Components. Search on Bibsonomy DATE The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
28Kenneth Y. Yun, Ayoob E. Dooply Optimal Evaluation Clocking of Self-Resetting Domino Pipelines. Search on Bibsonomy ASP-DAC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
28Kei-Yong Khoo, Chao-Liang Chen, Alan N. Willson Jr. A CMOS pipelined carry-save array using true single-phase single-transistor-latch clocking. Search on Bibsonomy ISCAS (1) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
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