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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 239 occurrences of 111 keywords
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Results
Found 182 publication records. Showing 182 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
105 | Zachary D. Patitz, Nohpill Park |
Modeling and Evaluation of Threshold Defect Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 211-219, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
83 | Mehdi Baradaran Tahoori |
Low-overhead defect tolerance in crossbar nanoarchitectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 5(2), pp. 11:1-11:24, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
reconfigurable architectures, nanotechnology, Defect tolerance |
82 | Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi |
On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 96-104, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
79 | Zhanglei Wang, Krishnendu Chakrabarty |
Built-in Self-test and Defect Tolerance in Molecular Electronics-based Nanofabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(2-3), pp. 145-161, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
nanofabric, CAEN, chemically assembled, reconfiguration, BIST, nanotechnology, defect tolerance, molecular electronics |
79 | Prasanna Sundararajan, Steve Guccione |
Run-Time defect tolerance using JBits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001, pp. 193-198, 2001, ACM, 1-58113-341-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Java, FPGA, cores, defect tolerance, run-time reconfiguration |
75 | Maryam Ashouei, Adit D. Singh, Abhijit Chatterjee |
Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 27-32, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
72 | S. K. Tewksbury |
Challenges Facing Practical DFT for MEMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 11-17, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Microelectromechanical systems, microsystems technologies, fault tolerance, defect tolerance |
71 | Reza M. Rad, Mohammad Tehranipoor |
A Reconfiguration-based Defect Tolerance Method for Nanoscale Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 107-118, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Nanoscale Devices, Fault Tolerance, Test, Reconfiguration, Redundancy, Crossbar |
63 | Vijay K. Jain, Glenn H. Chapman |
Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 157-165, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
3D Heterogeneous sensor, redundancy and reconfiguration, energy economization, heterogeneous SOC, J-platform, defect tolerance |
60 | Tao Xu 0002, Krishnendu Chakrabarty |
Integrated droplet routing and defect tolerance in the synthesis of digital microfluidic biochips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 4(3), pp. 11:1-11:24, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Physical design automation, microfluidics, biochips, module placement |
60 | Xiaobo Sharon Hu, Alexander Khitun, Konstantin K. Likharev, Michael T. Niemier, Mingqiang Bao, Kang L. Wang |
Design and defect tolerance beyond CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 223-230, 2008, ACM, 978-1-60558-470-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
cmol, nanotechnology, defect tolerance, qca, spin wave |
60 | Arvind Kumar, Sandip Tiwari |
Defect tolerance for nanocomputer architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 89-96, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
wire length estimation, FPGA, reliability, reconfigurability, defect tolerance, nanoelectronics, Rent's rule, nanocomputing |
59 | Zhan Chen, Israel Koren |
Techniques for Yield Enhancement of VLSI Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France, pp. 222-229, 1995, IEEE Computer Society, 0-8186-7109-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
VLSI yield, VLSI adder, defect tolerance, VLSI layout |
58 | Aiman H. El-Maleh, Bashir M. Al-Hashimi, Aissa Melouki |
Transistor-level based defect tolerance for reliable nanoelectronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICCSA ![In: The 6th ACS/IEEE International Conference on Computer Systems and Applications, AICCSA 2008, Doha, Qatar, March 31 - April 4, 2008, pp. 53-60, 2008, IEEE Computer Society, 978-1-4244-1967-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
56 | Fei Su, Krishnendu Chakrabarty |
Defect Tolerance Based on Graceful Degradation and Dynamic Reconfiguration for Digital Microfluidics-Based Biochips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 2944-2953, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
56 | Fei Su, Krishnendu Chakrabarty |
Defect Tolerance for Gracefully-Degradable Microfluidics-Based Biochips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 321-326, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
55 | Claude Thibeault, Yvon Savaria, Jean-Louis Houle |
Test quality of hierarchical defect-tolerant integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(1), pp. 93-102, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
defect level, fault coverage, defect tolerance, defect modeling, Combinatorial analysis |
54 | Jing Huang 0001, Mariam Momenzadeh, Fabrizio Lombardi |
Defect tolerance of QCA tiles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 774-779, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
emerging technologies, defect tolerance, QCA |
53 | Reza M. Rad, Mohammad Tehranipoor |
SCT: A novel approach for testing and configuring nanoscale devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 4(3), pp. 14:1-14:24, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Configuration and testing, reconfigurable nanoscale devices, fault tolerance, crossbar, nanowire |
52 | Hongbin Sun 0001, Nanning Zheng 0001, Tong Zhang 0002 |
Realization of L2 Cache Defect Tolerance Using Multi-bit ECC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 254-262, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
51 | Rahul Jain 0004, Anindita Mukherjee, Kolin Paul |
Defect-Aware Design Paradigm for Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 91-96, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
48 | Arvind Kumar, Sandip Tiwari |
Testing and Defect Tolerance: A Rent's Rule Based Analysis and Implications on Nanoelectronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 280-288, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
47 | Kristian Granhaug, Snorre Aunet |
Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 157-163, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Subthreshold CMOS, Output-wired redundancy, Yield and defect tolerance |
47 | Israel Koren, Zahava Koren |
Analysis of a Hybrid Defect-Tolerance Scheme for High-Density Memory ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France, pp. 166-174, 1997, IEEE Computer Society, 0-8186-8168-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Memory IC, yield, defect-tolerance |
45 | Kouhi Shinohara, Minoru Watanabe |
Defect tolerance of holographic configurations in ORGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
45 | Glenn H. Chapman, Vijay K. Jain |
Defect Tolerance for a Capacitance Based Nanoscale Biosensor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 220-228, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
45 | S. Ramsundar, Ahmad A. Al-Yamani, Dhiraj K. Pradhan |
Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 807-813, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Mehdi Baradaran Tahoori |
Application-independent defect-tolerant crossbar nano-architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 730-734, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
41 | Yoonjae Huh, Yoon-Hwa Choi |
Module Grouping for Defect Tolerance in Nanoscale Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 16-23, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
40 | Teijiro Isokawa, Shin'ya Kowada, Ferdinand Peper, Naotake Kamiura, Nobuyuki Matsui |
Online isolation of defects in cellular nanocomputers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Frontiers Comput. Sci. China ![In: Frontiers Comput. Sci. China 1(4), pp. 397-406, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
radom fly, cellular automata, asynchronous, nanotechnology, defect tolerance |
39 | Vinu Vijay Kumar, John C. Lach |
Heterogeneous Redundancy for Fault and Defect Tolerance with Complexity Independent Area Overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 571-, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
39 | Mahim Mishra, Seth Copen Goldstein |
Defect Tolerance at the End of the Roadmap. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 1201-1210, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
39 | W. Bruce Culbertson, Rick Amerson, Richard J. Carter, Philip Kuekes, Greg Snider |
Defect tolerance on the Teramac custom computer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 16-18 April 1997, Napa Valley, CA, USA, pp. 116-124, 1997, IEEE Computer Society, 0-8186-8159-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
38 | Konstantin Likharev |
Defect-Tolerant Hybrid CMOS/Nanoelectronic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 504-504, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Teijiro Isokawa, Shin'ya Kowada, Yousuke Takada, Ferdinand Peper, Naotake Kamiura, Nobuyuki Matsui |
Defect-Tolerance in Cellular Nanocomputers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
New Gener. Comput. ![In: New Gener. Comput. 25(2), pp. 171-199, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Cellular Automata, Configurability, Asynchronous, Nanotechnology, Defect Tolerance |
37 | Mehdi Baradaran Tahoori |
Application-independent defect tolerance of reconfigurable nanoarchitectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 2(3), pp. 197-218, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
reconfigurable architectures, nanotechnology, Defect tolerance |
37 | Fausto Distante, Mariagiovanna Sami, Renato Stefanelli |
Array partitioning to achieve defect tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 487-491, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
array partitioning, processing arrays, run time faults, reconfiguration techniques, architectural regularity, interconnection channel width, reconfiguration efficiency, partitioning approach, critical fault patterns, fault tolerance, redundancy, reconfigurable architectures, survival, defect tolerance, path length |
36 | Tao Xu 0002, Krishnendu Chakrabarty, Fei Su |
Defect-Aware Synthesis of Droplet-Based Microfluidic Biochips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 647-652, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Xiaohong Jiang 0001, Susumu Horiguchi, Yue Hao |
Predicting the Yield Efficacy of a Defect-Tolerant Embedded Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings, pp. 30-, 2000, IEEE Computer Society, 0-7695-0719-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
36 | Marco Broglia, Giacomo Buonanno, Mariagiovanna Sami, M. Selvini |
Designing for Yield: A Defect-Tolerant Approach to High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 312-317, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Slice, Defect Tolerance, Data-Path |
35 | Mohammad Tehranipoor, Reza M. Rad |
Defect Tolerance for Nanoscale Crossbar-Based Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(6), pp. 549-559, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Mehdi Baradaran Tahoori |
BISM: built-in self map for hybrid crossbar nano-architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 153-156, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
crossbar array, emerging nanotechnologies, logic mapping |
33 | Lei Zhang 0008, Yinhe Han 0001, Qiang Xu 0001, Xiaowei Li 0001 |
Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 891-896, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Shu Li, Tong Zhang 0002 |
Exploratory study on circuit and architecture design of very high density diode-switch phase change memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 424-429, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
32 | Vamsi Vankamamidi, Fabrizio Lombardi |
Design of defect tolerant tile-based QCA circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 237-242, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
missing cell, simulation, qca |
32 | Timothy J. Dysart, Peter M. Kogge |
System Reliabilities When Using Triple Modular Redundancy in Quantum-Dot Cellular Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 72-80, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Reza M. Rad, Mohammad Tehranipoor |
SCT: An Approach For Testing and Configuring Nanoscale Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 370-377, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Mehdi Baradaran Tahoori |
Defects, Yield, and Design in Sublithographic Nano-electronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 3-11, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Bogdan M. Maziarz, Vijay K. Jain |
Automatic Reconfiguration and Yield of the TESH Multicomputer Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(8), pp. 963-972, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
TESH, fault-tolerance, routing, VLSI, Interconnection networks, reconfiguration, redundancy, yield, hierarchical networks, manufacturing defects, parallel computing systems, ULSI |
30 | V. Hecht, Karsten Rönner, Peter Pirsch |
A defect-tolerant systolic array implementation for real time image processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 5(1), pp. 37-47, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
29 | Wei Xu 0021, Yiran Chen 0001, Xiaobin Wang, Tong Zhang 0002 |
Improving STT MRAM storage density through smaller-than-worst-case transistor sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 87-90, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
STT MRAM, defect tolerance, transistor sizing |
29 | Jing Huang 0001, Mariam Momenzadeh, Fabrizio Lombardi |
On the Tolerance to Manufacturing Defects in Molecular QCA Tiles for Processing-by-wire. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(2-3), pp. 163-174, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
processing by wire, emerging technologies, defect tolerance, QCA |
28 | Kristian Granhaug, Snorre Aunet |
Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 20-28, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Mariam Momenzadeh, Jing Huang 0001, Fabrizio Lombardi |
Defect Characterization and Tolerance of QCA Sequential Devices and Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 199-207, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Debayan Bhaduri, Sandeep K. Shukla |
NANOPRISM: a tool for evaluating granularity vs. reliability trade-offs in nano architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 109-112, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
CTMR, defect-tolerant architecture, nanotechnology, granularity, TMR, PRISM |
23 | Shuo Wang, Jianwei Dai, Lei Wang 0003 |
Defect-tolerant digital filtering with unreliable molecular electronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2008, October 8-10, 2008, Washington, D.C. Metro Area, USA, pp. 194-199, 2008, IEEE, 978-1-4244-2924-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Hayssam El-Razouk, Zine Abid |
A New Transistor-Redundant Voter for Defect-Tolerant Digital Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 1078-1081, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Shanrui Zhang, Minsu Choi, Nohpill Park |
Modeling Yield of Carbon-Nanotube/Silicon-Nanowire FET-Based Nanoarray Architecture with h-hot Addressing Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 356-364, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Gethin Norman, David Parker 0001, Marta Z. Kwiatkowska, Sandeep K. Shukla |
Evaluating the Reliability of Defect-Tolerant Architectures for Nanotechnology with Probabilistic Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 907-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Michael Crocker, Xiaobo Sharon Hu, Michael T. Niemier |
Defects and faults in QCA-based PLAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 5(2), pp. 8:1-8:27, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
logic mapping, Nanotechnology, faults, defects, quantum-dot cellular automata |
21 | Somnath Paul, Swarup Bhunia |
MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 77-82, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Tadashi Kunieda, Teijiro Isokawa, Ferdinand Peper, Ayumu Saitoh, Naotake Kamiura, Nobuyuki Matsui |
Reconfiguring Circuits Around Defects in Self-Timed Cellular Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACRI ![In: Cellular Automata, 8th International Conference on Cellular Aotomata for Reseach and Industry, ACRI 2008, Yokohama, Japan, September 23-26, 2008. Proceedings, pp. 200-209, 2008, Springer, 978-3-540-79991-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Dmitri B. Strukov, Konstantin K. Likharev |
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 131-140, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
integrated hybrid circuits, architecture, programmable logic, nanoelectronics, programmable interconnect |
21 | Teijiro Isokawa, Shin'ya Kowada, Ferdinand Peper, Naotake Kamiura, Nobuyuki Matsui |
Online Marking of Defective Cells by Random Flies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACRI ![In: Cellular Automata, 7th International Conference on Cellular Automata, for Research and Industry, ACRI 2006, Perpignan, France, September 20-23, 2006, Proceedings, pp. 347-356, 2006, Springer, 3-540-40929-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Abderrahim Doumar, Satoshi Kaneko, Hideo Ito |
Defect and Fault Tolerance FPGAs by Shifting the Configuration Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 377-385, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | John R. Samson Jr., Wilfrido Alejandro Moreno, Fernando J. Falquez |
Validating fault tolerant designs using laser fault injection (LFI). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France, pp. 175-185, 1997, IEEE Computer Society, 0-8186-8168-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
fault tolerant designs validation, laser fault injection, VHSIC technology, in situ testing, transient error conditions, VLSI, faults, automated testing, transient, VLSI technology |
19 | Xiaojun Ma, Masoud Hashempour, Lei Wang 0003, Fabrizio Lombardi |
Manufacturing yield of QCA circuits by synthesized DNA self-assembled templates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 275-280, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
design, manufacturing, nanotechnology, defect tolerance |
19 | Siddhartha Datta, Bharat Joshi, Arun Ravindran, Arindam Mukherjee 0001 |
Efficient parallel testing and diagnosis of digital microfluidic biochips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 5(2), pp. 10:1-10:17, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Microfluidic biochip, droplet flooding, fault tolerance, testing, reconfigurability, defect tolerance, multiple faults, microfluidics |
19 | Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Rötteler, Niraj K. Jha |
A hybrid nano-CMOS architecture for defect and fault tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 5(3), pp. 14:1-14:26, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
nanotechnology, Defect tolerance, nanowires |
19 | Raphael Rubin, André DeHon |
Choose-your-own-adventure routing: lightweight load-time defect avoidance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 23-32, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
bitstream load, in-field repair, defect tolerance, alternatives, programmable interconnect |
19 | Salvatore Pontarelli, Marco Ottavi, Vamsi Vankamamidi, Gian Carlo Cardarilli, Fabrizio Lombardi, Adelio Salsano |
Analysis and Evaluations of Reliability of Reconfigurable FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 105-116, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, Reliability, Fault model, Defect tolerance |
19 | Michael Leuchtenburg, Pritish Narayanan, Teng Wang, Csaba Andras Moritz |
Impact of Process Variation in Fault-Resilient Streaming Nanoprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NanoNet ![In: Nano-Net - Third International ICST Conference, NanoNet 2008, Boston, MA, USA, September 14-16, 2008, Revised Selected Papers, pp. 26-27, 2008, Springer, 978-3-642-02426-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
nanoscale processor, process variation, defect tolerance |
19 | Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang 0011, Michael Orshansky |
Architecting a reliable CMP switch architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 4(1), pp. 2, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
CMP switch, reliability, defect-tolerance |
19 | Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck |
A self-organizing defect tolerant SIMD architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 3(2), pp. 10, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Self-organizing, SIMD, data parallel, DNA, defect tolerance, nanocomputing, bit-serial |
19 | Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck, Daniel J. Sorin |
NANA: A nano-scale active network architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 2(1), pp. 1-30, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Accumulator ISA, defect isolation, reverse path forwarding, active network, DNA, defect tolerance, self-assembly, carbon nanotube, nanoelectronics, nanocomputing |
19 | Song Peng, Rajit Manohar |
Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 159-164, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
asynchronous circuits, yield, defect tolerance, 3D integration, self-reconfiguration |
19 | Jaidev P. Patwardhan, Vijeta Johri, Chris Dwyer, Alvin R. Lebeck |
A defect tolerant self-organizing nanoscale SIMD architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2006, San Jose, CA, USA, October 21-25, 2006, pp. 241-251, 2006, ACM, 1-59593-451-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
self-organizing, SIMD, data parallel, DNA, defect tolerance, nanocomputing, bit-serial |
19 | Mahim Mishra, Timothy J. Callahan, Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein, Mihai Budiu |
Tartan: evaluating spatial computation for whole program execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2006, San Jose, CA, USA, October 21-25, 2006, pp. 163-174, 2006, ACM, 1-59593-451-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
low power, asynchronous circuits, reconfigurable hardware, defect tolerance, spatial computation, dataflow machine |
19 | André DeHon |
Nanowire-based programmable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 1(2), pp. 109-162, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Manhattan mesh, stochastic construction, sublithographic architecture, programmable logic arrays, Defect tolerance, nanowires, programmable interconnect |
19 | Rajesh K. Gupta 0001 |
Nanotechnology: Where science of the small meets math of the large. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(4), pp. 289, 294, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
scalability, integration, reconfiguration, nanotechnology, defect tolerance |
19 | Chen He, Margarida F. Jacome, Gustavo de Veciana |
A Reconfiguration-Based Defect-Tolerant Design Paradigm for Nanotechnologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(4), pp. 316-326, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
probabilistic design, reconfiguration, Nanotechnologies, defect tolerance |
19 | Mariam Momenzadeh, Marco Ottavi, Fabrizio Lombardi |
Modeling QCA Defects at Molecular-level in Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 208-216, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
fault model, emerging technology, defect tolerance, QCA |
19 | Fei Su, Krishnendu Chakrabarty |
Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 825-830, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
synthesis, placement, defect tolerance, microfluidics, biochip |
19 | Marco Ottavi, Xiaopeng Wang, Fred J. Meyer, Fabrizio Lombardi |
Simulation of reconfigurable memory core yield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 136-140, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Markov chain, manufacturability, yield, defect tolerance |
19 | Margarida F. Jacome, Chen He, Gustavo de Veciana, Stephen Bijansky |
Defect tolerant probabilistic design paradigm for nanotechnologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 596-601, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
probabilistic design, nanotechnologies, defect tolerance |
19 | Fred J. Meyer, Nohpill Park |
Predicting Defect-Tolerant Yield in the Embedded Core Context. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(11), pp. 1470-1479, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Yield, integrated circuit, defect tolerance, embedded core |
19 | Thomas S. Barnett, Adit D. Singh, Victor P. Nelson |
Yield-Reliability Modeling for Fault Tolerant Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 29-38, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
infant mortality, negative binomial distribution, clustering, reliability, redundancy, yield, defects, defect tolerance, burn-in |
19 | Yves Audet, Glenn H. Chapman |
Design of a Self-Correcting Active Pixel Sensor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 18-, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
defect tolerance, digital cameras, Active Pixel Sensors |
19 | Weiping Shi, Ming-Feng Chang, W. Kent Fuchs |
Harvest Rate of Reconfigurable Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 45(10), pp. 1200-1203, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Harvest rate, pipelines, yield, random graphs, defect tolerance, percolation, reconfigurable arrays |
19 | Claude Thibeault, Yvon Savaria, Jean-Louis Houle |
A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(6), pp. 687-698, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
defect-tolerant integrated circuits, optimum number of spares, reconfiguration strategies, optimum redundancy, VLSI, logic testing, redundancy, defect tolerance, circuit reliability, yield models, integrated circuit manufacture |
18 | Takuto Nishimura, Yuya Ichikawa, Akira Goda, Naoko Misawa, Chihiro Matsui, Ken Takeuchi |
Stochastic Computing-based Computation-in-Memory (SC CiM) Architecture for DNNs and Hierarchical Evaluations of Non-volatile Memory Error and Defect Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMW ![In: IEEE International Memory Workshop, IMW 2023, Monterey, CA, USA, May 21-24, 2023, pp. 1-4, 2023, IEEE, 978-1-6654-7459-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Shiva Shankar Thiagarajan, Suriyaprakash Natarajan, Yiorgos Makris |
A defect tolerance framework for improving yield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022, pp. 847-852, 2022, ACM, 978-1-4503-9142-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Sebastian Dengler, Said Lahriri, Emanuel Trunzer, Birgit Vogel-Heuser |
Applied machine learning for a zero defect tolerance system in the automated assembly of pharmaceutical devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Decis. Support Syst. ![In: Decis. Support Syst. 146, pp. 113540, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
18 | Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri |
TSV-Cluster Defect Tolerance Using Tree-Based Redundancy for Yield Improvement of 3-D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8), pp. 1500-1510, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
18 | Tanmoy Chaku, Aarjesh Rakshit, Ismail Sarkar, Malay Kule |
On Defect Tolerance of Nanocrossbar Arrays using Divide and Conquer Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISDCS ![In: 4th International Symposium on Devices, Circuits and Systems, ISDCS 2021, Higashi-Hiroshima, Japan, March 3-5, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1478-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
18 | Samiya Mahjabin, Md Mahfuzul Haque, Md. Khan Sobayel Bin Rafiq, M. S. Jamal, Mohammad Aminul Islam, V. Selvanathan, Abdulaziz K. Assaifan, Hamad F. Alharbi, K. Sopian, Nowshad Amin, Md. Akhtaruzzaman |
Perceiving of Defect Tolerance in Perovskite Absorber Layer for Efficient Perovskite Solar Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 106346-106353, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Xiaojing Zha, Yinshui Xia |
Defective cell reuse based defect-tolerance method for CMOL cell mapping optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 105, pp. 104863, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Suriyaprakash Natarajan, Andres F. Malavasi, Pascal Andreas Meinerzhagen |
Automated Design For Yield Through Defect Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 38th IEEE VLSI Test Symposium, VTS 2020, San Diego, CA, USA, April 5-8, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-5359-9. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Onur Tunali, Mustafa Altun |
A Fast Logic Mapping Algorithm for Multiple-Type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 7(4), pp. 518-529, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Hossein Pourmeidani, Mehdi Habibi |
A Range Matching CAM for Hierarchical Defect Tolerance Technique in NRAM Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1907.04504, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
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