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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 173 occurrences of 127 keywords
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Results
Found 311 publication records. Showing 311 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
115 | Priyadarsan Patra, Donald S. Fussell |
Power-efficient delay-insensitive codes for data transmission. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 316-323, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
telecommunication switching, power-efficient delay-insensitive codes, dynamic delay-insensitive codes, switching energy optimization, data pins, protocols, delays, power consumption, codes, asynchronous systems, data communication, data communication, data transmission, energy reduction, delay-insensitive circuits |
105 | Jia Di, Parag K. Lala |
Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(2-3), pp. 175-192, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Reed-Muller expression, nanoscale circuit, layout, stuck-at fault, cellular arrays, delay-insensitive circuit |
99 | H. Bekker, E. J. Dijkstra |
Delay-Insensitive Synchronization on a Message-Passing Architecture with an Open Collector Bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), January 24-26, 1996, Portugal, pp. 75-79, 1996, IEEE Computer Society, 0-8186-7376-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
delay-insensitive synchronization, open collector bus, high latency, constraint algorithm, SHAKE, Constraint Molecular Dynamics simulation, ring architecture, delay insensitive algorithm, performance evaluation, performance, parallel algorithms, parallel algorithms, parallel architectures, message passing, multiprocessor interconnection networks, multiprocessor interconnection networks, synchronisation, digital simulation, physics computing, system buses, communication time, message passing architecture |
74 | Sandeep Pagey |
Fast functional testing of delay-insensitive circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 375-381, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
four-phase handshake signalling, Martin's method, distributed circuit, OR/C blocks, generation of test sequences, program flow graph, logic testing, delays, design for testability, logic CAD, asynchronous circuits, functional testing, testing time, self-timed circuits, delay-insensitive circuits, OR gates |
70 | Venkatesh Akella, Nitin H. Vaidya, G. Robert Redinbo |
Asynchronous Comparison-Based Decoders for Delay-Insensitive Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 47(7), pp. 802-811, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Delay-insensitive codes, self-timed design, delay-insensitive communication, block codes |
59 | Pedro A. Molina, Peter Y. K. Cheung |
A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands, pp. 126-139, 1997, IEEE Computer Society, 0-8186-7922-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Tri-state Buffers, Asynchronous, Composability, Bus, Data Path, Delay-Insensitive, Handshake Circuits |
57 | Hiroshi Saito, Alex Kondratyev, Takashi Nanya |
Design of Asynchronous Controllers with Delay Insensitive Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 93-98, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
delay insensitive interface, gate-level transformation, behavioral transformation, asynchronous circuits, hazards |
57 | Yoshio Kameda, Stanislav Polonsky, Masaaki Maezawa, Takashi Nanya |
Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 262-273, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
pulse-driven logic, Josephson junction device, RSFQ device, pipeline, asynchronous circuit, delay-insensitive circuit |
54 | Jia Lee, Ferdinand Peper, Susumu Adachi, Kenichi Morita |
Universal Delay-Insensitive Circuits with Bidirectional and Buffering Lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(8), pp. 1034-1046, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
bidirectional buffering lines, module, Asynchronous systems, universality, delay-insensitive circuits |
54 | Willem C. Mallon, Jan Tijmen Udding |
Using Metrics for Proof Rules for Recursively Defined Delay-insensitive Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands, pp. 175-, 1997, IEEE Computer Society, 0-8186-7922-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
delay-insensitive specifications, recursive definition, linear proofs, intuitive induction rule, algebraic specification, algebraic specifications, theorem provers, correctness proofs, proof rules, proof rule |
48 | Gregg N. Hoyer, Gin Yee, Carl Sechen |
Locally clocked pipelines and dynamic logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(1), pp. 58-62, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
48 | Yoshio Kameda |
Pulse-Driven Delay-Insensitive Circuits using Single-Flux-Quantum Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 419-425, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
45 | David K. Probst, Hon Fung Li |
Partial-Order Model Checking: A Guide for the Perplexed. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 3rd International Workshop, CAV '91, Aalborg, Denmark, July, 1-4, 1991, Proceedings, pp. 322-331, 1991, Springer, 3-540-55179-4. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
delay-insensitive system, partial-order representation, recurrence structure, model checking, state explosion, state encoding |
45 | Daniel H. Linder, James C. Harden |
Phased Logic Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 45(9), pp. 1031-1044, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Asynchronous circuitry, delay-insensitive circuitry, dual-rail encoding, LEDR, phased logic, synchronous circuitry, data flow, marked graphs |
43 | Jia Di, Dilip P. Vasudevan |
Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 149-156, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
43 | Christopher LaFrieda, Rajit Manohar |
Fault Detection and Isolation Techniques for Quasi Delay-Insensitive Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2004 International Conference on Dependable Systems and Networks (DSN 2004), 28 June - 1 July 2004, Florence, Italy, Proceedings, pp. 41-50, 2004, IEEE Computer Society, 0-7695-2052-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
42 | Lei Wang 0014, Carl McCrosky |
Performance Comparison of Control Schemes for ABR Service in ATM LANs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: MASCOTS 1997, Proceedings of the Fifth International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, January 12-15, 1997 Haifa, Israel, pp. 205-212, 1997, IEEE Computer Society, 0-8186-7758-9. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
ABR service, ATM Forum, available bit rate service, constrained cell loss, network resource utilization, CBR/VBR services, burst level traffic control, rate based feedback control, loss sensitive applications, delay insensitive applications, burst transfer delay, simulation, asynchronous transfer mode, bandwidth, performance comparison, ATM LAN, delay variation |
41 | Masashi Imai, Metehan Γzcan, Takashi Nanya |
Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 62-71, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
41 | A. Neslin Ismailoglu, Murat Askar |
Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3259-3262, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Ethiopia Nigussie, Juha Plosila, Jouni Isoaho |
Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 217-224, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
41 | Jia Di, Parag K. Lala, Dilip P. Vasudevan |
On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 371-379, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Igor Lemberski, Mark B. Josephs |
Optimal Two-Level Delay - Insensitive Implementation of Logic Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002, pp. 92-100, 2002, Springer, 3-540-44143-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
38 | Mark B. Josephs, Dennis P. Furey |
Delay-Insensitive Interface Specification and Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 169-173, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
38 | Riccardo Mariani, Roberto Roncella, Roberto Saletti, Pierangelo Terreni |
On the Realisation of Delay-Insensitive Asynchronous Circuits with CMOS Ternary Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands, pp. 54-, 1997, IEEE Computer Society, 0-8186-7922-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
38 | Priyadarsan Patra, Donald S. Fussell |
Efficient Delay-Insensitive RSFQ Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 413-418, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
38 | David M. Goldschlag |
Mechanically Verifying Safety and Liveness Properties of Delay Insensitive Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 3rd International Workshop, CAV '91, Aalborg, Denmark, July, 1-4, 1991, Proceedings, pp. 354-364, 1991, Springer, 3-540-55179-4. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
38 | Anders Gammelgaard |
Implementation Conditions for Delay Insensitive Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARLE (1) ![In: PARLE '89: Parallel Architectures and Languages Europe, Volume I: Parallel Architectures, Eindhoven, The Netherlands, June 12-16, 1989, Proceedings, pp. 341-355, 1989, Springer, 3-540-51284-5. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
36 | Dario Pompili, Tommaso Melodia, Ian F. Akyildiz |
Routing algorithms for delay-insensitive and delay-sensitive applications in underwater sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MobiCom ![In: Proceedings of the 12th Annual International Conference on Mobile Computing and Networking, MOBICOM 2006, Los Angeles, CA, USA, September 23-29, 2006, pp. 298-309, 2006, ACM, 1-59593-286-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
routing algorithms, underwater sensor networks |
35 | Raffaele Mascella, Luca G. Tallini |
Efficient m-Ary Balanced Codes which Are Invariant under Symbol Permutation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(8), pp. 929-946, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Coding and information theory, m{hbox{-}}rm ary communication, line codes, DC-free communication, delay-insensitive communication, error control codes, digital communication, constant weight codes, balanced codes |
35 | Yannick Monnet, Marc Renaudin, RΓ©gis Leveugle |
Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(9), pp. 1104-1115, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
quasi-delay insensitive, hardening techniques, Asynchronous circuits, data encryption standard, fault attacks |
35 | Yannick Monnet, Marc Renaudin, RΓ©gis Leveugle |
Asynchronous circuits transient faults sensitivity evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 863-868, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
quasi delay insensitive, simulation, fault model, asynchronous circuits, transient fault |
35 | Hemangee K. Kapoor, Mark B. Josephs |
Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 830-833, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
asynchronous logic synthesis, delay-insensitive decomposition |
35 | Marc Renaudin, Pascal Vivet, FrΓ©dΓ©ric Robin |
ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 22-31, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
asynchronous microprocessor, quasi-delay-insensitive circuits, standard-cell asynchronous design |
35 | R. S. Hogg, W. I. Hughes, David W. Lloyd |
A Novel Asynchronous ALU for Massively Parallel Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), January 24-26, 1996, Portugal, pp. 282-289, 1996, IEEE Computer Society, 0-8186-7376-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
novel asynchronous ALU, self timed asynchronous bit serial massively parallel architecture, fixed word length, small magnitude data, self timed communication techniques, self timed single instruction systolic array, ST-SISA, self timed delay insensitive techniques, parallel architectures, systolic arrays, asynchronous circuits, clock skew, massively parallel architectures, clocked control, arithmetic logic unit |
35 | Priyadarsan Patra, Donald S. Fussell |
Fully asynchronous, robust, high-throughput arithmetic structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 141-145, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
fully asynchronous structures, high-throughput arithmetic structures, bit serial adders, scaleability, VLSI, digital arithmetic, asynchronous circuits, adders, integrated logic circuits, multiplying circuits, RSA cryptosystems, delay-insensitive, bit serial multipliers |
35 | David K. Probst, Hon Fung Li |
Using Partial-Order Semantics to Avoid the State Explosion Problem in Asynchronous Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 2nd International Workshop, CAV '90, New Brunswick, NJ, USA, June 18-21, 1990, Proceedings, pp. 146-155, 1990, Springer, 3-540-54477-1. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
delay-insensitive system, branching point, recurrence structure, behavior machine, behavior state, model checking, state explosion, partial-order semantics |
31 | Masashi Imai, Takashi Nanya |
A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France, pp. 68-77, 2006, IEEE Computer Society, 0-7695-2498-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Ethiopia Nigussie, Juha Plosila, Jouni Isoaho |
Area efficient delay-insensitive and differential current sensing on-chip interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 143-146, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Hemangee K. Kapoor, Mark B. Josephs, Dennis P. Furey |
Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 4th International Conference on Application of Concurrency to System Design (ACSD 2004), 16-18 June 2004, Hamilton, Canada, pp. 89-98, 2004, IEEE Computer Society, 0-7695-2077-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Amitava Mitra, William F. McLaughlin, Steven M. Nowick |
Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 12-14 March 2006, Berkeley, California, USA, pp. 186-195, 2007, IEEE Computer Society, 978-0-7695-2771-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Yannick Monnet, Marc Renaudin, RΓ©gis Leveugle |
Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 113-120, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Giuseppe Campobello, Marco Castano, Carmine Ciofi, Daniele Mangano |
GALS networks on chip: a new solution for asynchronous delay-insensitive links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE Designers' Forum ![In: Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 160-165, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-0-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin |
Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2006, 8th International Workshop, Yokohama, Japan, October 10-13, 2006, Proceedings, pp. 384-398, 2006, Springer, 3-540-46559-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
QDI Asynchronous circuits, Path Swapping (PS), Power analysis |
29 | G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard |
Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia, pp. 11-24, 2005, Springer, 978-0-387-73660-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Bertrand Folco, Vivian BrΓ©gier, Laurent Fesquet, Marc Renaudin |
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia, pp. 55-69, 2005, Springer, 978-0-387-73660-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain |
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 424-429, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Konrad J. Kulikowski, Ming Su, Alexander B. Smirnov, Alexander Taubin, Mark G. Karpovsky, Daniel MacDonald |
Delay Insensitive Encoding and Power Analysis: A Balancing Act. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA, pp. 116-125, 2005, IEEE Computer Society, 0-7695-2305-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Hemangee K. Kapoor, Mark B. Josephs |
Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: Fifth International Conference on Application of Concurrency to System Design (ACSD 2005), 6-9 June 2005, St. Malo, France, pp. 58-67, 2005, IEEE Computer Society, 0-7695-2363-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Myeong-Hoon Oh, Dong-Soo Har |
A Novel Mechanism for Delay-Insensitive Data Transfer Based on Current-Mode Multiple Valued Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 691-700, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Alexander Taubin, Karl Fant, John McCardle |
Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 104-111, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Robert Berks, Radu Negulescu |
Partial-Order Correctness-Preserving Properties of Delay-Insensitive Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 11-14 March 2001, Salt Lake City, UT, USA, pp. 74-, 2001, IEEE Computer Society, 0-7695-1034-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
29 | W. J. Bainbridge, Stephen B. Furber |
Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 11-14 March 2001, Salt Lake City, UT, USA, pp. 118-126, 2001, IEEE Computer Society, 0-7695-1034-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
29 | Nattha Sretasereekul, Takashi Nanya |
Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 437-442, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
29 | Willem C. Mallon |
On Directed Transformations of Delay-Insensitive Specifications, Alternations and Dynamic Nondeterminism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 12-22, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
{Communicating Processes}, {Computer Aided Design}, Meta-stability, Formal Methods, Handshake Protocol, Delay-Insensitivity |
29 | Fu-Chiung Cheng, Chuin-Ren Wang |
Specification and Design of a Quasi-Delay-Insensitive Java Card. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 356-361, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Tom Verhoeff |
Analyzing Specifications for Delay-Insensitive Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 172-183, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
29 | Priyadarsan Patra, Stanislav Polonsky, Donald S. Fussell |
Delay Insensitive Logic for RSFQ Superconductor Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands, pp. 42-53, 1997, IEEE Computer Society, 0-8186-7922-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
29 | Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald, Wen-Chung Cho |
Delay-Insensitive Carry-Lookahead Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 322-328, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
29 | S. C. Leung, Hon Fung Li |
On the realizability and synthesis of delay-insensitive behaviors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(7), pp. 833-848, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
29 | S. C. Leung, Hon Fung Li |
A syntax-directed translation for the synthesis of delay-insensitive circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 2(2), pp. 196-210, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
29 | Takashi Nanya, Yoichiro Ueno, Hiroto Kagotani, Masashi Kuwako, Akihiro Takamura |
TITAC: Design of A Quasi-Delay-Insensitive Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 11(2), pp. 50-63, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
29 | Mark B. Josephs, Jan Tijmen Udding |
Delay-Insensitive Circuits: An Algebraic Approach to their Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONCUR ![In: CONCUR '90, Theories of Concurrency: Unification and Extension, Amsterdam, The Netherlands, August 27-30, 1990, Proceedings, pp. 342-366, 1990, Springer, 3-540-53048-7. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
29 | Alain J. Martin |
The Design of a Delay-Insensitive Microprocessor: An Example of Circuit Synthesis by Program Transformation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hardware Specification, Verification and Synthesis ![In: Hardware Specification, Verification and Synthesis: Mathematical Aspects, Mathematical Science Institute Workshop, Cornall University, Ithaca, New York, USA, July 5-7, 1989, Proceedings, pp. 244-259, 1989, Springer, 3-540-97226-9. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
26 | David W. Lloyd, Jim D. Garside |
A Practical Comparison of Asynchronous Design Styles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 11-14 March 2001, Salt Lake City, UT, USA, pp. 36-45, 2001, IEEE Computer Society, 0-7695-1034-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Scott C. Smith |
Design of a logic element for implementing an asynchronous FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007, pp. 13-22, 2007, ACM, 978-1-59593-600-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
NULL convention logic (NCL), asynchronous logic design, field programmable gate array (FPGA), reconfigurable logic, delay-insensitive circuits |
26 | Mehrdad Najibi, Kamran Saleh, Hossein Pedram |
Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 299-304, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
quasi-delay insensitive, standard-cell layout, asynchronous circuits |
26 | Signe J. Silver, Janusz A. Brzozowski |
True Concurrency in Models of Asynchronous Circuit Behavior. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 22(3), pp. 183-203, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
multiple-winner, single-winner, semi-modular, asynchronous, circuit, interleaving, true concurrency, delay-insensitive |
26 | Luca G. Tallini, Bella Bose |
Transmission Time Analysis for the Parallel Asynchronous Communication Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(5), pp. 558-571, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
delay-insensitive codes, proximity detecting codes, low weight codes, Asynchronous communication, constant weight codes, unordered codes |
26 | Scott C. Smith |
Speedup of Self-Timed Digital Systems Using Early Completion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 25-26 April 2002, Pittsburgh, PA, USA, pp. 107-116, 2002, IEEE Computer Society, 0-7695-1486-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
asynchronous, NCL, NULL Convention Logic, delay-insensitive |
26 | Luca G. Tallini, Bella Bose |
Some Transmission Time Analysis for the Parallel Asynchronous Communication Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FTCS ![In: Digest of Papers: FTCS-29, The Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, Madison, Wisconsin, USA, June 15-18, 1999, pp. 192-199, 1999, IEEE Computer Society, 0-7695-0213-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
delay-insensitive codes, proximity detecting codes, low weight codes, Asynchronous communication, constant weight codes, unordered codes |
26 | Nozar Tabrizi, Michael J. Liebelt, Kamran Eshraghian |
A Tabular Method for Guard Strengthening, Symmetrization, and Operator Reduction for Martin's Asynchronous Design Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 46(9), pp. 1050-1054, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
formal program transformation, self-timed logic, signal transition graphs (STG), speed independent circuits, guarded commands, delay insensitive circuits, Asynchronous sequential circuits |
24 | Dario Pompili, Tommaso Melodia |
Three-dimensional routing in underwater acoustic sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PE-WASUN ![In: Proceedings of the 2nd ACM International Workshop on Performance Evaluation of Wireless Ad Hoc, Sensor, and Ubiquitous Networks, PE-WASUN 2005, Montreal, Quebec, Canada, October 10-13, 2005, pp. 214-221, 2005, ACM, 1-59593-182-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
routing algorithms, mathematical programming/optimization, underwater acoustic sensor networks |
24 | Myeong-Hoon Oh, Dong-Soo Har |
Low Delay-Power Product Current-Mode Multiple Valued Logic for Delay-Insensitive Data Transfer Mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(5), pp. 1379-1383, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | P. Balasubramanian 0001, David A. Edwards, Charlie Brej |
Self-timed full adder designs based on hybrid input encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 56-61, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Robert B. Reese, Mitchell A. Thornton, Cherrice Traver, David Hemmendinger |
Early evaluation for performance enhancement in phased logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4), pp. 532-550, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Susumu Adachi, Ferdinand Peper, Jia Lee |
Universality of Hexagonal Asynchronous Totalistic Cellular Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACRI ![In: Cellular Automata, 6th International Conference on Cellular Automata for Research and Industry, ACRI 2004, Amsterdam, The Netherlands, October 25-28, 2004, Proceedings, pp. 91-100, 2004, Springer, 3-540-23596-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Mark B. Josephs |
Formal Derivation of a Loadable Asynchronous Counter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MPC ![In: Mathematics of Program Construction, MPC'98, Marstrand, Sweden, June 15-17, 1998, Proceedings, pp. 234-253, 1998, Springer, 3-540-64591-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Riccardo Mariani, Roberto Roncella, Roberto Saletti, Pierangelo Terreni |
Useful Application of CMOS Ternary Logic to the Realisation of Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 27th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1997, Antigonish, Nova Scotia, Canada, May 28-30, 1997, Proceedings, pp. 203-208, 1997, IEEE Computer Society, 0-8186-7910-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Yong Zhang, Xin Zhang 0001 |
QoS Based Proportional Fair Scheduling Algorithm for CDMA Forward Link. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Spring ![In: Proceedings of the 65th IEEE Vehicular Technology Conference, VTC Spring 2007, 22-25 April 2007, Dublin, Ireland, pp. 1031-1035, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Zaheer Tabassam, Andreas Steininger |
Towards Resilient Quasi Delay Insensitive Conditional Control Elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 26th Euromicro Conference on Digital System Design, DSD 2023, Golem, Albania, September 6-8, 2023, pp. 206-213, 2023, IEEE, 979-8-3503-4419-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Zaheer Tabassam, Andreas Steininger |
SET Effects on Quasi Delay Insensitive and Synchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: IEEE European Test Symposium, ETS 2023, Venezia, Italy, May 22-26, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-3634-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Zaheer Tabassam, Andreas Steininger, Robert Najvirt, Florian Huemer |
ΞΆ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 28th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2023, Beijing, China, July 16-19, 2023, pp. 48-57, 2023, IEEE, 979-8-3503-0576-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Duarte Lopes de Oliveira, Marcus H. Victor, Luiz C. Moreira, Felipe F. Nascimento |
Design of Quasi Delay Insensitive Combinational Circuits Based on Optimized DIMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: 14th IEEE Latin America Symposium on Circuits and System, LASCAS 2023, Quito, Ecuador, February 28 - March 3, 2023, pp. 1-4, 2023, IEEE, 978-1-6654-5705-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Dalta Imam Maulana, Wanyeong Jung |
An Energy-Efficient Delay Insensitive Asynchronous Interface for Globally Asynchronous Locally Synchronous (GALS) System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, CA, USA, May 21-25, 2023, pp. 1-5, 2023, IEEE, 978-1-6654-5109-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Zeguo Liu, Jingyi Yuan, Feng Wu, Lin Cheng 0001 |
A 12V/24V-to-1V PWM-Controlled DSD Converter With Delay-Insensitive and Dual-Phase Charging Techniques for Fast Transient Responses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(12), pp. 3853-3864, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Yue Feng, Yuanli Yue, Qiang Wu 0005, Chao Wang 0074 |
Delay-Insensitive Time Stretch Interrogation of Fiber Bragg Grating Sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSNDSP ![In: 13th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2022, Porto, Portugal, July 20-22, 2022, pp. 662-666, 2022, IEEE, 978-1-6654-1044-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Orlando Verducci Jr., Duarte Lopes de Oliveira, Gracieth Cavalcanti Batista |
Fault-Tolerant Finite State Machine Quasi Delay Insensitive in Commercial FPGA Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: 13th IEEE Latin America Symposium on Circuits and System, LASCAS 2022, Puerto Varas, Chile, March 1-4, 2022, pp. 1-4, 2022, IEEE, 978-1-6654-2008-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Raghda El Shehaby, Andreas Steininger |
Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 63-68, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
19 | Duarte Lopes de Oliveira, Gabriel C. Duarte, Gracieth Cavalcanti Batista |
A New QDI Asynchronous Pipeline with Two-Phase Delay-Insensitive Global Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: 12th IEEE Latin America Symposium on Circuits and System, LASCAS 2021, Arequipa, Peru, February 21-24, 2021, pp. 1-4, 2021, IEEE, 978-1-7281-7670-3. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
19 | Taciano A. Rodolfo, Marcos L. L. Sartori, Matheus T. Moreira, Ney Laert Vilar Calazans |
Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, pp. 1-5, 2021, IEEE, 978-1-7281-9201-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
19 | Orlando Verducci Jr., Duarte Lopes de Oliveira, Robson L. Moreno |
Fault-Tolerant Quasi Delay Insensitive Combinational Circuits in Commercial FPGA Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 22nd IEEE Latin American Test Symposium, LATS 2021, Punta del Este, Uruguay, October 27-29, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2057-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
19 | Linh Duc Tran, Thanh Chi Pham, Omid Kavehei, Peter C. M. Burton, Glenn Ian Matthews |
Extended Boolean algebra for asynchronous quasi-delay-insensitive logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 14(8), pp. 1201-1213, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
19 | Padmanabhan Balasubramanian, Nikos E. Mastorakis |
Quasi-Delay-Insensitive Implementation of Approximate Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Symmetry ![In: Symmetry 12(11), pp. 1919, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
19 | P. Balasubramanian 0001, Douglas L. Maskell, Nikos E. Mastorakis |
Area Optimized Quasi Delay Insensitive Majority Voter for TMR Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2008.05685, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
19 | Yuri Stepchenkov, Yuri Rogdestvenski, Anton N. Kamenskih, Yuri Diachenko, Denis Diachenko |
Improvement of the Quasi Delay-Insensitive Pipeline Noise Immunity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DESSERT ![In: 11th IEEE International Conference on Dependable Systems, Services and Technologies, DESSERT 2020, Kyiv, Ukraine, May 14-18, 2020, pp. 47-51, 2020, IEEE, 978-1-7281-9957-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
19 | P. Balasubramanian 0001, Douglas L. Maskell, Nikos E. Mastorakis |
Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1903.09433, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
19 | P. Balasubramanian 0001 |
Performance Comparison of Quasi-Delay-Insensitive Asynchronous Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1907.10826, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
19 | Quang Tran Minh 0001, Van An Le, Tran Khanh Dang, Nam Thoai, Takeshi Kitahara |
Flow aggregation for SDN-based delay-insensitive traffic control in mobile core networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Commun. ![In: IET Commun. 13(8), pp. 1051-1060, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
19 | Yi-Fan Evan Chang, Ruei-Yang Huang, Jie-Hong R. Jiang |
Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 25th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2019, Hirosaki, Japan, May 12-15, 2019, pp. 19-26, 2019, IEEE, 978-1-5386-4747-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
19 | P. Balasubramanian 0001, Douglas L. Maskell, Nikos E. Mastorakis |
Area Optimized Quasi Delay Insensitive Majority Voter for TMR Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EECS ![In: 3rd European Conference on Electrical Engineering and Computer Science, EECS 2019, Athens, Greece, December 28-30, 2019, pp. 37-44, 2019, IEEE, 978-1-7281-6109-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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