Search results for "nanoelectronic"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
134	Bao Liu 0001	Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolution.	ISQED	2009	DBLP DOI BibTeX RDF
118	Wenjing Rao, Alex Orailoglu, Ramesh Karri	Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays.	DSN	2007	DBLP DOI BibTeX RDF
107	Lutz J. Micheel, Hans L. Hartnagel	Interband RTDs with Nanoelectronic HBT-LED Structures for Multiple-Valued Computation.	ISMVL	1996	DBLP DOI BibTeX RDF	heterojunction bipolar transistors, resonant tunnelling devices, light emitting devices, interband RTDs, resonant tunnelling devices, nanoelectronic HBT-LED structures, multiple-valued computation, nanoelectronic arrays, complex signal processing methods, HBT-LED-RTD circuitry, heterojunction bipolar transistors, light emitting devices, internal optical methods, signal summation, precision photon streams, positive-digit radix-2 MVL, A/D conversion capability, optical isolation, buried optical interconnects, microcavity lasers, signal processing, optical interconnections, optical interconnects, multiple-valued logic, multivalued logic circuits, thresholding functions, analogue-digital conversion
86	Bao Liu 0001	Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture.	ASP-DAC	2009	DBLP DOI BibTeX RDF
70	Wenjing Rao, Alex Orailoglu, Ramesh Karri	Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors.	ICCD	2005	DBLP DOI BibTeX RDF
54	Bao Liu 0001	Robust differential asynchronous nanoelectronic circuits.	ISQED	2009	DBLP DOI BibTeX RDF
54	Wenjing Rao, Alex Orailoglu, Ramesh Karri	Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics.	ETS	2006	DBLP DOI BibTeX RDF
54	Jie Han 0001, Erin Taylor 0001, Jianbo Gao, José A. B. Fortes	Faults, Error Bounds and Reliability of Nanoelectronic Circuits.	ASAP	2005	DBLP DOI BibTeX RDF
48	Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici	Optimization of Nanoelectronic Systems Reliability by Reducing Logic Depth.	NanoNet	2009	DBLP DOI BibTeX RDF	logic depth, reliability of nanoelectronic systems, Fault-tolerance, redundancy, high defect density
43	Mesbah Uddin, Md. Badruddoja Majumder, Garrett S. Rose	Nanoelectronic Security Designs for Resource-Constrained Internet of Things Devices: Finding Security Solutions with Nanoelectronic Hardwares.	IEEE Consumer Electron. Mag.	2018	DBLP DOI BibTeX RDF
43	Mohammad Reza Jahangir, Shadi Sheikhfaal, Shaahin Angizi, Keivan Navi, Firdous Ahmad	Designing Nanoelectronic-Compatible 8-bit Square Root Circuit by Quantum-Dot Cellular Automata.	iNIS	2015	DBLP DOI BibTeX RDF
38	Samir M. Iqbal, Rashid Bashir	Nanoelectronic-Based Detection for Biology and Medicine.	Handbook of Automation	2009	DBLP DOI BibTeX RDF
38	Wenjing Rao, Alex Orailoglu	Towards fault tolerant parallel prefix adders in nanoelectronic systems.	DATE	2008	DBLP DOI BibTeX RDF
38	Oliver Soffke, Peter Zipf, Tudor Murgan, Manfred Glesner	A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits.	DATE	2006	DBLP DOI BibTeX RDF
38	Zhi Huo, Qishan Zhang, S. Haruehanroengra, Wei Wang	Logic optimization for majority gate-based nanoelectronic circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
38	Wenjing Rao, Alex Orailoglu, Ramesh Karri	Fault tolerant nanoelectronic processor architectures.	ASP-DAC	2005	DBLP DOI BibTeX RDF
38	Jui-Lin Lai, Peter Chung-Yu Wu	Architectural design and analysis of learnable self-feedback ratio-memory cellular nonlinear network (SRMCNN) for nanoelectronic systems.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
38	Garrett S. Rose, Matthew M. Ziegler, Mircea R. Stan	Large-signal two-terminal device model for nanoelectronic circuit analysis.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
38	Terry J. Fountain, Michael J. B. Duff, D. G. Crawley, Chris D. Tomlinson, C. D. Moffat	The use of nanoelectronic devices in highly parallel computing systems.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
32	Ilia Polian, Wenjing Rao	Selective Hardening of NanoPLA Circuits.	DFT	2008	DBLP DOI BibTeX RDF
32	Wenjing Rao, Alex Orailoglu, Ramesh Karri	Towards Nanoelectronics Processor Architectures.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	fault tolerance, reliability, computational model, processor architecture, nanoelectronics, time redundancy, hardware redundancy
32	Kwang-Ting (Tim) Cheng	Design and CAD for Nanotechnologies.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	process diagnosis, CAD, redundancy, CMOS, delay testing, SEU
32	Jie Han 0001, Pieter Jonker	From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers.	ICPR (3)	2004	DBLP DOI BibTeX RDF
32	Gerhard Klimeck, Carlos Salazar-Lazaro, Adrian Stoica, Thomas A. Cwik	"Genetically Engineered" Nanoelectronics.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
27	Dennis Huo, Qiaoyan Yu, David Wolpert 0001, Paul Ampadu	A simulator for ballistic nanostructures in a 2-D electron gas.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	2DEG, Ballistic transport, nanoelectronic device, transistor
27	Marek A. Bawiec	Resonant Tunnelling Diode-Based Circuits: Simulation and Synthesis.	EUROCAST	2009	DBLP DOI BibTeX RDF	Nanoelectronic Devices, NDR Modelling, Boolean Logic Synthesis, SPICE Simulation
27	Milos Stanisavljevic, Frank K. Gürkaynak, Alexandre Schmid, Yusuf Leblebici, Maria Gabrani	Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	reliability of submicron and nanoelectronic systems, fault-tolerant architecture, high defect density
27	Wenjing Rao, Alex Orailoglu, Ramesh Karri	Topology aware mapping of logic functions onto nanowire-based crossbar architectures.	DAC	2006	DBLP DOI BibTeX RDF	logic synthesis, PLA, nanoelectronic, crossbar
22	David Esseni, Francesco Driussi, Daniel Lizzit, Marco Massarotto, Mattia Segatto	Modelling and Simulations of Ferroelectric Materials and Ferroelectric-Based Nanoelectronic Devices.	CoRR	2023	DBLP DOI BibTeX RDF
22	Supriya Chakraborty, Tamoghno Das, Manan Suri	Exploiting Nanoelectronic Properties of Memory Chips for Prevention of IC Counterfeiting.	CoRR	2022	DBLP DOI BibTeX RDF
22	Konstantinos Rallis, Panagiotis Dimitrakis, Georgios Ch. Sirakoulis, Antonio Rubio 0001, Ioannis Karafyllidis	Current Characteristics of Defective GNR Nanoelectronic Devices.	NANOARCH	2022	DBLP DOI BibTeX RDF
22	Maria Helena Fino	Nanoelectronic Challenges and Opportunities for Cyber-Physical Systems.	MIXDES	2022	DBLP DOI BibTeX RDF
22	Hans-Christian Ruiz Euler, Unai Alegre Ibarra, Bram van de Ven, Hajo Broersma, Peter A. Bobbert, Wilfred G. van der Wiel	Dopant network processing units: towards efficient neural network emulators with high-capacity nanoelectronic nodes.	Neuromorph. Comput. Eng.	2021	DBLP DOI BibTeX RDF
22	Francis Balestra	Status and trends in Nanoelectronic devices for the ultimate integration of ICs.	ASICON	2021	DBLP DOI BibTeX RDF
22	M. M. Abutaleb	Utilizing charge reconfigurations of quantum-dot cells in building blocks to design nanoelectronic adder circuits.	Comput. Electr. Eng.	2020	DBLP DOI BibTeX RDF
22	Hai Helen Li, Wei Zhang 0012, Swarup Bhunia, Wujie Wen	Introduction to the Special Issue on New Trends in Nanoelectronic Device, Circuit, and Architecture Design, Part 1.	ACM J. Emerg. Technol. Comput. Syst.	2020	DBLP DOI BibTeX RDF
22	Hans-Christian Ruiz Euler, Unai Alegre Ibarra, Bram van de Ven, Hajo Broersma, Peter A. Bobbert, Wilfred G. van der Wiel	Dopant Network Processing Units: Towards Efficient Neural-network Emulators with High-capacity Nanoelectronic Nodes.	CoRR	2020	DBLP BibTeX RDF
22	Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer 0001, Anton Klotz, Michael Hübner 0001, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka	RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems.	DATE	2020	DBLP DOI BibTeX RDF
22	Oleksandr V. Prokhorov, Yurii Pronchakov, Oleg Fedorovich, Nataliia Kunanets	Modeling of Technological Process in Nanoelectronic Production.	CSIT (1)	2020	DBLP DOI BibTeX RDF
22	Md. Badruddoja Majumder, Md Sakib Hasan, Mesbah Uddin, Garrett S. Rose	A Secure Integrity Checking System for Nanoelectronic Resistive RAM.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
22	Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer 0001, Anton Klotz, Michael Hübner 0001, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka	RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems.	CoRR	2019	DBLP BibTeX RDF
22	Atul Mohan	Virus-based nanoelectronic devices.		2019	RDF
22	Arne Heittmann, Tobias G. Noll	Architecture and optimization of associative memories used for the implementation of logic functions based on nanoelectronic 1S1R cells.	DATE	2018	DBLP DOI BibTeX RDF
22	H. Sribhuvaneshwari, K. Suthendran 0001	A Novel March C2RR Algorithm for Nanoelectronic Resistive Random Access Memory (RRAM) Testing.	VDAT	2018	DBLP DOI BibTeX RDF
22	P. Balasubramanian 0001, R. T. Naayagi	Mathematical Estimation of Logical Masking Capability of Majority/Minority Gates Used in Nanoelectronic Circuits.	CoRR	2017	DBLP BibTeX RDF
22	Elias Kougianos	Nanoelectronic Mixed-Signal System Design [Book Reviews].	IEEE Consumer Electron. Mag.	2017	DBLP DOI BibTeX RDF
22	Arne Heittmann, Tobias G. Noll	Mixing circuit based on neural associative memories and nanoelectronic 1S1R cells.	NANOARCH	2017	DBLP DOI BibTeX RDF
22	Fazel Sharifi, Himanshu Thapliyal	Energy-efficient magnetic circuits based on nanoelectronic devices.	ISCAS	2017	DBLP DOI BibTeX RDF
22	Francis Balestra	Ultra low power and high performance nanoelectronic devices.	ASICON	2017	DBLP DOI BibTeX RDF
22		IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2017, Bhopal, India, December 18-20, 2017	iNIS	2017	DBLP BibTeX RDF
22	Matteo Bollo, Giulia Santoro, Umberto Garlando, Maurizio Zamboni	NANOcom: A Mosaic Approach for nanoelectronic circuits design.	DTIS	2017	DBLP DOI BibTeX RDF
22	Paolo Scarbolo	Electrical characterization and modeling of pH and microparticle nanoelectronic sensors.		2017	RDF
22	Anirban Sengupta, Deepak Kachave, Shubha Neema, Panugothu Sri Harsha	Reliability and Threat Analysis of NBTI Stress on DSP Cores.	iNIS	2017	DBLP DOI BibTeX RDF
22	Abir J. Mondal, Alak Majumder, Bidyut K. Bhattacharyya	A Design Methodology for MOS Current Mode Logic VCO.	iNIS	2017	DBLP DOI BibTeX RDF
22	Syed Samsuz Zaman, Pankaj Kumar, Manash Pratim Sarma, Ashok Ray, Gaurav Trivedi	Design and Simulation of SF-FinFET and SD-FinFET and Their Performance in Analog, RF and Digital Applications.	iNIS	2017	DBLP DOI BibTeX RDF
22	Monalisa Das, Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya	A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application.	iNIS	2017	DBLP DOI BibTeX RDF
22	Rathin K. Joshi, Rutu Parekh, Yash Agrawal	Design and Optimization of Single Electron Transistor Based 4-Bit Arithmetic and Logic Unit at Room Temperature Operation.	iNIS	2017	DBLP DOI BibTeX RDF
22	Dharmendra Singh Yadav, Dheeraj Sharma, Sukeshni Tirkey, Deepak Soni, Deepak G. Sharma, Shriya Bajpai, Neeraj Sharma	A Comparative Study of GaP/SiGe Hetero Junction Double Gate Tunnel Field Effect Transistor.	iNIS	2017	DBLP DOI BibTeX RDF
22	Anoop D, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra	High Performance Sense Amplifier Based Flip Flop for Driver Applications.	iNIS	2017	DBLP DOI BibTeX RDF
22	Sauvagya Ranjan Sahoo, Sudeendra Kumar K, Abhishek Mahapatra, Ayas Kanta Swain, Kamala Kanta Mahapatra	On-chip RO-Sensor for Recycled IC Detection.	iNIS	2017	DBLP DOI BibTeX RDF
22	Sudeendra Kumar K, Sauvagya Ranjan Sahoo, Abhishek Mahapatra, Ayas Kanta Swain, Kamala Kanta Mahapatra	Microprocessor Based Physical Unclonable Function.	iNIS	2017	DBLP DOI BibTeX RDF
22	Saranyu Chattopadhyay, Kaustav Brahma, Arkaprova Ray, Mrigank Sharad	STT-MRAM for Low Power Access for Read-Intensive Parallel Deep-Learning Architectures.	iNIS	2017	DBLP DOI BibTeX RDF
22	Manoj R, Adrian Fernandez	Rapid Prototyping IoT End Applications Using Software Development Kits and Add on Plugins.	iNIS	2017	DBLP DOI BibTeX RDF
22	Himanshu Thapliyal, T. S. S. Varun, Edgard Muñoz-Coreas, Keith A. Britt, Travis S. Humble	Quantum Circuit Designs of Integer Division Optimizing T-Count and T-Depth.	iNIS	2017	DBLP DOI BibTeX RDF
22	Amit Singh Rajput, Manisha Pattanaik, Ritesh Kumar Tiwari	Design and Analysis of Schmitt Trigger Based 10T SRAM in 32 nm Technology.	iNIS	2017	DBLP DOI BibTeX RDF
22	Mannem Naga Sasikanth, Sashank Gambhira, Mrigank Sharad	Design Optimization of DSP for Wearable Biomedical Device.	iNIS	2017	DBLP DOI BibTeX RDF
22	S. Dinesh Kumar, Himanshu Thapliyal	Security Evaluation of MTJ/CMOS Circuits Against Power Analysis Attacks.	iNIS	2017	DBLP DOI BibTeX RDF
22	Anirban Sengupta, Dipanjan Roy	Mathematical Validation of HWT Based Lossless Image Compression.	iNIS	2017	DBLP DOI BibTeX RDF
22	Mohammed Ahmed	Digital Video Stabilization- Review with a Perspective of Real Time Implementation.	iNIS	2017	DBLP DOI BibTeX RDF
22	Grandhi Sai Anirudh, Soumya J.	Routing Algorithm for Application-Specific Network-on-Chip with Irregular Core Sizes.	iNIS	2017	DBLP DOI BibTeX RDF
22	Nagendra Babu Gunti, Karthikeyan Lingasubramanian	Neutralization of the Effect of Hardware Trojan in SCADA System Using Selectively Placed TMR.	iNIS	2017	DBLP DOI BibTeX RDF
22	Bipasha Nath, Alak Majumder	Binary Counter Based Gated Clock Tree for Integrated CPU Chip.	iNIS	2017	DBLP DOI BibTeX RDF
22	Tapan Chowdhury, Arijit Mukherjee, Susanta Chakraborty	An Efficient MapReduce-Based Adaptive K-Means Clustering for Large Dataset.	iNIS	2017	DBLP DOI BibTeX RDF
22	Nawaz Shafi, Chitrakant Sahu, C. Periasamy, Jawar Singh	SiGe Source Charge Plasma TFET for Biosensing Applications.	iNIS	2017	DBLP DOI BibTeX RDF
22	Sitansusekhar Roymohapatra, Ganesh R. Gore, Akanksha Yadav, Mahesh B. Patil, Krishnan S. Rengrajan, Maryam Shojaei Baghini	Enhanced Look-Up Table Approach for Modeling of Floating Body SOI MOSFET.	iNIS	2017	DBLP DOI BibTeX RDF
22	Tuhin Subhra Das, Prasun Ghosal	MSM: Performance Enhancing Area and Congestion Aware Network-on-Chip Architecture.	iNIS	2017	DBLP DOI BibTeX RDF
22	Deepak Soni, Dheeraj Sharma, Shivendra Yadav, Mohd. Aslam, Dharmendra Singh Yadav, Neeraj Sharma	Gate Metal Work Function Engineering for the Improvement of Electrostatic Behaviour of Doped Tunnel Field Effect Transistor.	iNIS	2017	DBLP DOI BibTeX RDF
22	Nagendra Babu Gunti, Karthikeyan Lingasubramanian	Fault Sensitive Neutralization of Hardware Trojans Using Multi-level Triple Modular Redundancy Scheme.	iNIS	2017	DBLP DOI BibTeX RDF
22	Alak Majumder, Pritam Bhattacharjee	Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip.	iNIS	2017	DBLP DOI BibTeX RDF
22	Shrestha Bansal, Hemanta Kumar Mondal, Sri Harsha Gade, Sujay Deb	Energy Efficient NoC Router for High Throughput Applications in Many-Core GPUs.	iNIS	2017	DBLP DOI BibTeX RDF
22	Vipul Kumar Mishra, Anirban Sengupta	Comprehensive Operation Chaining Based Schedule Delay Estimation During High Level Synthesis.	iNIS	2017	DBLP DOI BibTeX RDF
22	Soudip Sinha Roy	Towards the Approximation of Cell Wise Switching Time in Quantum-Dot Cellular Automata.	iNIS	2017	DBLP DOI BibTeX RDF
22	Shivram Mansore, Radheshyam Gamad, D. K. Mishra	A Single-Ended Read Decoupled 9T SRAM Cell for Low Power Applications.	iNIS	2017	DBLP DOI BibTeX RDF
22	Rekib Uddin Ahmed, Prabir Saha	Modeling of Threshold Voltage and Subthreshold Current for P-Channel Symmetric Double-Gate MOSFET in Nanoscale Regime.	iNIS	2017	DBLP DOI BibTeX RDF
22	Ashish Sharma 0005, Yogendra Gupta, Sonal Yadav, Lava Bhargava, Manoj Singh Gaur, Vijay Laxmi	A Power, Thermal and Reliability-Aware Network-on-Chip.	iNIS	2017	DBLP DOI BibTeX RDF
22	Soudip Sinha Roy	Fault Tolerance and Temperature Stability: The Dynamic Error Estimation in Quantum-Dot Cellular Automata.	iNIS	2017	DBLP DOI BibTeX RDF
22	Dharmendra Kumar, Chintoo Kumar, Shipra Gautam, Debasis Mitra 0002	Design of Practical Parity Generator and Parity Checker Circuits in QCA.	iNIS	2017	DBLP DOI BibTeX RDF
22	Sudeendra Kumar K, Sauvagya Ranjan Sahoo, Abhishek Mahapatra, Ayas Kanta Swain, Kamala Kanta Mahapatra	Security Enhancements to System on Chip Devices for IoT Perception Layer.	iNIS	2017	DBLP DOI BibTeX RDF
22	Subhendu Kumar Sahoo, Gangishetty Akhilesh, Rasmita Sahoo	Design of a High Performance Carry Generation Circuit for Ternary Full Adder Using CNTFET.	iNIS	2017	DBLP DOI BibTeX RDF
22	Aditya Japa, T. Nagateja, Ramesh Vaddi	Tunneling Field Effect Transistors for Energy Efficient Logic, Sensor Interface and 3D IC Circuits for IoT Platforms.	iNIS	2017	DBLP DOI BibTeX RDF
22	Pankaj Kumar, Syed Samsuz Zaman, Manash Pratim Sarma, Ashok Ray, Gaurav Trivedi	Basic CMOS Gate Design by Mixed-Mode Analysis of Step-Channel TMDG-MOSFET.	iNIS	2017	DBLP DOI BibTeX RDF
22	Pratima Chatterjee, Prasun Ghosal	Realizing All Logic Operations Using mRNA-Ribosome System as a Post Si Alternative.	iNIS	2017	DBLP DOI BibTeX RDF
22	Rajani Suthar, Kirti S. Pande, N. S. Murty	Leakage Reduction in DT8T SRAM Cell Using Body Biasing Technique.	iNIS	2017	DBLP DOI BibTeX RDF
22	Gurveen Vaseer, Garima Ghai, Pushpinder Singh Patheja	A Novel Intrusion Detection Algorithm: An AODV Routing Protocol Case Study.	iNIS	2017	DBLP DOI BibTeX RDF
22	Vipul Kumar Mishra	Cost Aware Majority Logic Synthesis for Emerging Technologies.	iNIS	2017	DBLP DOI BibTeX RDF
22	Sarfraz Hussain, Rajesh Kumar, Gaurav Trivedi	A Novel Low Power High Speed BEC for 2GHz Sampling Rate Flash ADC in 45nm Technology.	iNIS	2017	DBLP DOI BibTeX RDF
22	Saurabh Chaturvedi, Mladen Bozanic, Saurabh Sinha	Implementation of a 6 GHz MEMS Switch.	iNIS	2017	DBLP DOI BibTeX RDF
22	Samya Muhuri, Debasree Das, Susanta Chakraborty	An Automated Game Theoretic Approach for Cooperative Road Traffic Management in Disaster.	iNIS	2017	DBLP DOI BibTeX RDF
22	Subhendu Kumar Sahoo, Pramod Kumar Meher	Lookup Table-Based Low-Power Implementation of Multi-channel Filters for Software Defined Radio.	iNIS	2017	DBLP DOI BibTeX RDF
22	Pallabi Sarkar, Anirban Sengupta, Santosh Rathlavat, Mrinal Kanti Naskar	A Firefly Algorithm Driven Approach for High Level Synthesis.	iNIS	2017	DBLP DOI BibTeX RDF