Search results for "parasitic"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
111	Ning Lu, Judy H. McCullen	Enablement of Variation-Aware Timing: Treatment of Parasitic Resistance and Capacitance.	ISQED	2007	DBLP DOI BibTeX RDF
94	Dukgwon Lee, Seunghyun Beak, Youngmin Lee, Eunser Lee, Jungkook Kim, Gyung-Leen Park, Taikyeong Jeong	Minimize the delay of parasitic capacitance and modeling in RLC circuit.	ICHIT	2009	DBLP DOI BibTeX RDF	Elmore, parasitic capacitance, delay, interconnection, oscillator
92	Huiying Yang, Ranga Vemuri	Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit Synthesis.	VLSI Design	2007	DBLP DOI BibTeX RDF
84	Gang Zhang, E. Aykut Dengi, Ronald A. Rohrer, Rob A. Rutenbar, L. Richard Carley	A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits.	DAC	2004	DBLP DOI BibTeX RDF	modeling, synthesis, layout, sizing, parasitic, radio frequency
65	Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri	Fast and accurate parasitic capacitance models for layout-aware.	DAC	2004	DBLP DOI BibTeX RDF	layout aware, parasitic estimation, analog synthesis
63	K. C. Sivaramakrishnan, Lukasz Ziarek, Raghavendra Prasad, Suresh Jagannathan	Lightweight asynchrony using parasitic threads.	DAMP	2010	DBLP DOI BibTeX RDF	lightweight threading, mlton, message passing, asynchronous communication
63	Chaitanya Kshirsagar, Mohamed N. El-Zeftawi, Kaustav Banerjee	Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs.	DAC	2008	DBLP DOI BibTeX RDF	RF performance, carbon nanotube FET (CNFET), modeling
63	Anuradha Agarwal, Ranga Vemuri	Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners.	ICCD	2005	DBLP DOI BibTeX RDF
57	Chauchin Su, Yue-Tsang Chen	Intrinsic response extraction for the removal of the parasiticeffects in analog test buses.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
55	Pantelis K. Varlamos, Panagiotis J. Papakanellos, Christos N. Capsalis	Design of Circular Switched Parasitic Dipole Arrays Using a Genetic Algorithm.	Int. J. Wirel. Inf. Networks	2004	DBLP DOI BibTeX RDF	Circular switched parasitic dipole arrays, electronic beam steering, induced EMF method, genetic algorithms, method of moments
54	Nuttorn Jangkrajarng, Lihong Zhang, Sambuddha Bhattacharya, Nathan Kohagen, C.-J. Richard Shi	Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts.	ICCAD	2006	DBLP DOI BibTeX RDF	analog/RF integrated circuits, layout automation, layout symmetry, design reuse, parasitics
54	N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus D. Cantrell	Benchmarks for Interconnect Parasitic Resistance and Capacitance.	ISQED	2003	DBLP DOI BibTeX RDF
50	Thomas Plos	Evaluation of the Detached Power Supply as Side-Channel Analysis Countermeasure for Passive UHF RFID Tags.	CT-RSA	2009	DBLP DOI BibTeX RDF	Deta-ched Power Supply, Parasitic Backscatter, RFID, Differential Power Analysis, Side-Channel Analysis, UHF
50	Henry H. Y. Chan, Zeljko Zilic	Modeling Layout Effects for Sensitivity-Based Analog Circuit Optimization.	ISQED	2005	DBLP DOI BibTeX RDF	Analog circuit optimization, adjoint analysis, sensitivity analysis, parasitic extraction
48	Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou	Intrinsic response for analog module testing using an analog testability bus.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	analog testability bus, intrinsic response, design for testability, analog testing, boundary scan
46	Hiroyuki Iizuka, Hideyuki Ando, Taro Maeda	The Anticipation of Human Behavior Using "Parasitic Humanoid".	HCI (3)	2009	DBLP DOI BibTeX RDF	parasitic humanoid, behavior-based turing test, attractor superimposition, Ambient interface
46	Jung Hyun Choi	Minimization of parasitic effects on the design of an accurate 2-MHz RC oscillator for low voltage and low power applications.	SBCCI	2005	DBLP DOI BibTeX RDF	2MHz RC circuit, parasitic effects, design, minimization, oscillator
46	Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram	A green function-based parasitic extraction method for inhomogeneous substrate layers.	DAC	2005	DBLP DOI BibTeX RDF	green function, substrate noise, parasitic extraction
46	Luís Miguel Silveira, Joel R. Phillips	Exploiting input information in a model reduction algorithm for massively coupled parasitic networks.	DAC	2004	DBLP DOI BibTeX RDF	interconnect, model order reduction, parasitic
46	Zhanhai Qin, Chung-Kuan Cheng	Realizable parasitic reduction using generalized Y-Delta transformation.	DAC	2003	DBLP DOI BibTeX RDF	Y-?, parasitic reduction, transformation, model order reduction
46	Mike Hill	Parasitic Languages for Requirements.	ICRE	1996	DBLP DOI BibTeX RDF	Parasitic Langauge, Modelling, Requirements Engineering
44	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design.	ISQED	2008	DBLP DOI BibTeX RDF
44	Zhao Li, C.-J. Richard Shi	SILCA: SPICE-accurate iterative linear-centric analysis for efficient time-domain Simulation of VLSI circuits with strong parasitic couplings.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
44	Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri	Accurate Estimation of Parasitic Capacitances in Analog Circuits.	DATE	2004	DBLP DOI BibTeX RDF
44	Pierluigi Daglio, David Iezzi, Danilo Rimondi, Carlo Roma, Salvatore Santapa	Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components.	DATE	2004	DBLP DOI BibTeX RDF
44	William H. Kao, Chi-Yuan Lo, Raminderpal Singh, Mark Basel	Parasitic extraction: current state of the art and future trends.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
44	Eileen You, Lakshminarasimh Varadadesikan, John MacDonald, Wieze Xie	A practical approach to parasitic extraction for design of multimillion-transistor integrated circuits.	DAC	2000	DBLP DOI BibTeX RDF
44	Michael W. Beattie, Lawrence T. Pileggi	Electromagnetic parasitic extraction via a multipole method with hierarchical refinement.	ICCAD	1999	DBLP DOI BibTeX RDF
40	Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee	Prospect of ballistic CNFET in high performance applications: Modeling and analysis.	ACM J. Emerg. Technol. Comput. Syst.	2007	DBLP DOI BibTeX RDF	Ballistic carbon nanotube FET (CNFET), circuit compatible model, parasitic capacitance, process variability, circuit performance
40	Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee	Modeling and analysis of circuit performance of ballistic CNFET.	DAC	2006	DBLP DOI BibTeX RDF	ballistic carbon nanotube FET (CNFET), circuit compatible model, parasitic capacitance, circuit performance
40	Jinsong Hou, Zeyi Wang, Xianlong Hong	The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance.	ASP-DAC	1999	DBLP DOI BibTeX RDF	Parasitic Capacitance, Hierarchical h-Adaptive Computation, VLSI, Boundary Element Method
36	Sandra Irobi, Zaid Al-Ars, Said Hamdioui	Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs.	ETS	2011	DBLP DOI BibTeX RDF	Parasitic Bit Line coupling, SRAMs, Memory tests
36	John Kymissis, Clyde Kendall, Joseph A. Paradiso, Neil Gershenfeld	Parasitic Power Harvesting in Shoes.	ISWC	1998	DBLP DOI BibTeX RDF	Human-powered systems, power scavenging, parasitic power, self-powered, piezoelectrics, PVDF, Thunder, energy harvesting, RFID systems
34	Zheng Liu, Lihong Zhang	Performance-constrained parasitic-aware retargeting and optimization of analog layouts.	CCECE	2009	DBLP DOI BibTeX RDF
34	Florian Alt, Albrecht Schmidt 0001, Richard Atterer, Paul Holleis	Bringing Web 2.0 to the Old Web: A Platform for Parasitic Applications.	INTERACT (1)	2009	DBLP DOI BibTeX RDF
34	Abhisek Dixit, Anirban Bandhyopadhyay, Nadine Collaert, Kristin De Meyer, Malgorzata Jurczak	Measurement and Analysis of Parasitic Capacitance in FinFETs with High-k Dielectrics and Metal-Gate Stack.	VLSI Design	2009	DBLP DOI BibTeX RDF
34	Robert Bains, Ralf R. Müller	Using Parasitic Elements for Implementing the Rotating Antenna for MIMO Receivers.	IEEE Trans. Wirel. Commun.	2008	DBLP DOI BibTeX RDF
34	Fabian Henrici, Joachim Becker, Alexander Buhmann, Maurits Ortmanns, Yiannos Manoli	A Continuous-Time Field Programmable Analog Array Using Parasitic Capacitance Gm-C Filters.	ISCAS	2007	DBLP DOI BibTeX RDF
34	Zhao Li, C.-J. Richard Shi	A Quasi-Newton Preconditioned Newton-Krylov Method for Robust and Efficient Time-Domain Simulation of Integrated Circuits With Strong Parasitic Couplings.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
34	Chanseok Hwang, Chang Woo Kang, Massoud Pedram	Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs.	ISQED	2006	DBLP DOI BibTeX RDF
34	Lars A. Schreiner, Markus Olbrich, Erich Barke, Volker Meyer zu Bexten	Routing of analog busses with parasitic symmetry.	ISPD	2005	DBLP DOI BibTeX RDF	analog routing, net bundles, paired nets, virtual terminals, routing, EDA, RF, bus routing, IC-layout
34	Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi	Template-driven parasitic-aware optimization of analog integrated circuit layouts.	DAC	2005	DBLP DOI BibTeX RDF	analog layout automation, optimization, sensitivity, parasitics
34	Elena Gnani, Vincenzo Giudicissi, Radu Vissarion, Claudio Contiero, Massimo Rudan	Automatic 2-D and 3-D simulation of parasitic structures insmart-power integrated circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
34	Sadahiro Tani, Yoshihiro Uchida, Makoto Furuie, Shuji Tsukiyama, BuYeol Lee, Shuji Nishi, Yasushi Kubota, Isao Shirakawa, Shigeki Imai	Parasitic capacitance modeling for multilevel interconnects.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
34	Lun Ye, Foong-Charn Chang, Peter Feldmann, Rakesh Chadha, Nagaraj Ns, Frank Cano	Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs.	DATE	1999	DBLP DOI BibTeX RDF
34	Peter B. Aronhime, Zbigniew Lata, Jie Deng, Brent Maundy	Effects of parasitic admittances in active synthesis of current-mode circuits.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
34	Ichirou Oota, Noriaki Hara, Fumio Ueno	Influence of parasitic inductance on serial fixed type switched-capacitor transformer.	ISCAS (5)	1999	DBLP DOI BibTeX RDF
34	Victor Giménez, Margarita Pérez-Castellanos, J. Rios Carrion, Luis Fernando de Mingo López	Capacity and Parasitic Fixed Points Control in a Recursive Neural Network.	IWANN	1997	DBLP DOI BibTeX RDF
34	Umakanta Choudhury, Alberto L. Sangiovanni-Vincentelli	Automatic generation of parasitic constraints for performance-constrained physical design of analog circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
31	Nicolas Butzen, Michiel S. J. Steyaert	MIMO Switched-Capacitor DC-DC Converters Using Only Parasitic Capacitances Through Scalable Parasitic Charge Redistribution.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
31	Nicolas Butzen, Michiel Steyaert	MIMO Switched-Capacitor converter using only parasitic capacitance with Scalable Parasitic Charge Redistribution.	ESSCIRC	2016	DBLP DOI BibTeX RDF
30	Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede	Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment.	CHES	2005	DBLP DOI BibTeX RDF	dual rail with precharge, wave dynamic differential logic (WDDL), differential routing, parasitic capacitance matching, side-channel attack (SCA), differential power analysis (DPA), countermeasure
30	Bernard N. Sheehan	Branch Merge Reduction of RLCM Networks.	ICCAD	2003	DBLP DOI BibTeX RDF	transmission-line modeling, Gaussian elimination, model order reduction, Parasitic extraction
30	Claude Thibeault	Detection and location of faults and defects using digital signal processing.	VTS	1995	DBLP DOI BibTeX RDF	sampled current, sampled voltage, quiescent current, parasitic resistive contacts, DSP technique, fault diagnosis, logic testing, integrated circuit testing, fault detection, diagnosis, signal processing, digital signal processing, fault location, fault location, defects, digital integrated circuits, test method
29	Zheng Liu, Lihong Zhang	Performance-constrained template-driven retargeting for analog and RF layouts.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	optimization, performance, layout, retargeting, parasitics
29	Yangmin Li 0001, Qingsong Xu	Design and Optimization of an XYZ Parallel Micromanipulator with Flexure Hinges.	J. Intell. Robotic Syst.	2009	DBLP DOI BibTeX RDF	Precision machine, Flexure hinge, Particle swarm optimization (PSO), Parallel manipulator, Robotic modeling, Optimum design
29	Aditya P. Karmarkar, Xiaopeng Xu, Victor Moroz, Greg Rollins, Xiao Lin	Analysis of performance and reliability trade-off in dummy pattern design for 32-nm technology.	ISQED	2009	DBLP DOI BibTeX RDF
29	Anirban Banerjee, Dhiman Barman, Michalis Faloutsos, Laxmi N. Bhuyan	Cyber-Fraud is One Typo Away.	INFOCOM	2008	DBLP DOI BibTeX RDF
29	Mikhail Popovich, Eby G. Friedman	Nanoscale on-chip decoupling capacitors.	SoCC	2008	DBLP DOI BibTeX RDF
29	Almitra Pradhan, Ranga Vemuri	A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	layout-aware, matrix-models, sizing
29	Nancy Ying Zhou, Zhuo Li 0001, Yuxin Tian, Weiping Shi, Frank Liu 0001	A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects.	ASP-DAC	2007	DBLP DOI BibTeX RDF
29	Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny, Radu M. Secareanu	Maximum effective distance of on-chip decoupling capacitors in power distribution grids.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	power distribution grids, decoupling capacitors, power distribution systems
29	N. S. Nagaraj, Tom Bonifield, Abha Singh, Roger Griesmer, Poras T. Balsara	Interconnect Modeling for Copper/Low-k Technologies.	VLSI Design	2004	DBLP DOI BibTeX RDF
29	J. Shorb, Xiaoyong Li 0001, David J. Allstot	A resonant pad for ESD protected narrowband CMOS RF applications.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
29	Li Ding 0002, Pinaki Mazumder	Accurate Estimating Simultaneous Switching Noises by Using Application Specific Device Modeling.	DATE	2002	DBLP DOI BibTeX RDF
29	Andreas Herrmann, Erich Barke, Mathias Silvant, Jürgen Schlöffel	PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits.	PATMOS	2000	DBLP DOI BibTeX RDF
29	Fenghao Mu, Christer Svensson	A layout-based schematic method for very high-speed CMOS cell design.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
25	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dual oxide technology, nano-cmos, performance aware design, vco, process variation, parasitics, power aware design
25	Lihong Zhang, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, C.-J. Richard Shi	Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
25	Jun Luo 0001, Panagiotis Papadimitratos, Jean-Pierre Hubaux	GossiCrypt: Wireless Sensor Network Data Confidentiality Against Parasitic Adversaries.	SECON	2008	DBLP DOI BibTeX RDF
25	Zhao Li, C.-J. Richard Shi	A quasi-newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplings.	ASP-DAC	2006	DBLP DOI BibTeX RDF
25	Su-Jeong Sim, Jeongmin Park, Sung Min Park 0001	A 1.8V, 60dB Omega 11 GHz transimpedance amplifier with strong immunity to input parasitic capacitance.	ISCAS	2006	DBLP DOI BibTeX RDF
25	Laura Gobbi, Alessandro Cabrini, Guido Torelli	Impact of parasitic elements on CMOS charge pumps: a numerical analysis.	ISCAS	2006	DBLP DOI BibTeX RDF
25	Karen Chow	The Challenges and Impact of Parasitic Extraction at 65 nm.	ISQED	2006	DBLP DOI BibTeX RDF
25	Zhao Li, C.-J. Richard Shi	An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation.	DATE	2005	DBLP DOI BibTeX RDF
25	Grzegorz Tosik, Zbigniew Lisik, Malgorzata Langer, Janusz Wozny	Simulation of Parasitic Interconnect Capacitance for Present and Future ICs.	International Conference on Computational Science (1)	2005	DBLP DOI BibTeX RDF
25	Takahide Sato, Shigetaka Takagi, Nobuo Fujii, Yasuyuki Hashimoto, Kohji Sakata, Hiroyuki Okada	Feedforward-type parasitic capacitance canceler and its application to 4 Gb/s T/H circuit.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
25	Nur Kurt-Karsilayan	Generic Modeling of Non-planar Dielectrics for 2 1/2D Parasitic Extraction.	IWSOC	2005	DBLP DOI BibTeX RDF
25	Dipanjan Gope, Indranil Chowdhury, Vikram Jandhyala	DiMES: multilevel fast direct solver based on multipole expansions for parasitic extraction of massively coupled 3D microelectronic structures.	DAC	2005	DBLP DOI BibTeX RDF	non-iterative, parasitics, multilevel, multipole
25	Dipanjan Gope, Vikram Jandhyala	Oct-tree-based multilevel low-rank decomposition algorithm for rapid 3-D parasitic extraction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
25	Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen	Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models.	DATE	2004	DBLP DOI BibTeX RDF
25	Liu Yang, Xiaobo Guo, Zeyi Wang	An efficient method MEGCR for solving systems with multiple right-hand sides in 3-D parasitic inductance extraction.	ASP-DAC	2004	DBLP DOI BibTeX RDF	Inductance extraction, Multiple right-hand sides, Multipole method, PEEC
25	Janet Meiling Wang, Prashant Saxena, Omar Hafiz, Xing Wang	Realizable parasitic reduction for distributed interconnects using matrix pencil technique.	ASP-DAC	2004	DBLP DOI BibTeX RDF
25	Min Chu, David J. Allstot, Jeffrey M. Huard, Kim Y. Wong	NSGA-based parasitic-aware optimization of a 5GHz low-noise VCO.	ASP-DAC	2004	DBLP DOI BibTeX RDF
25	Dipanjan Gope, Swagato Chakraborty, Vikram Jandhyala	A fast parasitic extractor based on low-rank multilevel matrix compression for conductor and dielectric modeling in microelectronics and MEMS.	DAC	2004	DBLP DOI BibTeX RDF	conductors and dielectrics, low-rank, parasitics, multilevel
25	Shrirang K. Karandikar, Sachin S. Sapatnekar	Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
25	Jérôme Lescot, François J. R. Clément	Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated Circuits.	PATMOS	2003	DBLP DOI BibTeX RDF
25	Zhao Li, C.-J. Richard Shi	SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong Parasitic Coupling Effects.	ICCAD	2003	DBLP DOI BibTeX RDF	SPICE
25	Xiaoyan Wang, Pietro Andreani	Impact of mutual inductance and parasitic capacitance on the phase-error performance of CMOS quadrature VCOs.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
25	Kiyong Choi, David J. Allstot, Sayfe Kiaei	Parasitic-aware synthesis of RF CMOS switching power amplifiers.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
25	Taro Maeda, Hideyuki Ando, Maki Sugimoto, Junji Watanabe, Takeshi Miki	Wearable Robotics as a Behavioral Interface - The Study of the Parasitic Humanoid.	ISWC	2002	DBLP DOI BibTeX RDF
25	Zhaozhi Yang, Zeyi Wang, Shuzhou Fang	A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance.	ASP-DAC	2001	DBLP DOI BibTeX RDF
25	Tim Ebringer, Peter Thorne, Yuliang Zheng 0001	Parasitic Authentication To Protect Your E-Wallet.	Computer	2000	DBLP DOI BibTeX RDF
25	Martin Bächtold, Mirko Spasojevic, Christian Lage, Per B. Ljung	A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
25	Mattan Kamon, Steve McCormick, Ken Sheperd	Interconnect parasitic extraction in the digital IC design methodology.	ICCAD	1999	DBLP DOI BibTeX RDF
25	Wayne Wei-Ming Dai	Chip Parasitic Extraction and Signal Integrity Verification (Extended Abstract).	DAC	1997	DBLP DOI BibTeX RDF
25	Carlo Marazzini, Mauro Santomauro, Michele Taliercio	CIRCE: a program for parasitic parameter extraction.	EURO-DAC	1990	DBLP DOI BibTeX RDF
25	Shun-Lin Su, Vasant B. Rao, Timothy N. Trick	HPEX: A Hierarchical Parasitic Circuit Extractor.	DAC	1987	DBLP DOI BibTeX RDF
21	Tarek A. El-Moselhy, Luca Daniel	Stochastic dominant singular vectors method for variation-aware extraction.	DAC	2010	DBLP DOI BibTeX RDF	intrusive algorithms, stochastic PDEs, stochastic dominant singular vectors, variation-aware extraction, stochastic simulation, integral equations, surface roughness, parasitic extraction
21	Lin Liu, Yuanfu Zhao, Suge Yue	3D Simulation of Charge Collection and MNU in Highly-Scaled SRAM Design.	NCM	2009	DBLP DOI BibTeX RDF	charge collection, hardened cells, multiple-node upset (MNU), parasitic bipolar conduction