Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
72 | Edoardo Charbon, Paolo Miliozzi, Enrico Malavasi, Alberto L. Sangiovanni-Vincentelli |
Generalized constraint generation in the presence of non-deterministic parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 187-192, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
constraint-driven layout synthesis, non-deterministic parasitics, constraint generation |
61 | Zheng Liu, Lihong Zhang |
Performance-constrained template-driven retargeting for analog and RF layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 429-434, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
optimization, performance, layout, retargeting, parasitics |
61 | Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos |
Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 303-308, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dual oxide technology, nano-cmos, performance aware design, vco, process variation, parasitics, power aware design |
49 | Carsten Wegener, Michael Peter Kennedy |
Overcoming Test Setup Limitations by Applying Model-Based Testing to High-Precision ADCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(3), pp. 299-310, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
model-based ADC test, device interface parasitics, Design-for-Test |
49 | Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi |
Template-driven parasitic-aware optimization of analog integrated circuit layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 644-647, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
analog layout automation, optimization, sensitivity, parasitics |
49 | Raoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri |
A high level language for pre-layout extraction in parasite-aware analog circuit synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 271-276, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
MSL, pre-layout extraction, parasitics, analog VLSI |
48 | Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram |
Extraction of Parasitics in Inhomogeneous Substrates With a New Green Function-Based Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9), pp. 1595-1606, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
48 | Nishath K. Verghese, David J. Allstot |
SUBTRACT: a program for the efficient evaluation of substrate parasitics in integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 194-198, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
48 | Ranjit Gharpurey, Srinath Hosur |
Transform domain techniques for efficient extraction of substrate parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 461-467, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Green Function, orthonormal transforms, parasitics, substrate coupling |
37 | Nancy Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li 0001, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi |
The impact of BEOL lithography effects on the SRAM cell performance and yield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 607-612, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
37 | Zheng Liu, Lihong Zhang |
Performance-constrained parasitic-aware retargeting and optimization of analog layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, CCECE 2009, 3-6 May 2009, Delta St. John's Hotel and Conference Centre, St. John's, Newfoundland, Canada, pp. 1194-1197, 2009, IEEE, 978-1-4244-3508-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
37 | Lihong Zhang, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, C.-J. Richard Shi |
Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(5), pp. 791-802, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
37 | N. S. Nagaraj, Tom Bonifield, Abha Singh, Roger Griesmer, Poras T. Balsara |
Interconnect Modeling for Copper/Low-k Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 425-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
37 | N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus D. Cantrell |
Benchmarks for Interconnect Parasitic Resistance and Capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA, pp. 163-168, 2003, IEEE Computer Society, 0-7695-1881-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Mohamed Dessouky, Marie-Minerve Louërat |
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 291-298, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Analog layout, layout generation |
37 | Rex Lowther |
Compact modeling of interconnect and substrate coupling at GHz frequencies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 238-241, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
37 | Andrew B. Kahng, Chung-Wen Albert Tsao |
Practical Bounded-Skew Clock Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 16(2-3), pp. 199-215, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
37 | Umakanta Choudhury, Alberto L. Sangiovanni-Vincentelli |
Automatic generation of parasitic constraints for performance-constrained physical design of analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(2), pp. 208-224, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
37 | Umakanta Choudhury, Alberto L. Sangiovanni-Vincentelli |
Constraint Generation for Routing Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 561-566, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
36 | Nuttorn Jangkrajarng, Lihong Zhang, Sambuddha Bhattacharya, Nathan Kohagen, C.-J. Richard Shi |
Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 342-348, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
analog/RF integrated circuits, layout automation, layout symmetry, design reuse, parasitics |
36 | Bikram Baidya, Tamal Mukherjee |
Extraction and LVS for mixed-domain integrated MEMS layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 361-366, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
MEMS LVS, MEMS extraction, integrated MEMS, verification, parasitics |
36 | Frederik Beeftink, Arjan J. van Genderen, N. P. van der Meijs |
Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 360-365, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
MOS integrated circuits, bipolar integrated circuits, BiCMOS integrated circuits, layout-to-circuit extraction, high-speed MOS integrated circuits, bipolar/BiCMOS integrated circuits, device recognition, equivalent network, layout parasitics, interconnects, circuit analysis computing, circuit layout CAD, Space, Spice, device modeling |
36 | Nancy Ying Zhou, Zhuo Li 0001, Yuxin Tian, Weiping Shi, Frank Liu 0001 |
A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 450-455, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Eunseok Song, Heeseok Lee, Jungtae Lee, Woojin Jin, Kiwon Choi, Sa-Yoon Kang |
Upper/Lower Boundary Estimation of Package Interconnect Parasitics for Chip-Package Co-Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 573-579, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram |
An error control method for application of the discrete cosine transform to extraction of substrate parasitics in ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5), pp. 932-938, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Ajit Sharma, Patrick Birrer, Sasi Kumar Arunachalam, Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram |
Accurate Prediction of Substrate Parasitics in Heavily Doped CMOS Processes Using a Calibrated Boundary Element Solver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(7), pp. 843-851, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Michael W. Beattie, Lawrence T. Pileggi |
Parasitics extraction with multipole refinement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(2), pp. 288-292, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Martin R. Frerichs |
Precise extraction of ultra deep submicron interconnect parasitics with parameterizable 3D-modeling: invited talk. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 50-56, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
36 | H. Levy, W. Scott, Don MacMillen, Jacob White 0001 |
A rank-one update method for efficient processing of interconnect parasitics in timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 75-78, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
36 | Mariusz Niewczas, Adam Wojtasik |
Modeling of VLSI RC parasitics based on the network reduction algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(2), pp. 137-144, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
36 | Teng-Sin Pong, Martin A. Brooke |
A parasitics extraction and network reduction algorithm for analog VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(2), pp. 145-149, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
36 | Jacques Wenin, Johan Verhasselt, Marc Van Camp, Jean Leonard, Pierre Guebels |
Rule-based VLSI Verification System Constrained by Layout Parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 662-667, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
25 | Vinayak Honkote, Baris Taskin |
PEEC based parasitic modeling for power analysis on custom rotary rings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 111-116, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
resonant clocking, simulation, modeling, interconnect |
25 | Ali Davoudi, Juri Jatskevich, Patrick L. Chapman |
Computer-Aided Average-Value Modeling of Fourth-Order PWM DC-DC Converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 793-796, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Massimo Alioto, Gaetano Palumbo |
Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3255-3258, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Scott B. Kuntze, Lacra Pavel, J. Stewart Aitchison |
Novel gain control in a multichannel semiconductor optical amplifier with equivalent circuit using nonlinear state-space methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BROADNETS ![In: Fourth International Conference on Broadband Communications, Networks and Systems, (BROADNETS 2007), 10-14 September 2007, Raleigh, North-Carolina, USA, pp. 915-918, 2007, IEEE, 978-1-4244-1432-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Ning Fu, Mitsutoshi Mineshima, Shigetoshi Nakatake |
Multi-SP: A Representation with United Rectangles for Analog Placement and Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 38-43, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Di Long, Xianlong Hong, Sheqin Dong |
Signal-path driven partition and placement for analog circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 694-699, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
analog placement, device merging, layout automation, signal-path, symmetry constrain, circuit partition |
25 | Amitava Bhaduri, Ranga Vemuri |
Parasitic Aware Routing Methodology Based on Higher Order RLCK Moment Metrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 141-146, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Anuradha Agarwal, Ranga Vemuri |
Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 444-452, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Hiroaki Yoshida, Kaushik De, Vamsi Boppana |
Accurate pre-layout estimation of standard cell characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 208-211, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
cell characterization, transistor-level optimization, standard cell |
25 | Lin Jia, Alper Cabuk, Jianguo Ma, Kiat Seng Yeo |
A 52 GHz VCO with Low Phase Noise Implemented in SiGe BiCMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June - 2 July 2003, Calgary, Alberta, Canada, pp. 264-269, 2003, IEEE Computer Society, 0-7695-1944-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Xin Li 0001, Peng Li 0001, Yang Xu 0017, Lawrence T. Pileggi |
Analog and RF circuit macromodels for system-level analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 478-483, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
analog/RF circuits, macromodel |
25 | Carl De Ranter, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen |
CYCLONE: automated design and layout of RF LC-oscillators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10), pp. 1161-1170, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Peng Li 0001, Lawrence T. Pileggi |
A Linear-Centric Modeling Approach to Harmonic Balance Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 634-639, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Andrew B. Kahng, Chung-Wen Albert Tsao |
More Practical Bounded-Skew Clock Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 594-599, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
24 | Chuanyi Yang, Swagato Chakraborty, Dipanjan Gope, Vikram Jandhyala |
A parallel low-rank multilevel matrix compression algorithm for parasitic extraction of electrically large structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 1053-1056, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
parallel, MPI, compression, parasitics |
24 | Dipanjan Gope, Indranil Chowdhury, Vikram Jandhyala |
DiMES: multilevel fast direct solver based on multipole expansions for parasitic extraction of massively coupled 3D microelectronic structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 159-162, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
non-iterative, parasitics, multilevel, multipole |
24 | Dipanjan Gope, Swagato Chakraborty, Vikram Jandhyala |
A fast parasitic extractor based on low-rank multilevel matrix compression for conductor and dielectric modeling in microelectronics and MEMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 794-799, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
conductors and dielectrics, low-rank, parasitics, multilevel |
24 | Marian K. Kazimierczuk, Fabio Corti, Gabriele Maria Lozito, Alberto Reatti |
Non-Isolated Zeta PWM DC-DC Power Converter Analysis for CCM Including Parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 12, pp. 2635-2647, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
24 | Eun-Bin Park, Taigon Song |
Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 31(2), pp. 177-187, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Rashmi Patel, Rajagopalan Chudamani |
Experimental Investigation on Influence of Parasitics on Stability of Multi-Converter System and Analysis of Optimum Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IECON ![In: 49th Annual Conference of the IEEE Industrial Electronics Society, IECON 2023, Singapore, October 16-19, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-3182-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Erez Zolkov, Emanuel Cohen |
Analysis and Modeling of N-Path Circuits Peak Frequency Shift Caused by Switch Parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 69(2), pp. 374-378, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Md Hasibul Amin, Mohammed E. Elbtity, Ramtin Zand |
Interconnect Parasitics and Partitioning in Fully-Analog In-Memory Computing Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2201.12480, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
24 | Md Hasibul Amin, Mohammed E. Elbtity, Ramtin Zand |
Xbar-Partitioning: A Practical Way for Parasitics and Noise Tolerance in Analog IMC Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Emerg. Sel. Topics Circuits Syst. ![In: IEEE J. Emerg. Sel. Topics Circuits Syst. 12(4), pp. 867-877, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Saurabh Sirohi, Beng Woon Lim, Ajay Raman, Frederick A. Anderson |
Impact of Layout Parasitics and Thermal Coupling on PA performance and ruggedness in SiGe HBTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BCICTS ![In: 2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, BCICTS 2022, Phoenix, AZ, USA, October 16-19, 2022, pp. 82-85, 2022, IEEE, 978-1-6654-9132-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar |
From Global Route to Detailed Route: ML for Fast and Accurate Wire Parasitics and Timing Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MLCAD ![In: 2022 ACM/IEEE Workshop on Machine Learning for CAD, MLCAD 2022, Virtual Event, China, September 12-13, 2022, pp. 7-14, 2022, ACM / IEEE, 978-1-4503-9486-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Md Hasibul Amin, Mohammed E. Elbtity, Ramtin Zand |
Interconnect Parasitics and Partitioning in Fully-Analog In-Memory Computing Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, pp. 389-393, 2022, IEEE, 978-1-6654-8485-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Linkai Li, Qiao Zhang, Run Min, Kan Liu 0002, Qiaoling Tong, Dian Lyu |
A Current Reshaping Strategy to Reduce Parasitics-Induced Current Distortion in Discontinuous Conduction Mode Boost Power Factor Correction Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 68(3), pp. 2215-2224, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Hongyue Zhu, Xinhong Cheng, Wai Tung Ng, Dawei Xu, Xinchang Li, Yifei Xia |
A Self-Adaptive Measurement System for IGBT Collector Current Using Package Parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 68(8), pp. 7545-7555, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | David Berthiaume, Jean-Jacques Laurin, Nicolas G. Constantin |
Anti-Series Varactor Network With Improved Linearity Performances in the Presence of Inductive and Capacitive Parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 48325-48340, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Rafid Adnan Khan, Mohammad Muhtady Muhaisin, Gordon W. Roberts |
Extracting RLC Parasitics From a Flexible Electronic Hybrid Assembly Using On-Chip ESD Protection Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 68(10), pp. 4025-4037, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Roberto Rubino, Paolo Stefano Crovetti, Francesco Musolino |
FPGA-Based Relaxation D/A Converters With Parasitics-Induced Error Suppression and Digital Self-Calibration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 68(6), pp. 2494-2507, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Sherin A. Thomas, Sahibia Kaur Vohra, Rahul Kumar, Rohit Sharma, Devarshi Mrinal Das |
Analysis of Parasitics on CMOS based Memristor Crossbar Array for Neuromorphic Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 64th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021, Lansing, MI, USA, August 9-11, 2021, pp. 309-312, 2021, IEEE, 978-1-6654-2461-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Eun-Bin Park, Taigon Song |
An Optimized Standard Cell Design Methodology Targeting Low Parasitics and Small Area for Complementary FETs (CFETs). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 18th International SoC Design Conference, ISOCC 2021, Jeju Island, South Korea, Republic of, October 6-9, 2021, pp. 395-396, 2021, IEEE, 978-1-6654-0174-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Amira Nabil, Jose A. Bernardo, Yue Ma, Mohamed Abouelatta, Ahmed Shaker, Latifa Fakri-Bouchet, Hani F. Ragai, Christian Gontrand |
Electrical modeling of tapered TSV including MOS-Field effect and substrate parasitics: Analysis and application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 100, pp. 104797, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Haoxing Ren, George F. Kokai, Walker J. Turner, Ting-Sheng Ku |
ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 57th ACM/IEEE Design Automation Conference, DAC 2020, San Francisco, CA, USA, July 20-24, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-1085-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Vivek T. Bharambe, Jinwoo Ma, Michael D. Dickey, Jacob J. Adams |
Planar, Multifunctional 3D Printed Antennas Using Liquid Metal Parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 7, pp. 134245-134255, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Antonio Alex-Amor, Javier Moreno-Núñez, Jose-Manuel Fernandez-Gonzalez, Pablo Padilla, Jaime Esteban |
Parasitics Impact on the Performance of Rectifier Circuits in Sensing RF Energy Harvesting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 19(22), pp. 4939, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Martin Kovác, Daniel Arbet, Viera Stopjaková, Michal Sovcik, Lukás Nagy |
Investigation of Low-Voltage, Sub-threshold Charge Pump with Parasitics Aware Design Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2019, Cluj-Napoca, Romania, April 24-26, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-0073-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Zhixing Zhao, Patrick James Artz, Klaus Hempel, Juergen Faul, Tianbing Chen, Richard Taylor, Jerome Mazurier, Carsten Grass, Jan Hoentschel, David Harame, Steffen Lehmann, Luca Lucci, Yogadissen Andee, Alexis Divay, Luca Pirro, Tom Herrmann, Alban Zaka, Ricardo Sousa |
22FDX® fMAX Optimization through Parasitics Reduction and GM Boost. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 49th European Solid-State Device Research Conference, ESSDERC 2019, Cracow, Poland, September 23-26, 2019, pp. 166-169, 2019, IEEE, 978-1-7281-1539-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Piotr Zajac, Mariusz Jankowski, Piotr Amrozik, Michal Szermer |
Application of Offset Trimming Circuit for Reducing the Impact of Parasitics in Capacitive Sensor Readout Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIXDES ![In: 26th International Conference on Mixed Design of Integrated Circuits and Systems, MIXDES 2019, Rzeszów, Poland, June 27-29, 2019, pp. 178-181, 2019, IEEE, 978-83-63578-16-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Axel Hald, Pekka Herzogenrath, Jürgen Scheible, Jens Lienig, Johannes Seelhorst, Peter Brandl |
Full custom MEMS design: A new method for the analysis of motion-dependent parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 63, pp. 362-372, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Anne Beyreuther, Norbert Herfurth, Elham Amini, Tomonori Nakamura, Ingrid De Wolf, Christian Boit |
Photon emission as a characterization tool for bipolar parasitics in FinFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 88-90, pp. 273-276, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Edi Emanovic, Drazen Jurisic, George S. Moschytz |
Influence of CMOS CCII Parasitics in Realization of Two-Integrator Band-Pass Filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018, Windsor, ON, Canada, August 5-8, 2018, pp. 89-92, 2018, IEEE, 978-1-5386-7392-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Georg Gläser, Martin Grabmann, Dirk Nuernbergk |
Impact Rating of Layout Parasitics in Mixed-Signal Circuits: Finding a Needle in a Haystack. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMACD ![In: 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2018, Prague, Czech Republic, July 2-5, 2018, pp. 149-152, 2018, IEEE, 978-1-5386-5153-7. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Fábio Passos, Ricardo Martins 0003, Nuno C. Lourenço, Elisenda Roca, Rafael Castro-López, Ricardo Povoa, António Canelas, Nuno Horta, Francisco V. Fernández 0001 |
Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMACD ![In: 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2018, Prague, Czech Republic, July 2-5, 2018, pp. 1-164, 2018, IEEE, 978-1-5386-5153-7. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Debjani Chakraborty, Elena Breaz, Akshay Kumar Rathore, Fei Gao 0003 |
Parasitics-Assisted Soft-Switching and Secondary Modulated Snubberless Clamping Current-Fed Bidirectional Voltage Doubler for Fuel Cell Vehicles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Veh. Technol. ![In: IEEE Trans. Veh. Technol. 66(2), pp. 1053-1062, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Hossein Ghafarian, Christian Moranz, Mahdi Rajabzadeh, Joachim Leicht, Yiannos Manoli |
A fully integrated charge pump using parasitics to increase the usable capacitance by 25 % and the efficiency by up to 18 % with poly-poly capacitors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017, pp. 835-838, 2017, IEEE, 978-1-5090-6389-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Axel Hald, Johannes Seelhorst, Pekka Herzogenrath, Jürgen Scheible, Jens Lienig |
A new method for the analysis of movement dependent parasitics in full custom designed MEMS sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMACD ![In: 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2017, Giardini Naxos, Italy, June 12-15, 2017, pp. 1-4, 2017, IEEE, 978-1-5090-5052-9. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Moon Seok Kim, William Cane-Wissing, Xueqing Li, Jack Sampson, Suman Datta, Sumeet Kumar Gupta, Vijaykrishnan Narayanan |
Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 12(4), pp. 38:1-38:23, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Mayank Kumar 0001, Rajesh Gupta 0002 |
Stability and Sensitivity Analysis of Uniformly Sampled DC-DC Converter With Circuit Parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(11), pp. 2086-2097, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Yulin Zhang, Edoardo Bonizzoni, Franco Maloberti |
Mismatch and parasitics limits in capacitors-based SAR ADCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016, Monte Carlo, Monaco, December 11-14, 2016, pp. 33-36, 2016, IEEE, 978-1-5090-6113-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Ritwik Chattopadhyay, Mark A. Juds, Paul R. Ohodnicki, Subhashish Bhattacharya |
Modelling, design and analysis of three limb high frequency transformer including transformer parasitics, for SiC Mosfet based three port DAB. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IECON ![In: IECON 2016 - 42nd Annual Conference of the IEEE Industrial Electronics Society, Florence, Italy, October 23-26, 2016, pp. 4181-4186, 2016, IEEE, 978-1-5090-3474-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Mina Wahib, Alois P. Freundorfer |
A miniaturized lumped element directional coupler with parasitics compensation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016, pp. 2383-2386, 2016, IEEE, 978-1-4799-5341-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Om. Prakash, Satish Maheshwaram, Mohit Sharma 0003, Anand Bulusu, A. K. Saxena, S. K. Manhas |
A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 20th International Symposium on VLSI Design and Test, VDAT 2016, Guwahati, India, May 24-27, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-1422-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Jen-Huan Tsai, Sheng-An Ko, Chia-Wei Wang, Yang-Chi Yen, Hui-Huan Wang, Po-Chiun Huang, Po-Hsiang Lan, Meng-Hung Shen |
A 1 V Input, 3 V-to-6 V Output, 58%-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 50(11), pp. 2533-2548, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Adam Rudzinski |
Modelling of battery-powered boost DC-DC power LED driver with parasitics by multivariate power series expansion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 43(9), pp. 1197-1208, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Chika Tanaka, Keiji Ikeda, Masumi Saitoh |
New layout design methodology for monolithically integrated 3D CMOS logic circuits based on parasitics engineering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 45th European Solid State Device Research Conference, ESSDERC 2015, Graz, Austria, September 14-18, 2015, pp. 258-261, 2015, IEEE, 978-1-4673-7133-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Gábor Tóth, Attila Zolomy, Gábor Fehér, Tibor Berceli |
Effect of parasitics in tunable X-band metamaterial isolators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTON ![In: 17th International Conference on Transparent Optical Networks, ICTON 2015, Budapest, Hungary, July 5-9, 2015, pp. 1-4, 2015, IEEE, 978-1-4673-7880-2. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Debjani Chakraborty, Akshay Kumar Rathore, Elena Breaz, Fei Gao 0003 |
Parasitics assisted soft-switching and naturally commutated current-fed bidirectional push-pull voltage doubler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IAS ![In: 2015 IEEE Industry Applications Society Annual Meeting, Addison, TX, USA, October 18-22, 2015, pp. 1-8, 2015, IEEE, 978-1-4799-8394-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Ying Qiu, Xiyou Chen, Chongquan Zhong, Chen Qi |
Uniform Models of PWM DC-DC Converters for Discontinuous Conduction Mode Considering Parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 61(11), pp. 6071-6080, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Ajay N. Bhoj, Niraj K. Jha |
Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 22(3), pp. 548-561, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Rachid Hamani, Cristian Andrei, Bernard Jarry, Mien Lintignat |
LNA circuit design counting the interconnect line parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014, Marseille, France, December 7-10, 2014, pp. 351-354, 2014, IEEE, 978-1-4799-4242-8. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Alberto Rodríguez-Pérez, Manuel Delgado-Restituto, Fernando Medeiro |
Impact of parasitics on even symmetric split-capacitor arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 41(9), pp. 972-987, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Saraju P. Mohanty |
A Special Issue on Power, Parasitics, and Process-Variation (P3) Awareness in Mixed-Signal Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 8(3), pp. 259-260, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Joris Lacord, Perrine Batude, Gérard Ghibaudo, Frédéric Boeuf |
Analytical modeling of parasitics in monolithically integrated 3D inverters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: IEEE International Conference on IC Design & Technology, ICICDT 2012, Austin, TX, USA, May 30 - June 1, 2012, pp. 1-4, 2012, IEEE, 978-1-4673-0146-6. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Giuseppe Pasetti, Nico Costantino, Francesco Tinfena, Riccardo Serventi, Paolo D'Abramo, Sergio Saponara, Luca Fanucci |
Characterization of an Intelligent Power Switch for LED driving with control of wiring parasitics effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, pp. 1119-1120, 2011, IEEE, 978-1-61284-208-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Kuen-Yu Tsai, Wei-Jhih Hsieh, Yuan-Ching Lu, Bo-Sen Chang, Sheng-Wei Chien, Yi-Chang Lu |
A new method to improve accuracy of parasitics extraction considering sub-wavelength lithography effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010, pp. 651-656, 2010, IEEE, 978-1-60558-837-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
24 | Samuel R. Cove, Martin Ordonez, John E. Quaicoe |
Modeling of planar transformer parasitics using design of experiment methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the 23rd Canadian Conference on Electrical and Computer Engineering, CCECE 2010, Calgary, Alberta, Canada, 2-5 May, 2010, pp. 1-5, 2010, IEEE, 978-1-4244-5376-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|