Search results for "pattern-dependent"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
31	Jonathan T.-Y. Chang, Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey	Analysis of pattern-dependent and timing-dependent failures in an experimental test chip.	ITC	1998	DBLP DOI BibTeX RDF
28	Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, M. Enamul Amyeen	Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults.	VLSI Design	2004	DBLP DOI BibTeX RDF
24	Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown	Efficient techniques for gate leakage estimation.	ISLPED	2003	DBLP DOI BibTeX RDF	pattern-dependent, pattern-independent, estimation, leakage, gate leakage
22	Nishath Verghese, Richard Rouse, Philippe Hurat	Predictive models and CAD methodology for pattern dependent variability.	ASP-DAC	2008	DBLP DOI BibTeX RDF
22	Alex M. Thomson	Presynaptic Frequency- and Pattern-Dependent Filtering.	J. Comput. Neurosci.	2003	DBLP DOI BibTeX RDF	fusion core complex, transmitter release, facilitation, depression, synapse
22	Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng	Dynamic Timing Analysis Considering Power Supply Noise Effects.	ISQED	2000	DBLP DOI BibTeX RDF	dynamic timing analysis, input pattern dependent, power supply noise, deep submicron designs
21	Irith Pomeranz, Sudhakar M. Reddy	On diagnosis and diagnostic test generation for pattern-dependenttransition faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
20	Desta Tadesse, D. Sheffield, E. Lenge, R. Iris Bahar, Joel Grodstein	Accurate timing analysis using SAT and pattern-dependent delay models.	DATE	2007	DBLP DOI BibTeX RDF
17	Jaekyun Moon, Jongseung Park	Pattern-dependent noise prediction in signal-dependent noise.	IEEE J. Sel. Areas Commun.	2001	DBLP DOI BibTeX RDF
17	Ahmed M. Shams, Magdy A. Bayoumi	Performance evaluation of 1-bit CMOS adder cells.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
17	Alexander V. Shafarenko, Konstantin S. Turitsyn, Sergei K. Turitsyn	Information-Theory Analysis of Skewed Coding for Suppression of Pattern-Dependent Errors in Digital Communications.	IEEE Trans. Commun.	2007	DBLP DOI BibTeX RDF
17	Jyun-Wei Chen, Ying-Yen Chen, Jing-Jia Liou	Handling Pattern-Dependent Delay Faults in Diagnosis.	VTS	2007	DBLP DOI BibTeX RDF
17	Tudor Murgan, Massoud Momeni, Alberto García Ortiz, Manfred Glesner	A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects.	ICCAD	2006	DBLP DOI BibTeX RDF
15	Di Mu, Tian Xia, Hao Zheng 0001	Data Dependent Jitter Characterization Based on Fourier Analysis.	DFT	2006	DBLP DOI BibTeX RDF
11	Kai Sheng, Weixin Gai, Zeze Feng, Haowei Niu, Bingyi Ye, Hang Zhou	A 128Gb/s PAM-4 Transmitter with Programmable-Width Pulse Generator and Pattern-Dependent Pre-Emphasis in 28nm CMOS.	ISSCC	2023	DBLP DOI BibTeX RDF
11	Vidya A. Chhabria, Sachin S. Sapatnekar	Analysis of Pattern-dependent Rapid Thermal Annealing Effects on SRAM Design.	ISQED	2023	DBLP DOI BibTeX RDF
11	Weishen Chu, Seyyed Ehsan Esfahani Rashidi, Yanli Zhang, Johann Alsmeier, Toshiyuki Sega	An Analytical Model for Thin Film Pattern-dependent Asymmetric Wafer Warpage Prediction.	IMW	2022	DBLP DOI BibTeX RDF
11	Wen-Li Sung, Yiming Li 0005	A Nanosized-Metal-Grain Pattern-Dependent Threshold Voltage Model for the Work Function Fluctuation of GAA Si NW MOSFETs.	IEEE Access	2021	DBLP DOI BibTeX RDF
11	Yi Cai 0002, Hungchang Chien, Meng Xiang, Zihe Hu, Mingyi Gao	Adaptive Pattern-Dependent Equalization for Coherent Optical Fiber Communication Systems.	OFC	2021	DBLP BibTeX RDF
11	Ai He, Weixin Gai, Kai Sheng, Ninghuang Li	An Adaptive DFE Using Pattern-Dependent Data-Level Reference in 28 nm CMOS Technology.	ASICON	2021	DBLP DOI BibTeX RDF
11	Jaehyeong Hong, Dong Hoon Baek, Hyunwoo Son, Cheolmin Ahn, Byungsub Kim, Hong-June Park, Jae-Yoon Sim	A pattern-dependent injection-locked CDR for clock-embedded signaling.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
11	Shanwei Shi, John R. Barry	Multitrack Detection with 2D Pattern-Dependent Noise Prediction.	ICC	2018	DBLP DOI BibTeX RDF
11	Sasan Zhalehpour, Jiachuan Lin, Hassan Sepehrian, Wei Shi 0007, Leslie A. Rusch	Countering Pattern Dependent Effects in SiP Modulators with Iterative Learning Control Predistortion for 64QAM.	ECOC	2018	DBLP DOI BibTeX RDF
11	Jingook Kim	Statistical Analysis for Pattern-Dependent Simultaneous Switching Outputs (SSO) of Parallel Single-Ended Buffers.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
11	Dong Hoon Baek, Byungsub Kim, Hong-June Park, Jae-Yoon Sim	2.6 A 5.67mW 9Gb/s DLL-based reference-less CDR with pattern-dependent clock-embedded signaling for intra-panel interface.	ISSCC	2014	DBLP DOI BibTeX RDF
11	Xiaoliang Zhu, Kishore Padmaraju, Long Chen, Dylan F. Logan, Jason J. Ackert, Andrew P. Knights, Michal Lipson, Keren Bergman	Pattern-dependent performance of microring modulators.	OFC/NFOEC	2013	DBLP BibTeX RDF
11	Kyriakos E. Zoiros, C. L. Janer, Michael J. Connelly, Evangelia Dimitriadou	Reduction of pattern-dependent amplitude modulation for RZ data in semiconductor optical amplifier with delay interferometer.	CSNDSP	2012	DBLP DOI BibTeX RDF
11	Atul Gupta, Ajay Kumar, Manas Chhabra	Characterizing Pattern Dependent Delay Effects in DDR Memory Interfaces.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
11	Lele Jiang, Xiaojing Qin, Lifu Chang, Yuhua Cheng	Characterization and analysis of pattern dependent variation-aware interconnects for a 65nm technology.	ASICON	2011	DBLP DOI BibTeX RDF
11	Yun Ye, Frank Liu 0001, Min Chen 0024, Yu Cao 0001	Variability analysis under layout pattern-dependent rapid-thermal annealing process.	DAC	2009	DBLP DOI BibTeX RDF	dopant activation, layout pattern, rapid-thermal annealing, threshold voltage variation, physical design
11	Puneet Gupta 0001, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester	Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
11	Subarna Sinha, Jianfeng Luo, Charles C. Chiang	Model Based Layout Pattern Dependent Metal Filling Algorithm for Improved Chip Surface Uniformity in the Copper Process.	ASP-DAC	2007	DBLP DOI BibTeX RDF
11	Xiaoning Qi, Alex Gyure, Yansheng Luo, Sam C. Lo, Mahmoud Shahram, Kishore Singhal	Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	measurement, process variations, extraction, VLSI interconnects
11	Yungsoo Kim, Hwang-Soo Lee	A decision-feedback equalizer with pattern-dependent feedback for magnetic recording channels.	IEEE Trans. Commun.	2001	DBLP DOI BibTeX RDF
11	Vladimir V. Savchenko, Stanislav Sedukhin	Pattern Dependent Reconstruction of Raster Digital Elevation Models from Contour Maps.	VIIP	2001	DBLP BibTeX RDF
11	Irith Pomeranz, Sudhakar M. Reddy	On diagnosis of pattern-dependent delay faults.	DAC	2000	DBLP DOI BibTeX RDF
11	Takeshi Aihara, Minoru Tsukada	Temporal-Pattern Dependent Spatial-Distribution of LTP and LTD in Hippocampal CA1 Area.	ICONIP	1998	DBLP BibTeX RDF
11	Patrick R. Trischitta, Peddapullaiah Sannuti	The accumulation of pattern-dependent jitter for a chain of fiber optic regenerators.	IEEE Trans. Commun.	1988	DBLP DOI BibTeX RDF
11	Srinivas Raghvendra, Philippe Hurat	DFM: Linking Design and Manufacturing.	VLSI Design	2005	DBLP DOI BibTeX RDF
11	Yasuo Takahashi, Akira Fujiwara, Yukinori Ono, Katsumi Murase	Silicon Single-Electron Devices and Their Applications.	ISMVL	2000	DBLP DOI BibTeX RDF
11	Alessandro Bogliolo, Luca Benini, Giovanni De Micheli	Characterization-Free Behavioral Power Modeling.	DATE	1998	DBLP DOI BibTeX RDF	Modeling, Power consumption, RTL Simulation
8	Subodh M. Reddy, Rajeev Murgai	Accurate Substrate Noise Analysis Based on Library Module Characterization.	VLSI Design	2006	DBLP DOI BibTeX RDF
5	Xiaojun Ma, Masoud Hashempour, Lei Wang 0003, Fabrizio Lombardi	Manufacturing yield of QCA circuits by synthesized DNA self-assembled templates.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	design, manufacturing, nanotechnology, defect tolerance
5	Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir	Maximum circuit activity estimation using pseudo-boolean satisfiability.	DATE	2007	DBLP DOI BibTeX RDF
5	Ashesh Rastogi, Kunal P. Ganeshpure, Sandip Kundu	A Study on Impact of Leakage Current on Dynamic Power.	ISCAS	2007	DBLP DOI BibTeX RDF
5	Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip Kundu	An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect.	VLSI Design	2007	DBLP DOI BibTeX RDF
5	Ashesh Rastogi, Wei Chen, Sandip Kundu	On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method.	DAC	2007	DBLP DOI BibTeX RDF
5	Wenjian Yu, Mengsheng Zhang, Zeyi Wang	Efficient 3-D extraction of interconnect capacitance considering floating metal fills with boundary element method.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
5	Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi 0001, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi	A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors.	ISMVL	2006	DBLP DOI BibTeX RDF
5	Anthony Chan Carusone	Jitter equalization for binary baseband communication.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
5	Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel	Implementing a Scheme for External Deterministic Self-Test.	VTS	2005	DBLP DOI BibTeX RDF	Deterministic self-test, external BIST, test data compression, test resource partitioning
5	Hiroshi Inokawa, Yasuo Takahashi	Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic.	ISMVL	2003	DBLP DOI BibTeX RDF
5	Byungwoo Choi, D. M. H. Walker	Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation.	VTS	2000	DBLP DOI BibTeX RDF	interconnect coupling, delay fault model, process variation, timing analysis, delay fault test
5	Vikas Mehrotra, Shiou Lin Sam, Duane S. Boning, Anantha P. Chandrakasan, Rakesh Vallishayee, Sani R. Nassif	A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance.	DAC	2000	DBLP DOI BibTeX RDF
5	Radu Marculescu, Diana Marculescu, Massoud Pedram	Sequence compaction for power estimation: theory and practice.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
5	Michel Renovell, Florence Azaïs, Yves Bertrand	Detection of Defects Using Fault Model Oriented Test Sequences.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	fault modeling, defect
5	Radu Marculescu, Diana Marculescu, Massoud Pedram	Probabilistic modeling of dependencies during switching activity analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
5	Nicola Dragone, Roberto Zafalon, Carlo Guardiani, Cristina Silvano	Power invariant vector compaction based on bit clustering and temporal partitioning.	ISLPED	1998	DBLP DOI BibTeX RDF	low power VLSI design, vector compaction, Markov chains, power estimation
5	Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Riccò	Gate-level power and current simulation of CMOS integrated circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
5	Denis Deschacht, Michel Robert, Nadine Azémard-Crestani, Daniel Auvergne	Post-layout timing simulation of CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
5	Denis Deschacht, P. Pinede, Michel Robert, Daniel Auvergne	Path runner: an accurate and fast timing analyser.	EURO-DAC	1990	DBLP DOI BibTeX RDF