Search results for "pins"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
70	Makoto Sugihara, Hiroto Yasuura	Optimization of Test Accesses with a Combined BIST and External Test Scheme.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	external test, CBET, test access, external pins, BIST, test scheduling, test time, test bus
70	Jian-hua Cheng, Xinzhe Wang, Xu-hong Cheng, Yan-ling Hao	Research and Design of PINS Simulator Based on UnderWater Vehicle Space Model.	WKDD	2009	DBLP DOI BibTeX RDF
64	Dimitri do B. DeFigueiredo	The Case for Mobile Two-Factor Authentication.	IEEE Secur. Priv.	2011	DBLP DOI BibTeX RDF	mobile authentication, online PINs, offline PINs, mobile computing, mobile phones, computer security, passwords, PINs, two-factor authentication
51	Matthew G. Stout, Kenneth P. Tumin	Innovative Test Solutions for Pin-Limited Microcontrollers.	ISQED	2008	DBLP DOI BibTeX RDF	Freescale, Stout, Tumin, test, testing, DFT, scan, microcontroller, design-for-test, pins
50	Min Zhao 0001, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda	Optimal placement of power-supply pads and pins.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
50	María-Del-Pilar Villamil, Claudia Roncancio, Cyril Labbé	PinS: Peer-to-Peer Interrogation and Indexing System.	IDEAS	2004	DBLP DOI BibTeX RDF
49	Jieyi Long, Seda Ogrenci Memik	A framework for optimizing thermoelectric active cooling systems.	DAC	2010	DBLP DOI BibTeX RDF	thermal runaway, thermoelectric cooling, optimization
49	Tao Xu 0002, Krishnendu Chakrabarty	Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips.	DAC	2008	DBLP DOI BibTeX RDF	droplet-based microfluidics, electrowetting-on-dielectric, lab-on-chip
49	Yuko Uematsu, Hideo Saito	Interactive AR bowling system by vision-based tracking.	Advances in Computer Entertainment Technology	2007	DBLP DOI BibTeX RDF	bowling, AR, interactive application, vision-based tracking
49	Po-Han Lee, Chien-Hung Huang, Jywe-Fei Fang, Jeffrey J. P. Tsai, Ka-Lok Ng	Study of the protein-protein interaction networks via random graph approach.	IEEE ICCI	2005	DBLP DOI BibTeX RDF
41	Lizy Kurian John	VaWiRAM: a variable width random access memory module.	VLSI Design	1996	DBLP DOI BibTeX RDF	VaWiRAM, variable width random access memory, flexible memory systems, configuration pins, pass gates, reconfigurability, reconfigurable architectures, memory architecture, programmable logic, random-access storage, integrated circuit interconnections, programmable logic devices, programmable interconnect
41	Santonu Sarkar, Anupam Basu, Arun K. Majumdar	Representation and Synthesis of Interface of a Circuit for its Reuse.	VLSI Design	1996	DBLP DOI BibTeX RDF	VaWiRAM, variable width random access memory, flexible memory systems, configuration pins, pass gates, reconfigurability, reconfigurable architectures, memory architecture, programmable logic, random-access storage, integrated circuit interconnections, programmable logic devices, programmable interconnect
41	Jacob Savir	Module level weighted random patterns.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	module level self-test architecture, pseudorandom pattern generator, universal weighting generator, scan latch, near-optimal weight, signal pins, weight control function, self-test time, logic testing, probability, integrated circuit testing, automatic testing, multivalued logic circuits, boundary scan testing, scan test, weighted random patterns, multiple input signature register
41	Min Zhao 0001, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda	Optimal placement of power supply pads and pins.	DAC	2004	DBLP DOI BibTeX RDF	pad optimization, pad placement
41	Koushik Sinha, Susmita Sur-Kolay, Bhargab B. Bhattacharya, P. S. Dasgupta	Partitioning Routing Area into Zones with Distinct Pins.	VLSI Design	2001	DBLP DOI BibTeX RDF
39	José Ignacio Hidalgo, Juan Lanchares, Román Hermida	Partitioning and Placement for Multi-FPGA Systems Using Genetic Algorithms.	EUROMICRO	2000	DBLP DOI BibTeX RDF
39	Charles H. Ng	A "gridless" Variable-Width Channel Router for Marco Cell Design.	DAC	1987	DBLP DOI BibTeX RDF
38	Michael A. Cunningham, Danielle Pins, Zoltán Dezso, Maricel Torrent, Aparna Vasanthakumar, Abhishek Pandey	PINNED: identifying characteristics of druggable human proteins using an interpretable neural network.	J. Cheminformatics	2023	DBLP DOI BibTeX RDF
38	Lena Recki, Dennis Lawo, Veronika Krauß, Dominik Pins	A Qualitative Exploration of User-Perceived Risks of AI to Inform Design and Policy.	MuC (Workshopband)	2023	DBLP DOI BibTeX RDF
38	Fatemeh Alizadeh, Dominik Pins, Gunnar Stevens	User-friendly Explanatory Dialogues.	MuC (Workshopband)	2023	DBLP DOI BibTeX RDF
38	Dominik Pins, Timo Jakobi, Gunnar Stevens, Fatemeh Alizadeh, Jana Krüger	Finding, getting and understanding: the user journey for the GDPR'S right to access.	Behav. Inf. Technol.	2022	DBLP DOI BibTeX RDF
38	Dominik Pins, Dennis Paul	Towards a Framework for Supporting User Satisfaction of Conversational Agents according to the Usability Norm DIN EN ISO 9241-11.	Wirtschaftsinformatik	2022	DBLP BibTeX RDF
38	Dominik Pins, Timo Jakobi, Alexander Boden, Fatemeh Alizadeh, Volker Wulf	Alexa, We Need to Talk: A Data Literacy Approach on Voice Assistants.	Conference on Designing Interactive Systems	2021	DBLP DOI BibTeX RDF
38	Timo Jakobi, Gunnar Stevens, Maximilian von Grafenstein, Dominik Pins, Alexander Boden	Die nutzerInnenfreundliche Formulierung von Zwecken der Datenverarbeitung von Sprachassistenten.	MuC	2020	DBLP DOI BibTeX RDF
38	Dominik Pins, Alexander Boden, Britta Essing, Gunnar Stevens	"Miss Understandable" - Eine Studie zur Aneignung von Sprachassistenten und dem Umgang mit Fehlinteraktionen.	MuC	2020	DBLP DOI BibTeX RDF
38	Bersain Alexander Reyes, Hugo F. Posada-Quintero, Justin R. Bales, Amanda L. Clement, George D. Pins, Albert Swiston, Jarno Riistama, John P. Florian, Barbara Shykoff, Michael Qin, Ki H. Chon	Novel Electrodes for Underwater ECG Monitoring.	IEEE Trans. Biomed. Eng.	2014	DBLP DOI BibTeX RDF
38	Renaud Jardri, Delphine Pins, Véronique Houfflin-Debarge, Caroline Chaffiotte, Nathalie Rocourt, Jean-Pierre Pruvo, Marc Steinling, Pierre Delion, Pierre Thomas	Fetal cortical activation to sound at 33 weeks of gestation: A functional MRI study.	NeuroImage	2008	DBLP DOI BibTeX RDF
38	Renaud Jardri, Delphine Pins, Maxime Bubrovszky, Pascal Despretz, Jean-Pierre Pruvo, Marc Steinling, Pierre Thomas	Self awareness and speech processing: An fMRI study.	NeuroImage	2007	DBLP DOI BibTeX RDF
38	J. R. Foucher, P. Vidailhet, S. Chanraud, D. Gounot, D. Grucker, Delphine Pins, C. Damsa, J.-M. Danion	Functional integration in schizophrenia: too little or too much? Preliminary results on fMRI data.	NeuroImage	2005	DBLP DOI BibTeX RDF
38	Markus Pins	Analyse und Auswahl von Algorithmen zur Datenkompression unter besonderer Berücksichtigung von Bildern und Bildfolgen.		1990	RDF
38	Markus Pins, Hermann Hild	Variations on a Dither Algorithm.	Eurographics	1989	DBLP DOI BibTeX RDF
31	Priyadarsan Patra, Donald S. Fussell	Power-efficient delay-insensitive codes for data transmission.	HICSS (1)	1995	DBLP DOI BibTeX RDF	telecommunication switching, power-efficient delay-insensitive codes, dynamic delay-insensitive codes, switching energy optimization, data pins, protocols, delays, power consumption, codes, asynchronous systems, data communication, data communication, data transmission, energy reduction, delay-insensitive circuits
31	Stanley E. Lass	Automated printed circuit routing with a stepping aperture.	Commun. ACM	1969	DBLP DOI BibTeX RDF	circuit board, printed circuit, stepping aperture, routing, interconnections, lines, computer program, vias, pins, aperture
31	Vashek Matyas, Daniel Cvrcek, Jan Krhovjak, Marek Kumpost	Authorizing Card Payments with PINs.	Computer	2008	DBLP DOI BibTeX RDF	Chip and PIN technology, PIN pads, e-commerce
31	Travis Kirton, Hideaki Ogawa, Christa Sommerer, Laurent Mignonneau	PINS: a prototype model towards thedefinition of surface games.	ACM Multimedia	2008	DBLP DOI BibTeX RDF	fluid interaction, multitouch-tangible, relative environments, surface games, tangible playware
31	Wei-Chiu Tseng, Yu-Hsing Chen, Rung-Bin Lin	Router and cell library co-development for improving redundant via insertion at pins.	ICCD	2008	DBLP DOI BibTeX RDF
31	Ugur Çilingiroglu	Magnetic In-circuit Testing of Multiple Power and Ground Pins for Open Faults.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	in-circuit testing, opens testing, Hall sensors
29	Bo-Shiun Wu, Tsung-Yi Ho	Bus-pin-aware bus-driven floorplanning.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	bus planning, floorplanning
29	Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Lee, Yao-Wen Chang	Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
29	Muhammad Tahir, Gilles Bailly, Eric Lecolinet	Exploring the impulsion and vibration effects of tactile patterns.	BCS HCI (2)	2008	DBLP DOI BibTeX RDF	braille cell, tactile patterns, selection, tactile feedback, vibration, impulsion
29	Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Postplacement rewiring by exhaustive search for functional symmetries.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	VLSI, placement, rewiring
29	Hazem M. Abbas	A Novel Fast Orthogonal Search Method for design of functional link networks and their use in system identification.	SMC	2007	DBLP DOI BibTeX RDF
29	Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Li, Yao-Wen Chang	Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction.	ICCAD	2007	DBLP DOI BibTeX RDF
29	Alexander De Luca, Roman Weiss, Heinrich Hussmann	PassShape: stroke based shape passwords.	OZCHI	2007	DBLP DOI BibTeX RDF	PassShape, shape passwords, security, authentication
29	Ryo Kikuuwe, Akihito Sano, Hiromi Mochiyama, Naoyuki Takesue, Hideo Fujimoto	Enhancing haptic detection of surface undulation.	ACM Trans. Appl. Percept.	2005	DBLP DOI BibTeX RDF	sensation enhancement, surface undulation, tactile contact lens, Haptics, tactile sensing
29	Jurjen Westra, Patrick Groeneveld	Post-Placement Pin Optimiztion.	ISVLSI	2005	DBLP DOI BibTeX RDF
29	Chien-Hung Huang, Jywe-Fei Fang, Jeffrey J. P. Tsai, Ka-Lok Ng	Topological Robustness of the Protein-Protein Interaction Networks.	Systems Biology and Regulatory Genomics	2005	DBLP DOI BibTeX RDF
29	Mihir A. Shah, Janak H. Patel	Enhancement of the Illinois Scan Architecture for Use with Multiple Scan Inputs.	ISVLSI	2004	DBLP DOI BibTeX RDF
29	A. T. Sivaram, Masashi Shimanouchi, Howard Maassen, Robert Jackson	Tester Architecture For The Source Synchronous Bus.	ITC	2004	DBLP DOI BibTeX RDF
29	Leon van de Logt, Frank van der Heyden, Tom Waayers	An extension to JTAG for at-speed debug on a system.	ITC	2003	DBLP DOI BibTeX RDF
29	Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier	Enhanced Reduced Pin-Count Test for Full-Scan Design.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	reduced pin-count test, core test, design for testability, ATE, boundary-scan test, scan test
29	Yu Huang 0005, Nilanjan Mukherjee 0001, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy	Constraint Driven Pin Mapping for Concurrent SOC Testing.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
29	Peng-Cheng Koo, San-Liek Pang	A New Technique to Ensure Quality of Test Patterns.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
29	T. W. Her, Martin D. F. Wong	Module implementation selection and its application to transistor placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
29	Wuudiann Ke	Hybrid Pin Control Using Boundary-Scan And Its Applications.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	Boundary-Scan (B-S), Hybrid Pin Control, Fault Injection, Delay Test
21	Patrick Schaumont, Serge Vernalde, Luc Rijnders, Marc Engels, Ivo Bolsens	A Programming Environment for the Design of Complex High Speed ASICs.	DAC	1998	DBLP DOI BibTeX RDF	C++, congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
21	Shih-Chieh Chang, David Ihsin Cheng	Efficient Boolean Division and Substitution.	DAC	1998	DBLP DOI BibTeX RDF	congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
21	Nuno Alexandre Marques, Mattan Kamon, Jacob White 0001, Luís Miguel Silveira	A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-Order Modeling of 3D Interconnects.	DAC	1998	DBLP DOI BibTeX RDF	congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
21	Jason Cong, Chang Wu	Optimal FPGA Mapping and Retiming with Efficient Initial State Computation.	DAC	1998	DBLP DOI BibTeX RDF	congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
21	Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey	A Methodology for Guided Behavioral-Level Optimization.	DAC	1998	DBLP DOI BibTeX RDF	congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
21	Phiroze N. Parakh, Richard B. Brown, Karem A. Sakallah	Congestion Driven Quadratic Placement.	DAC	1998	DBLP DOI BibTeX RDF	congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
21	Wen-Jong Fang, Allen C.-H. Wu	Performance-Driven Multi-FPGA Partitioning Using Functional Clustering and Replication.	DAC	1998	DBLP DOI BibTeX RDF	congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
21	Chunho Lee, Johnson Kin, Miodrag Potkonjak, William H. Mangione-Smith	Media Architecture: General Purpose vs. Multiple Application-Specific Programmable Processor.	DAC	1998	DBLP DOI BibTeX RDF	congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
21	Byron Krauter, Sharad Mehrotra	Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis.	DAC	1998	DBLP DOI BibTeX RDF	congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
21	Jaewon Oh, Massoud Pedram	Multi-Pad Power/Ground Network Design for Uniform Distribution of Ground Bounce.	DAC	1998	DBLP DOI BibTeX RDF	congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
21	Tong Li, Sung-Mo Kang	Layout Extraction and Verification Methodology CMOS I/O Circuits.	DAC	1998	DBLP DOI BibTeX RDF	congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
21	Maogang Wang, Prithviraj Banerjee, Majid Sarrafzadeh	Potential-NRG: Placement with Incomplete Data.	DAC	1998	DBLP DOI BibTeX RDF	congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
21	Victor N. Kravets, Karem A. Sakallah	M32: A Constructive multilevel Logic Synthesis System.	DAC	1998	DBLP DOI BibTeX RDF	congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
21	Yuji Kukimoto, Robert K. Brayton, Prashant Sawkar	Delay-Optimal Technology Mapping by DAG Covering.	DAC	1998	DBLP DOI BibTeX RDF	congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
21	Gopalakrishnan Vijayan	Generalization of Min-Cut Partitioning to Tree Structures and Its Applications.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	min-cut partitioning, hyperedges, VLSI design applications, iterative improvement heuristic, routing, computational complexity, data structures, trees (mathematics), hypergraph, minimisation, minimisation, tree structures, vertices, cost function, nodes, pins
21	Hailong Yang, Yinghao Liu, Tian Xia	Defect Detection Scheme of Pins for Aviation Connectors Based on Image Segmentation and Improved RESNET-50.	Int. J. Image Graph.	2024	DBLP DOI BibTeX RDF
21	Ke Tang, Lang Feng, Zhongfeng Wang 0001	Mixed Integer Programming based Placement Refinement by RSMT Model with Movable Pins.	ACM Trans. Design Autom. Electr. Syst.	2024	DBLP DOI BibTeX RDF
21	H. T. M. A. Riyadh, Divyanshu Bhardwaj, Adrian Dabrowski, Katharina Krombholz	Usable Authentication in Virtual Reality: Exploring the Usability of PINs and Gestures.	ACNS (3)	2024	DBLP DOI BibTeX RDF
21	Rafid Adnan Khan, Saad Yousaf, Gordon W. Roberts	An In-Circuit Test Method for Measuring the Bonding Resistances of Individual IC Pins From an Interconnected Multiple IC Assembly of Flexible Hybrid Electronics.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
21	Umberto Amato, Anestis Antoniadis, Italia De Feis, Domenico Fazio, Caterina Genua, Irène Gijbels, Donatella Granata, Antonino La Magna, Daniele Pagano, Gabriele Tochino, Patrizia Vasquez	Predictive Maintenance of Pins in the ECD Equipment for Cu Deposition in the Semiconductor Industry.	Sensors	2023	DBLP DOI BibTeX RDF
21	Asad Ali 0008, Olga Galinina, Jiri Hosek, Sergey Andreev 0001	Performance Scaling of mmWave Personal IoT Networks (PINs) for XR Applications.	ICC Workshops	2023	DBLP DOI BibTeX RDF
21	Shijia Ding, Yangyang Wang 0005, Tuoran Wang, Hongyu Wang 0001	Self-Attention Mechanism based Visual Detection for Transmission Line Pins.	ICDLT	2023	DBLP DOI BibTeX RDF
21	Xiaokaiti Maihebubai	Defect Detection Method of Overhead Line Pins Based on Multi-Sensor Data Acquisition of UAV.	ICMTEL (1)	2023	DBLP DOI BibTeX RDF
21	David A. Basin, Patrick Schaller, Jorge Toro-Pozo	Inducing Authentication Failures to Bypass Credit Card PINs.	USENIX Security Symposium	2023	DBLP BibTeX RDF
21	Luca Cassano, Mihalis Psarakis, Marcello Traiola, Alberto Bosio (eds.)	IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023, Juan-Les-Pins, France, October 3-5, 2023	DFT	2023	DBLP DOI BibTeX RDF
21	Momona Mizota, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai	A Block Partitioning Method for Region Exhaustive Test to Reduce the Number of Test Patterns and Improve Gate Exhaustive Fault Coverage.	DFT	2023	DBLP DOI BibTeX RDF
21	Tobias Kilian, Abhishek Sengupta, Daniel Tille, Martin Huch, Ulf Schlichtmann	An efficient High-Volume Production Performance Screening using On-Chip Ring Oscillators.	DFT	2023	DBLP DOI BibTeX RDF
21	Govind Rajhans Jadhav, Sonali Shukla, Virendra Singh	On Attacking Scan-based Logic Locking Schemes.	DFT	2023	DBLP DOI BibTeX RDF
21	S. Bouat, Stéphanie Anceau, Laurent Maingault, Jessy Clédière, Luc Salvo, Rémi Tucoulou	X ray nanoprobe for fault attacks and circuit edits on 28-nm integrated circuits.	DFT	2023	DBLP DOI BibTeX RDF
21	Christos Georgakidis, Dimitris Valiantzas, Stavros Simoglou, Iordanis Lilitsis, Nikolaos Chatzivangelis, Ilias Golfos, Marko S. Andjelkovic, Christos P. Sotiriou, Milos Krstic	Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis.	DFT	2023	DBLP DOI BibTeX RDF
21	Zahin Ibnat, Hadi Mardani Kamali, Farimah Farahmandi	Iterative Mitigation of Insecure Resource Sharing Produced by High-level Synthesis.	DFT	2023	DBLP DOI BibTeX RDF
21	Shruti Dutta, Sai Charan Rachamadugu Chinni, Abhishek Das, Nur A. Touba	Highly Efficient Layered Syndrome-based Double Error Correction Utilizing Current Summing in RRAM Cells to Simplify Decoder.	DFT	2023	DBLP DOI BibTeX RDF
21	Yudai Toyooka, Haruki Watanabe, Toshinori Hosokawa, Masayoshi Yoshimura	An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing.	DFT	2023	DBLP DOI BibTeX RDF
21	Toshinori Hosokawa, Kyohei Iizuka, Masayoshi Yoshimura	An Evaluation of a Testability Measure for State Assignment to Estimate Transition Fault Coverage for Controllers.	DFT	2023	DBLP DOI BibTeX RDF
21	Krishnendu Guha, Gouriprasad Bhattacharyya	A Self Aware Security Approach for Real Time Neural Network Applications from Row Hammer Attacks in Multi FPGA Multi User Environment.	DFT	2023	DBLP DOI BibTeX RDF
21	Payam Habiby, Sebastian Huhn 0001, Rolf Drechsler	RC-IJTAG: A Methodology for Designing Remotely-Controlled IEEE 1687 Scan Networks.	DFT	2023	DBLP DOI BibTeX RDF
21	Amalia-Artemis Koufopoulou, Athanasios Papadimitriou, Aggelos Pikrakis, Mihalis Psarakis, David Hély	On the Prediction of Hardware Security Properties of HLS Designs Using Graph Neural Networks.	DFT	2023	DBLP DOI BibTeX RDF
21	Kevin Böhmer, Bruno Forlin, Carlo Cazzaniga, Paolo Rech, Gianluca Furano, Nikolaos Alachiotis 0001, Marco Ottavi	Neutron Radiation Tests of the NEORV32 RISC-V SoC on Flash-Based FPGAs.	DFT	2023	DBLP DOI BibTeX RDF
21	Francisco Fuentes, Sergi Alcaide, Raimon Casanova, Jaume Abella 0001	Black-Box IP Validation with the SafeTI Traffic Injector: A Success Story.	DFT	2023	DBLP DOI BibTeX RDF
21	Yu Xie, Wen-Yue Yu, Ning Zhang, He Chen, Yizhuang Xie	Partial Triple Modular Redundancy Method for Fault-Tolerant Circuit based on HITS Algorithm.	DFT	2023	DBLP DOI BibTeX RDF
21	Senling Wang, Shaoqi Wei, Jun Ma, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi, Akihiro Shimizu, Xiaoqing Wen, Tianming Ni	SASL-JTAG: A Light-Weight Dependable JTAG.	DFT	2023	DBLP DOI BibTeX RDF
21	Alexandra Takou, Pavlos Stoikos, Moysis Moysis, George Floros 0002, Nestoras E. Evmorfopoulos, Georgios I. Stamoulis	An Efficient Security Closure Methodology for EM-based Attacks on Power Grid Structures.	DFT	2023	DBLP DOI BibTeX RDF
21	Carolina Imianosky, Douglas A. dos Santos, Douglas R. Melo, Felipe Viel, Luigi Dilillo	Implementation and Reliability Evaluation of a RISC-V Vector Extension Unit.	DFT	2023	DBLP DOI BibTeX RDF
21	Yu-Guang Chen, Ying-Jing Tsai	Reliability of Computing-In-Memories: Threats, Detection Methods, and Mitigation Approaches.	DFT	2023	DBLP DOI BibTeX RDF
21	Cristiana Bolchini, Luca Cassano, Antonio Miele, Alessandro Nazzari, Dario Passarello	Analyzing the Reliability of Alternative Convolution Implementations for Deep Learning Applications.	DFT	2023	DBLP DOI BibTeX RDF