Search results for "pipelining"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
126	Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou 0001	Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning.	ASP-DAC	2007	DBLP DOI BibTeX RDF	graph-based approach, microarchitecture pipelining optimization, throughput-aware floorplanning, block pipelining, interconnect pipelining, graph-based algorithm, mixed integer linear programming, wire pipelining
126	Jian Wang, Guang R. Gao	Pipelining-Dovetailing: A Transformation to Enhance Software Pipelining for Nested Loops.	CC	1996	DBLP DOI BibTeX RDF	Very Long Instruction Word(VLIW), Instruction-Level Parallelism, Software Pipelining, Superscalar, Nested Loop, Loop Scheduling, Fine-Grain Parallelism
106	Monica S. Lam	Software pipelining: an effective scheduling technique for VLIW machines (with retrospective)	Best of PLDI	1988	DBLP DOI BibTeX RDF
103	João M. P. Cardoso	Dynamic loop pipelining in data-driven architectures.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	compilation, reconfigurable computing, software pipelining, dataflow, data-driven architectures
88	Reese B. Jones, Vicki H. Allan	Software pipelining: a comparison and improvement.	MICRO	1990	DBLP BibTeX RDF	recognition of parallelism, software pipelining, operation scheduling
76	Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin	Design tradeoffs in high speed multipliers and FIR filters.	VLSI Design	1996	DBLP DOI BibTeX RDF	high speed multipliers, high speed FIR filters, modified Booth recoding, pipeline granularity, transistor count, activity factor reduction, guarded evaluation, gate-level pipelining, half-bit level pipelining, bit-level pipelining, delay, clocking, digital filters, FIR filters, multiplying circuits, power dissipation, design tradeoffs, pipeline arithmetic, operation speed
76	Miodrag Potkonjak, Jan M. Rabaey	Optimizing throughput and resource utilization using pipelining: Transformation based approach.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
73	Han-Saem Yun, Jihong Kim 0001, Soo-Mook Moon	Time Optimal Software Pipelining of Loops with Control Flows.	Int. J. Parallel Program.	2003	DBLP DOI BibTeX RDF	compiler optimization, instruction-level parallelism, software pipelining, VLIW
68	Mark G. Stoodley, Corinna G. Lee	Software Pipelining Loops with Conditional Branches.	MICRO	1996	DBLP DOI BibTeX RDF
66	Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao	Single-dimension software pipelining for multidimensional loops.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	Software pipelining, loop transformation, modulo scheduling
66	Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews	High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips.	ARVLSI	1995	DBLP DOI BibTeX RDF	counterflow-clocked pipelining, HDTV subband vector quantizer chips, clock skew problems, back-propagating clock signals, high speed clocks, dynamic latches, composition rules, two-dimensional data-flow, image compression chip set, subband VQ, VLSI, timing, image coding, pipeline processing, digital signal processing chips, vector quantisation, telecommunication computing, clock distribution, VLSI chips, high definition television
63	Smita Bakshi, Daniel Gajski	Performance-constrained hierarchical pipelining for behaviors, loops, and operations.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	DSP (digital signal processing) systems, hierarchical pipelining, pipelined systems, scheduling, component selection, loop pipelining
60	Kieron Turkington, Turkington A. Constantinides, Kostas Masselos, Peter Y. K. Cheung	Outer Loop Pipelining for Application Specific Datapaths in FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
60	Pallav Gupta, Niraj K. Jha	An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology.	DATE	2004	DBLP DOI BibTeX RDF
60	Bogong Su, Jian Wang 0046, Erh-Wen Hu, Joseph B. Manzano	Software De-Pipelining Technique.	SCAM	2004	DBLP DOI BibTeX RDF
58	Haitao Wei, Junqing Yu, Huafei Yu, Guang R. Gao	Minimizing communication in rate-optimal software pipelining for stream programs.	CGO	2010	DBLP DOI BibTeX RDF	dfbrook, multi-core, software pipelining, cell processor, stream programs
58	Won So, Alexander G. Dean	Complementing software pipelining with software thread integration.	LCTES	2005	DBLP DOI BibTeX RDF	TI C6000, DSP, software pipelining, VLIW, stream programming, coarse-grain parallelism, software thread integration
56	Dragan Milicev, Zoran Jovanovic	A Formal Model of Software Pipelining Loops with Conditions.	IPPS	1997	DBLP DOI BibTeX RDF	software pipelining loops, PSP model, parallel programming, finite state machine, formal model, software pipelining, parallelizing loops, conditional branches
53	Mohammed Fellahi, Albert Cohen 0001	Software Pipelining in Nested Loops with Prolog-Epilog Merging.	HiPEAC	2009	DBLP DOI BibTeX RDF
53	Lingfang Zeng, Dan Feng 0001, Fang Wang 0001	Pipelining Network Storage I/O.	International Conference on Computational Science (1)	2006	DBLP DOI BibTeX RDF
53	Guy E. Blelloch, Margaret Reid-Miller	Pipelining with Futures.	Theory Comput. Syst.	1999	DBLP DOI BibTeX RDF
53	Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah	Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
53	Monica Lam 0001	Software Pipelining: An Effective Scheduling Technique for VLIW Machines.	PLDI	1988	DBLP DOI BibTeX RDF
50	Takuya Miyamaru, Hiroshi Mineno, Yoshiaki Terashima, Yuichi Tokunaga, Tadanori Mizuno	State-Based Pipelining for Reprogramming Wireless Sensor Networks.	KES (3)	2007	DBLP DOI BibTeX RDF	Wireless sensor network, Pipelining, Reprogramming
50	Yuan-man Tong, Zhiying Wang 0003, Kui Dai, Hongyi Lu	Designing Power Analysis Resistant and High Performance Block Cipher Coprocessor Using WDDL and Wave-Pipelining.	Inscrypt	2006	DBLP DOI BibTeX RDF	WDDL, power analysis resistant, block cipher, design flow, Wave-pipelining
50	Noureddine Chabini, Wayne H. Wolf	An approach for integrating basic retiming and software pipelining.	EMSOFT	2004	DBLP DOI BibTeX RDF	embedded systems, system-on-chip, timings, instruction-level parallelism, software pipelining, VLIW, retiming, superscalar processor, peak power, code size
50	Akshay Sharma, Carl Ebeling, Scott Hauck	PipeRoute: a pipelining-aware router for FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF	BFS, PipeRoute, retimed circuits, routing, pipelining, minimum spanning tree, retiming, pipelined circuits
50	William Chow, Jonathan Rose	EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuits.	FPGA	2002	DBLP DOI BibTeX RDF	event horizon, manual placement and pipelining, FPGA, programmable logic
50	Han-Saem Yun, Jihong Kim 0001, Soo-Mook Moon	Optimal software pipelining of loops with control flows.	ICS	2002	DBLP DOI BibTeX RDF	instruction-level parallelism, software pipelining, VLIW
50	Jiang Xu 0001, Wayne H. Wolf	Wave pipelining for application-specific networks-on-chips.	CASES	2002	DBLP DOI BibTeX RDF	system-on-chip (SoC), interconnection, networks-on-chip (NoC), wave pipelining, coupling capacitance
50	Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck	Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	coarse grained logic, code generation, software pipelining, vliw, reconfigurable processor, spatial computation
50	Iffat H. Kazi, David J. Lilja	Coarse-Grained Thread Pipelining: A Speculative Parallel Execution Model for Shared-Memory Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	2001	DBLP DOI BibTeX RDF	Runtime parallelization, thread pipelining, superthreaded architecture, shared-memory multiprocessors, speculative execution, coarse-grained parallelization
50	Elana D. Granston, Eric Stotzer, Joe Zbiciak	Software Pipelining Irregular Loops on the TMS320C6000 VLIW DSP Architecture.	LCTES/OM	2001	DBLP DOI BibTeX RDF	WHILE loops, software pipelining, digital signal processors, VLIW architectures
50	G. Enrique Fernandez, R. Sridhar	Dual rail static CMOS architecture for wave pipelining.	VLSI Design	1996	DBLP DOI BibTeX RDF	dual rail static CMOS architecture, gate capacitance, storage elements, DRSCMOS, multi-functional basic building blocks, combinational logic block, delays, timing, throughput, combinational circuits, power consumption, pipeline processing, CMOS logic circuits, digital systems, capacitance, wave pipelining, delay variations
50	Alexander Aiken, Alexandru Nicolau, Steven Novack	Resource-Constrained Software Pipelining.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF	Software pipelining, instruction scheduling, program optimization, global scheduling, fine-grain parallelism
50	Jian Wang 0046, Andreas Krall, M. Anton Ertl, Christine Eisenbeis	Software pipelining with register allocation and spilling.	MICRO	1994	DBLP DOI BibTeX RDF	instruction-level parallelism, register allocation, software pipelining, loop scheduling, register spilling
50	Barron C. Housel	Pipelining: A Technique for Implementing Data Restructurers.	ACM Trans. Database Syst.	1979	DBLP DOI BibTeX RDF	database conversion, pipelining, deadlock, process scheduling, data translation
50	Xue Yang 0007, Nitin H. Vaidya, Priya Ravichandran	Split-Channel Pipelined Packet Scheduling for Wireless Networks.	IEEE Trans. Mob. Comput.	2006	DBLP DOI BibTeX RDF	bandwidth-independent overhead, bandwidth-dependent overhead, access energy cost, packet access delay, wireless LANs, pipelining, IEEE 802.11, multihop networks, channel utilization, Multiple access control (MAC)
50	Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha	Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications.	ICPP	2002	DBLP DOI BibTeX RDF	Scheduling, Software pipelining, Retiming, DSP processors
48	G. Seetharaman, B. Venkataramani	Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	FPGA, pipelining, SOC, CORDIC, wave-pipelining, DAA
48	SangMin Shim, Soo-Mook Moon	Split-Path Enhanced Pipeline Scheduling.	IEEE Trans. Parallel Distributed Syst.	2003	DBLP DOI BibTeX RDF	multipath loops, enhanced pipeline scheduling, all-path pipelining, Instruction-level parallelism, software pipelining, modulo scheduling
45	Akshay Sharma, Carl Ebeling, Scott Hauck	PipeRoute: a pipelining-aware router for reconfigurable architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
45	Daehong Kim, Dongwan Shin, Kiyoung Choi	Pipelining with common operands for power-efficient linear systems.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
45	Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong	Microarchitecture evaluation with floorplanning and interconnect pipelining.	ASP-DAC	2005	DBLP DOI BibTeX RDF
45	Naohiro Ishii, Hiroaki Ogi, Tsubasa Mochizuki, Kazunori Iwata 0001	Parallelism Improvements of Software Pipelining by Combining Spilling with Rematerialization.	KES (1)	2005	DBLP DOI BibTeX RDF
45	Hongbo Rong, Alban Douillet, Ramaswamy Govindarajan, Guang R. Gao	Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops.	CGO	2004	DBLP DOI BibTeX RDF
45	Haibo Lin, Wenlong Li, Zhizhong Tang	Overcoming Static Register Pressure for Software Pipelining in the Itanium Architecture.	APPT	2003	DBLP DOI BibTeX RDF
45	Han-Saem Yun, Jihong Kim 0001, Soo-Mook Moon	A First Step Towards Time Optimal Software Pipelining of Loops with Control Flows.	CC	2001	DBLP DOI BibTeX RDF
45	H. Safiri, Majid Ahmadi, Graham A. Jullien, William C. Miller	A novel approach based on genetic algorithm for pipelining of recursive filters.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
45	Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith	Timing constraints for high-speed counterflow-clocked pipelining.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
45	Alejandro P. Buchmann, Ming-Chuan Wu	Supporting Group-By and Pipelining in Bitmap-Enabled Query Processors.	SOFSEM	1999	DBLP DOI BibTeX RDF
45	Wayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu	Wave-pipelining: a tutorial and research survey.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
45	Fabian Klass, Michael J. Flynn, Ad J. van de Goor	Fast multiplication in VLSI using wave pipelining techniques.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
45	Rajesh S. Parthasarathy, Ramalingam Sridhar	Double Pass Transistor Logic for High Performance Wave Pipeline Circuits.	VLSI Design	1998	DBLP DOI BibTeX RDF
45	Debabrata Ghosh, S. K. Nandy 0001	Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
43	Reese B. Jones, Vicki H. Allan	Software Pipelining: An Evaluation of Enhanced Pipelining.	MICRO	1991	DBLP DOI BibTeX RDF	software pipelining, instruction scheduling, loop optimization, fine-grain parallelism
43	Hui Liu 0006, Zili Shao, Meng Wang 0005, Junzhao Du, Chun Jason Xue, Zhiping Jia	Combining Coarse-Grained Software Pipelining with DVS for Scheduling Real-Time Periodic Dependent Tasks on Multi-Core Embedded Systems.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Periodic dependent tasks, Scheduling, Multimedia, Real-time, Dynamic voltage scaling (DVS), Multi-core, Software pipelining, Retiming
43	Sebastian Winkel, Rakesh Krishnaiyer, Robyn Sampson	Latency-tolerant software pipelining in a production compiler.	CGO	2008	DBLP DOI BibTeX RDF	latency-tolerant scheduling, load clustering, compiler, code generation, prefetching, software pipelining, modulo scheduling, memory latency, memory-level parallelism, itanium, epic
43	Hyeong Seog Kim, In Soon Cho, Heon Young Yeom	A Task Pipelining Framework for e-Science Workflow Management Systems.	CCGRID	2008	DBLP DOI BibTeX RDF	task pipelining, workflow manager
43	Xue Yang 0007, Nitin H. Vaidya	A Wireless MAC Protocol Using Implicit Pipelining.	IEEE Trans. Mob. Comput.	2006	DBLP DOI BibTeX RDF	access energy cost, packet access delay, wireless LANs, pipelining, IEEE 802.11, multihop networks, channel utilization, Multiple access control (MAC)
43	Mario R. Casu, Luca Macchiarulo	Floorplan assisted data rate enhancement through wire pipelining: a real assessment.	ISPD	2005	DBLP DOI BibTeX RDF	through-put, systems-on-chip, floorplanning, wire pipelining
43	Jason Cong, Yiping Fan, Zhiru Zhang	Architecture-level synthesis for automatic interconnect pipelining.	DAC	2004	DBLP DOI BibTeX RDF	interconnect pipelining, multi-cycle communication, scheduling, high-level synthesis, register binding
43	Cagdas Akturan, Margarida F. Jacome	RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors.	CODES	2001	DBLP DOI BibTeX RDF	embedded systems, software pipelining, retiming, optimizing compilers, VLIW processors
43	Pierre-Yves Calland, Alain Darte, Yves Robert	Circuit Retiming Applied to Decomposed Software Pipelining.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	circuit retiming, Software pipelining, list scheduling, modulo scheduling, cyclic scheduling
43	Tao Yu, Zhizhong Tang, Chihong Zhang, Jun Luo	Control Mechanism for Software Pipelining on Nested Loop.	APDC	1997	DBLP DOI BibTeX RDF	ILSP, software pipelining, VLIW, dataflow, nested loop
43	Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor	A comparative evaluation of software techniques to hide memory latency.	HICSS (1)	1995	DBLP DOI BibTeX RDF	comparative software evaluation, software oriented techniques, superscalar machines, superpipelined machines, software cache prefetching, data fetch request, software controlled prefetching, aggressive prefetching, memory bandwidth requirements, bus traffic, performance, parallel machines, program compilers, processor scheduling, software performance evaluation, software pipelining, pipeline processing, microarchitecture, cache storage, instruction set architecture, memory latency, loop unrolling, static scheduling, conditional branches
40	KyungHi Chang, XuDuan Lin	Ultra-high-speed digital filtering algorithm for video signal processing.	ICIP	1995	DBLP DOI BibTeX RDF	ultra-high-speed digital filtering algorithm, improved minimum-order augmented pipelining, IMAP algorithm, clustered look-ahead technique, augmented pipelining order, undesirable quantization effects, 1-D IMAP digital filter, 2-D structure, bandwidth reduction algorithm, motion estimation, motion estimation, pipeline processing, minimization, minimisation, video signal processing, video signal processing, interference suppression, two-dimensional digital filters, spatio-temporal filtering
40	Siamak Arya, Howard Sachs, Sreeram Duvvuru	An architecture for high instruction level parallelism.	HICSS (1)	1995	DBLP DOI BibTeX RDF	high instruction level parallelism, sequential order, code execution, dataflow problems, condition bits, nonblocking cache, Software Scheduled SuperScalar, parallel programming, compiler, parallel architectures, parallel architecture, pipelining, program compilers, data flow analysis, software pipelining, pipeline processing, data flow, processor architecture, speculative execution, control flow, hardware support, program control structures, branches, registers, functional units, multiple instructions, conditional execution
38	Ching-Wen Chen, Chuan-Chi Weng, Po-Jung Chen	Design of a Low-Power and Low-Latency MAC Protocol with Nodes Grouping and Transmission Pipelining in Wireless Sensor Networks.	VTC Spring	2008	DBLP DOI BibTeX RDF
38	Florent Blachot, Benoît Dupont de Dinechin, Guillaume Huard	SCAN: A Heuristic for Near-Optimal Software Pipelining.	Euro-Par	2006	DBLP DOI BibTeX RDF
38	Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede	Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip.	ASAP	2006	DBLP DOI BibTeX RDF
38	To-Wei Chen, Yu-Wen Huang, Tung-Chien Chen, Yu-Han Chen, Chuan-Yung Tsai, Liang-Gee Chen	Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
38	Xiaoyao Liang, Akshay Athalye, Sangjin Hong	Equalizing data-path for processing speed determination in block level pipelining.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
38	Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao	Single-Dimension Software Pipelining for Multi-Dimensional Loops.	CGO	2004	DBLP DOI BibTeX RDF
38	Jia Di, Jiann-Shiun Yuan, Ronald F. DeMara	High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders.	ISVLSI	2003	DBLP DOI BibTeX RDF
38	Gang-Ryung Uh	Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop Buffer.	SCOPES	2003	DBLP DOI BibTeX RDF
38	Kalyan Muthukumar, Gautam Doshi	Software Pipelining of Nested Loops.	CC	2001	DBLP DOI BibTeX RDF
38	Mikhail Smelyanskiy, Gary S. Tyson, Edward S. Davidson	Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining.	IEEE PACT	2000	DBLP DOI BibTeX RDF
38	Toshinori Sato	A Simulation Study of Pipelining and Decoupling a Dynamic Instruction Scheduling Mechanism.	EUROMICRO	1999	DBLP DOI BibTeX RDF	instruction reissue, instruction window design, instruction level parallelism, data speculation, dynamic instruction scheduling
38	Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses	Some experiments about wave pipelining on FPGA's.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
38	Chihong Zhang, Zhizhong Tang	An Improvement on Data Dependence Analysis Supporting Software Pipelining Technique.	APDC	1997	DBLP DOI BibTeX RDF
38	Jian-Feng Shi, Liang-Fang Chao	Resource-Constrained Algebraic Transformation for Loop Pipelining.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
38	Derek C. Wong, Giovanni De Micheli, Michael J. Flynn	Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
38	Vincent Van Dongen, Guang R. Gao, Qi Ning	A Polynomial Time Method for Optimal Software Pipelining.	CONPAR	1992	DBLP DOI BibTeX RDF
38	Bogong Su, Jian Wang 0046, Zhizhong Tang, Wei Zhao, Yimin Wu	A software pipelining based VLIW architecture and optimizing compiler.	MICRO	1990	DBLP BibTeX RDF
38	Guang R. Gao, Herbert H. J. Hum, Yue-Bong Wong	Towards efficient fine-grain software pipelining.	ICS	1990	DBLP DOI BibTeX RDF
38	Alexander Aiken, Alexandru Nicolau	Perfect Pipelining: A New Loop Parallelization Technique.	ESOP	1988	DBLP DOI BibTeX RDF
38	Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha	Timing Optimization of Nested Loops Considering Code Size for DSP Applications.	ICPP	2004	DBLP DOI BibTeX RDF
35	Jean-Baptiste Tristan, Xavier Leroy	A simple, verified validator for software pipelining.	POPL	2010	DBLP DOI BibTeX RDF	software pipelining, translation validation, verified compilers, symbolic evaluation
35	Ram Rangan, Neil Vachharajani, Guilherme Ottoni, David I. August	Performance scalability of decoupled software pipelining.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	Decoupled software pipelining, performance analysis
35	Sid Ahmed Ali Touati	On the Periodic Register Need in Software Pipelining.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Periodic Register Requirement, MAXLIVE, Periodic Register Sufficiency, Stage Scheduling, Instruction Level Parallelism, Software Pipelining
35	Sevin Fide, Stephen F. Jenks	A middleware approach for pipelining communications in clusters.	Clust. Comput.	2007	DBLP DOI BibTeX RDF	Cluster communications, Middleware, MPI, Pipelining
35	Anuja Jayraj Thakkar, Abdel Ejnioui	Pipelining of double precision floating point division and square root operations.	ACM Southeast Regional Conference	2006	DBLP DOI BibTeX RDF	FPGA, pipelining, floating point, division, square root
35	Noureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini, Yvon Savaria	Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	multiphase, sequential circuit, software pipelining, clock, Retiming
35	Shih-Hao Wang, Wen-Hsiao Peng, Yuwen He, Guan-Yi Lin, Cheng-Yi Lin, Shih-Chien Chang, Chung-Neng Wang, Tihao Chiang	A Software-Hardware Co-Implementation of MPEG-4 Advanced Video Coding (AVC) Decoder with Block Level Pipelining.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	advanced video coding (AVC), joint video team (JVT), software-hardware co-implementation, MB level pipelining, H.264, MPEG-4, task partition
35	Daniel Kästner, Markus Pister 0002	Generic Software Pipelining at the Assembly Level.	SCOPES	2005	DBLP DOI BibTeX RDF	PROPAN, software pipelining, modulo scheduling, postpass optimization
35	François R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Michel Boyer	Optimal design of synchronous circuits using software pipelining techniques.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	software pipelining, retiming, Resynthesis
35	James K. Huggins, David Van Campenhout	Specification and verification of pipelining in the ARM2 RISC microprocessor.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	ARM processor, formal verification, pipelining, abstract state machines, design verification, pipelined processors
35	Soo-Mook Moon, Kemal Ebcioglu	Parallelizing Nonnumerical Code with Selective Scheduling and Software Pipelining.	ACM Trans. Program. Lang. Syst.	1997	DBLP DOI BibTeX RDF	global instruction scheduling, speculative code motion, instruction-level parallelism, software pipelining, VLIW, superscalar
35	Ireneusz Karkowski, Henk Corporaal	Design of Heterogenous Multi-Processor Embedded Systems: Applying Functional Pipelining.	IEEE PACT	1997	DBLP DOI BibTeX RDF	heterogenous multiprocessor embedded system design, functional pipelining, embedded program mapping, ANSI C program, application specific processor pipeline, frequency tracking system, two-processor system, highly optimized single core solution, architecture, multiprocessing systems, instruction level parallelism, speedup, efficient algorithm, loops