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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1997 occurrences of 975 keywords
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Results
Found 1754 publication records. Showing 1754 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
126 | Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou 0001 |
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 920-925, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
graph-based approach, microarchitecture pipelining optimization, throughput-aware floorplanning, block pipelining, interconnect pipelining, graph-based algorithm, mixed integer linear programming, wire pipelining |
126 | Jian Wang, Guang R. Gao |
Pipelining-Dovetailing: A Transformation to Enhance Software Pipelining for Nested Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 6th International Conference, CC'96, Linköping, Sweden, April 24-26, 1996, Proceedings, pp. 1-17, 1996, Springer, 3-540-61053-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Very Long Instruction Word(VLIW), Instruction-Level Parallelism, Software Pipelining, Superscalar, Nested Loop, Loop Scheduling, Fine-Grain Parallelism |
106 | Monica S. Lam |
Software pipelining: an effective scheduling technique for VLIW machines (with retrospective) ![Search on Bibsonomy](Pics/bibsonomy.png) |
Best of PLDI ![In: 20 Years of the ACM SIGPLAN Conference on Programming Language Design and Implementation 1979-1999, A Selection, pp. 244-256, 1988, ACM, 1-58113-623-4. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
103 | João M. P. Cardoso |
Dynamic loop pipelining in data-driven architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005, pp. 106-115, 2005, ACM, 1-59593-019-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
compilation, reconfigurable computing, software pipelining, dataflow, data-driven architectures |
88 | Reese B. Jones, Vicki H. Allan |
Software pipelining: a comparison and improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990, Orlando, Florida, USA, November 27-29, 1990, pp. 46-56, 1990, ACM/IEEE, 0-89791-413-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP BibTeX RDF |
recognition of parallelism, software pipelining, operation scheduling |
76 | Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin |
Design tradeoffs in high speed multipliers and FIR filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 29-32, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
high speed multipliers, high speed FIR filters, modified Booth recoding, pipeline granularity, transistor count, activity factor reduction, guarded evaluation, gate-level pipelining, half-bit level pipelining, bit-level pipelining, delay, clocking, digital filters, FIR filters, multiplying circuits, power dissipation, design tradeoffs, pipeline arithmetic, operation speed |
76 | Miodrag Potkonjak, Jan M. Rabaey |
Optimizing throughput and resource utilization using pipelining: Transformation based approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 8(2), pp. 117-130, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
73 | Han-Saem Yun, Jihong Kim 0001, Soo-Mook Moon |
Time Optimal Software Pipelining of Loops with Control Flows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 31(5), pp. 339-391, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
compiler optimization, instruction-level parallelism, software pipelining, VLIW |
68 | Mark G. Stoodley, Corinna G. Lee |
Software Pipelining Loops with Conditional Branches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 262-273, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
66 | Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao |
Single-dimension software pipelining for multidimensional loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 4(1), pp. 7, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Software pipelining, loop transformation, modulo scheduling |
66 | Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews |
High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 91-107, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
counterflow-clocked pipelining, HDTV subband vector quantizer chips, clock skew problems, back-propagating clock signals, high speed clocks, dynamic latches, composition rules, two-dimensional data-flow, image compression chip set, subband VQ, VLSI, timing, image coding, pipeline processing, digital signal processing chips, vector quantisation, telecommunication computing, clock distribution, VLSI chips, high definition television |
63 | Smita Bakshi, Daniel Gajski |
Performance-constrained hierarchical pipelining for behaviors, loops, and operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(1), pp. 1-25, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
DSP (digital signal processing) systems, hierarchical pipelining, pipelined systems, scheduling, component selection, loop pipelining |
60 | Kieron Turkington, Turkington A. Constantinides, Kostas Masselos, Peter Y. K. Cheung |
Outer Loop Pipelining for Application Specific Datapaths in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(10), pp. 1268-1280, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
60 | Pallav Gupta, Niraj K. Jha |
An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 974-979, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
60 | Bogong Su, Jian Wang 0046, Erh-Wen Hu, Joseph B. Manzano |
Software De-Pipelining Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCAM ![In: 4th IEEE International Workshop on Source Code Analysis and Manipulation (SCAM 2004), 15-16 September 2004, Chicago, IL, USA, pp. 7-16, 2004, IEEE Computer Society, 0-7695-2144-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
58 | Haitao Wei, Junqing Yu, Huafei Yu, Guang R. Gao |
Minimizing communication in rate-optimal software pipelining for stream programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Proceedings of the CGO 2010, The 8th International Symposium on Code Generation and Optimization, Toronto, Ontario, Canada, April 24-28, 2010, pp. 210-217, 2010, ACM, 978-1-60558-635-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
dfbrook, multi-core, software pipelining, cell processor, stream programs |
58 | Won So, Alexander G. Dean |
Complementing software pipelining with software thread integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'05), Chicago, Illinois, USA, June 15-17, 2005, pp. 137-146, 2005, ACM, 1-59593-018-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
TI C6000, DSP, software pipelining, VLIW, stream programming, coarse-grain parallelism, software thread integration |
56 | Dragan Milicev, Zoran Jovanovic |
A Formal Model of Software Pipelining Loops with Conditions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: 11th International Parallel Processing Symposium (IPPS '97), 1-5 April 1997, Geneva, Switzerland, Proceedings, pp. 554-558, 1997, IEEE Computer Society, 0-8186-7792-9. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
software pipelining loops, PSP model, parallel programming, finite state machine, formal model, software pipelining, parallelizing loops, conditional branches |
53 | Mohammed Fellahi, Albert Cohen 0001 |
Software Pipelining in Nested Loops with Prolog-Epilog Merging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings, pp. 80-94, 2009, Springer, 978-3-540-92989-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
53 | Lingfang Zeng, Dan Feng 0001, Fang Wang 0001 |
Pipelining Network Storage I/O. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science (1) ![In: Computational Science - ICCS 2006, 6th International Conference, Reading, UK, May 28-31, 2006, Proceedings, Part I, pp. 1063-1066, 2006, Springer, 3-540-34379-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
53 | Guy E. Blelloch, Margaret Reid-Miller |
Pipelining with Futures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Theory Comput. Syst. ![In: Theory Comput. Syst. 32(3), pp. 213-239, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
53 | Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah |
Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12), pp. 1526-1545, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
53 | Monica Lam 0001 |
Software Pipelining: An Effective Scheduling Technique for VLIW Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'88 Conference on Programming Language Design and Implementation (PLDI), Atlanta, Georgia, USA, June 22-24, 1988, pp. 318-328, 1988, ACM, 0-89791-269-1. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
50 | Takuya Miyamaru, Hiroshi Mineno, Yoshiaki Terashima, Yuichi Tokunaga, Tadanori Mizuno |
State-Based Pipelining for Reprogramming Wireless Sensor Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (3) ![In: Knowledge-Based Intelligent Information and Engineering Systems, 11th International Conference, KES 2007, XVII Italian Workshop on Neural Networks, Vietri sul Mare, Italy, September 12-14, 2007, Proceedings, Part III, pp. 531-538, 2007, Springer, 978-3-540-74828-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Wireless sensor network, Pipelining, Reprogramming |
50 | Yuan-man Tong, Zhiying Wang 0003, Kui Dai, Hongyi Lu |
Designing Power Analysis Resistant and High Performance Block Cipher Coprocessor Using WDDL and Wave-Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inscrypt ![In: Information Security and Cryptology, Second SKLOIS Conference, Inscrypt 2006, Beijing, China, November 29 - December 1, 2006, Proceedings, pp. 66-77, 2006, Springer, 3-540-49608-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
WDDL, power analysis resistant, block cipher, design flow, Wave-pipelining |
50 | Noureddine Chabini, Wayne H. Wolf |
An approach for integrating basic retiming and software pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: EMSOFT 2004, September 27-29, 2004, Pisa, Italy, Fourth ACM International Conference On Embedded Software, Proceedings, pp. 287-296, 2004, ACM, 1-58113-860-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
embedded systems, system-on-chip, timings, instruction-level parallelism, software pipelining, VLIW, retiming, superscalar processor, peak power, code size |
50 | Akshay Sharma, Carl Ebeling, Scott Hauck |
PipeRoute: a pipelining-aware router for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 68-77, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
BFS, PipeRoute, retimed circuits, routing, pipelining, minimum spanning tree, retiming, pipelined circuits |
50 | William Chow, Jonathan Rose |
EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2002, Monterey, CA, USA, February 24-26, 2002, pp. 85-94, 2002, ACM, 1-58113-452-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
event horizon, manual placement and pipelining, FPGA, programmable logic |
50 | Han-Saem Yun, Jihong Kim 0001, Soo-Mook Moon |
Optimal software pipelining of loops with control flows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 16th international conference on Supercomputing, ICS 2002, New York City, NY, USA, June 22-26, 2002, pp. 117-128, 2002, ACM, 1-58113-483-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
instruction-level parallelism, software pipelining, VLIW |
50 | Jiang Xu 0001, Wayne H. Wolf |
Wave pipelining for application-specific networks-on-chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 198-201, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
system-on-chip (SoC), interconnection, networks-on-chip (NoC), wave pipelining, coupling capacitance |
50 | Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck |
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 338-344, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
coarse grained logic, code generation, software pipelining, vliw, reconfigurable processor, spatial computation |
50 | Iffat H. Kazi, David J. Lilja |
Coarse-Grained Thread Pipelining: A Speculative Parallel Execution Model for Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 12(9), pp. 952-966, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Runtime parallelization, thread pipelining, superthreaded architecture, shared-memory multiprocessors, speculative execution, coarse-grained parallelization |
50 | Elana D. Granston, Eric Stotzer, Joe Zbiciak |
Software Pipelining Irregular Loops on the TMS320C6000 VLIW DSP Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES/OM ![In: Proceedings of The Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES 2001), June 22-23, 2001 / The Workshop on Optimization of Middleware and Distributed Systems (OM 2001), June 18, 2001, Snowbird, Utah, USA, pp. 138-144, 2001, ACM, 1-58113-425-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
WHILE loops, software pipelining, digital signal processors, VLIW architectures |
50 | G. Enrique Fernandez, R. Sridhar |
Dual rail static CMOS architecture for wave pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 335-336, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
dual rail static CMOS architecture, gate capacitance, storage elements, DRSCMOS, multi-functional basic building blocks, combinational logic block, delays, timing, throughput, combinational circuits, power consumption, pipeline processing, CMOS logic circuits, digital systems, capacitance, wave pipelining, delay variations |
50 | Alexander Aiken, Alexandru Nicolau, Steven Novack |
Resource-Constrained Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 6(12), pp. 1248-1270, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Software pipelining, instruction scheduling, program optimization, global scheduling, fine-grain parallelism |
50 | Jian Wang 0046, Andreas Krall, M. Anton Ertl, Christine Eisenbeis |
Software pipelining with register allocation and spilling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 95-99, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
instruction-level parallelism, register allocation, software pipelining, loop scheduling, register spilling |
50 | Barron C. Housel |
Pipelining: A Technique for Implementing Data Restructurers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Database Syst. ![In: ACM Trans. Database Syst. 4(4), pp. 470-492, 1979. The full citation details ...](Pics/full.jpeg) |
1979 |
DBLP DOI BibTeX RDF |
database conversion, pipelining, deadlock, process scheduling, data translation |
50 | Xue Yang 0007, Nitin H. Vaidya, Priya Ravichandran |
Split-Channel Pipelined Packet Scheduling for Wireless Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Mob. Comput. ![In: IEEE Trans. Mob. Comput. 5(3), pp. 240-257, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
bandwidth-independent overhead, bandwidth-dependent overhead, access energy cost, packet access delay, wireless LANs, pipelining, IEEE 802.11, multihop networks, channel utilization, Multiple access control (MAC) |
50 | Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha |
Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 31st International Conference on Parallel Processing (ICPP 2002), 20-23 August 2002, Vancouver, BC, Canada, pp. 613-620, 2002, IEEE Computer Society, 0-7695-1677-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Scheduling, Software pipelining, Retiming, DSP processors |
48 | G. Seetharaman, B. Venkataramani |
Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 2(2), pp. 11:1-11:19, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA, pipelining, SOC, CORDIC, wave-pipelining, DAA |
48 | SangMin Shim, Soo-Mook Moon |
Split-Path Enhanced Pipeline Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 14(5), pp. 447-462, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
multipath loops, enhanced pipeline scheduling, all-path pipelining, Instruction-level parallelism, software pipelining, modulo scheduling |
45 | Akshay Sharma, Carl Ebeling, Scott Hauck |
PipeRoute: a pipelining-aware router for reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3), pp. 518-532, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
45 | Daehong Kim, Dongwan Shin, Kiyoung Choi |
Pipelining with common operands for power-efficient linear systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(9), pp. 1023-1034, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
45 | Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong |
Microarchitecture evaluation with floorplanning and interconnect pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 8-15, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
45 | Naohiro Ishii, Hiroaki Ogi, Tsubasa Mochizuki, Kazunori Iwata 0001 |
Parallelism Improvements of Software Pipelining by Combining Spilling with Rematerialization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (1) ![In: Knowledge-Based Intelligent Information and Engineering Systems, 9th International Conference, KES 2005, Melbourne, Australia, September 14-16, 2005, Proceedings, Part I, pp. 820-826, 2005, Springer, 3-540-28894-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
45 | Hongbo Rong, Alban Douillet, Ramaswamy Govindarajan, Guang R. Gao |
Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 20-24 March 2004, San Jose, CA, USA, pp. 175-188, 2004, IEEE Computer Society, 0-7695-2102-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
45 | Haibo Lin, Wenlong Li, Zhizhong Tang |
Overcoming Static Register Pressure for Software Pipelining in the Itanium Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Programming Technologies, 5th International Workshop, APPT 2003, Xiamen, China, September 17-19, 2003, Proceedings, pp. 109-113, 2003, Springer, 3-540-20054-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
45 | Han-Saem Yun, Jihong Kim 0001, Soo-Mook Moon |
A First Step Towards Time Optimal Software Pipelining of Loops with Control Flows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 10th International Conference, CC 2001 Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2001 Genova, Italy, April 2-6, 2001, Proceedings, pp. 182-199, 2001, Springer, 3-540-41861-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
45 | H. Safiri, Majid Ahmadi, Graham A. Jullien, William C. Miller |
A novel approach based on genetic algorithm for pipelining of recursive filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 633-636, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
45 | Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith |
Timing constraints for high-speed counterflow-clocked pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(2), pp. 167-173, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
45 | Alejandro P. Buchmann, Ming-Chuan Wu |
Supporting Group-By and Pipelining in Bitmap-Enabled Query Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SOFSEM ![In: SOFSEM '99, Theory and Practice of Informatics, 26th Conference on Current Trends in Theory and Practice of Informatics, Milovy, Czech Republic, November 27 - December 4, 1999, Proceedings, pp. 249-260, 1999, Springer, 3-540-66694-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
45 | Wayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu |
Wave-pipelining: a tutorial and research survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(3), pp. 464-474, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
45 | Fabian Klass, Michael J. Flynn, Ad J. van de Goor |
Fast multiplication in VLSI using wave pipelining techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 7(3), pp. 233-248, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
45 | Rajesh S. Parthasarathy, Ramalingam Sridhar |
Double Pass Transistor Logic for High Performance Wave Pipeline Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 495-500, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
45 | Debabrata Ghosh, S. K. Nandy 0001 |
Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(1), pp. 36-48, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
43 | Reese B. Jones, Vicki H. Allan |
Software Pipelining: An Evaluation of Enhanced Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 24, Albuquerque, New Mexico, USA, November 18-20, 1991, pp. 82-92, 1991, ACM/IEEE, 0-89791-460-0. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
software pipelining, instruction scheduling, loop optimization, fine-grain parallelism |
43 | Hui Liu 0006, Zili Shao, Meng Wang 0005, Junzhao Du, Chun Jason Xue, Zhiping Jia |
Combining Coarse-Grained Software Pipelining with DVS for Scheduling Real-Time Periodic Dependent Tasks on Multi-Core Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 57(2), pp. 249-262, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Periodic dependent tasks, Scheduling, Multimedia, Real-time, Dynamic voltage scaling (DVS), Multi-core, Software pipelining, Retiming |
43 | Sebastian Winkel, Rakesh Krishnaiyer, Robyn Sampson |
Latency-tolerant software pipelining in a production compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Sixth International Symposium on Code Generation and Optimization (CGO 2008), April 5-9, 2008, Boston, MA, USA, pp. 104-113, 2008, ACM, 978-1-59593-978-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
latency-tolerant scheduling, load clustering, compiler, code generation, prefetching, software pipelining, modulo scheduling, memory latency, memory-level parallelism, itanium, epic |
43 | Hyeong Seog Kim, In Soon Cho, Heon Young Yeom |
A Task Pipelining Framework for e-Science Workflow Management Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCGRID ![In: 8th IEEE International Symposium on Cluster Computing and the Grid (CCGrid 2008), 19-22 May 2008, Lyon, France, pp. 657-662, 2008, IEEE Computer Society, 978-0-7695-3156-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
task pipelining, workflow manager |
43 | Xue Yang 0007, Nitin H. Vaidya |
A Wireless MAC Protocol Using Implicit Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Mob. Comput. ![In: IEEE Trans. Mob. Comput. 5(3), pp. 258-273, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
access energy cost, packet access delay, wireless LANs, pipelining, IEEE 802.11, multihop networks, channel utilization, Multiple access control (MAC) |
43 | Mario R. Casu, Luca Macchiarulo |
Floorplan assisted data rate enhancement through wire pipelining: a real assessment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 121-128, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
through-put, systems-on-chip, floorplanning, wire pipelining |
43 | Jason Cong, Yiping Fan, Zhiru Zhang |
Architecture-level synthesis for automatic interconnect pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 602-607, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect pipelining, multi-cycle communication, scheduling, high-level synthesis, register binding |
43 | Cagdas Akturan, Margarida F. Jacome |
RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Ninth International Symposium on Hardware/Software Codesign, CODES 2001, Copenhagen, Denmark, 2001, pp. 67-72, 2001, ACM, 1-58113-364-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
embedded systems, software pipelining, retiming, optimizing compilers, VLIW processors |
43 | Pierre-Yves Calland, Alain Darte, Yves Robert |
Circuit Retiming Applied to Decomposed Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 9(1), pp. 24-35, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
circuit retiming, Software pipelining, list scheduling, modulo scheduling, cyclic scheduling |
43 | Tao Yu, Zhizhong Tang, Chihong Zhang, Jun Luo |
Control Mechanism for Software Pipelining on Nested Loop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APDC ![In: Proceedings of the 1997 Advances in Parallel and Distributed Computing Conference (APDC '97), March 19-21, 1997, Shanghai, China, pp. 345-350, 1997, IEEE Computer Society, 0-8186-7876-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
ILSP, software pipelining, VLIW, dataflow, nested loop |
43 | Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor |
A comparative evaluation of software techniques to hide memory latency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 229-241, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
comparative software evaluation, software oriented techniques, superscalar machines, superpipelined machines, software cache prefetching, data fetch request, software controlled prefetching, aggressive prefetching, memory bandwidth requirements, bus traffic, performance, parallel machines, program compilers, processor scheduling, software performance evaluation, software pipelining, pipeline processing, microarchitecture, cache storage, instruction set architecture, memory latency, loop unrolling, static scheduling, conditional branches |
40 | KyungHi Chang, XuDuan Lin |
Ultra-high-speed digital filtering algorithm for video signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP ![In: Proceedings 1995 International Conference on Image Processing, Washington, DC, USA, October 23-26, 1995, pp. 121-124, 1995, IEEE Computer Society, 0-8186-7310-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
ultra-high-speed digital filtering algorithm, improved minimum-order augmented pipelining, IMAP algorithm, clustered look-ahead technique, augmented pipelining order, undesirable quantization effects, 1-D IMAP digital filter, 2-D structure, bandwidth reduction algorithm, motion estimation, motion estimation, pipeline processing, minimization, minimisation, video signal processing, video signal processing, interference suppression, two-dimensional digital filters, spatio-temporal filtering |
40 | Siamak Arya, Howard Sachs, Sreeram Duvvuru |
An architecture for high instruction level parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 153-162, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high instruction level parallelism, sequential order, code execution, dataflow problems, condition bits, nonblocking cache, Software Scheduled SuperScalar, parallel programming, compiler, parallel architectures, parallel architecture, pipelining, program compilers, data flow analysis, software pipelining, pipeline processing, data flow, processor architecture, speculative execution, control flow, hardware support, program control structures, branches, registers, functional units, multiple instructions, conditional execution |
38 | Ching-Wen Chen, Chuan-Chi Weng, Po-Jung Chen |
Design of a Low-Power and Low-Latency MAC Protocol with Nodes Grouping and Transmission Pipelining in Wireless Sensor Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Spring ![In: Proceedings of the 67th IEEE Vehicular Technology Conference, VTC Spring 2008, 11-14 May 2008, Singapore, pp. 143-147, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Florent Blachot, Benoît Dupont de Dinechin, Guillaume Huard |
SCAN: A Heuristic for Near-Optimal Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28 - September 1, 2006, Proceedings, pp. 289-298, 2006, Springer, 3-540-37783-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede |
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 2006 IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP 2006), 11-13 September 2006, Steamboat Springs, Colorado, USA, pp. 15-18, 2006, IEEE Computer Society, 0-7695-2682-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | To-Wei Chen, Yu-Wen Huang, Tung-Chien Chen, Yu-Han Chen, Chuan-Yung Tsai, Liang-Gee Chen |
Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2931-2934, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Xiaoyao Liang, Akshay Athalye, Sangjin Hong |
Equalizing data-path for processing speed determination in block level pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1646-1649, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao |
Single-Dimension Software Pipelining for Multi-Dimensional Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 20-24 March 2004, San Jose, CA, USA, pp. 163-174, 2004, IEEE Computer Society, 0-7695-2102-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
38 | Jia Di, Jiann-Shiun Yuan, Ronald F. DeMara |
High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 260-261, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
38 | Gang-Ryung Uh |
Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop Buffer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCOPES ![In: Software and Compilers for Embedded Systems, 7th International Workshop, SCOPES 2003, Vienna, Austria, September 24-26, 2003, Proceedings, pp. 133-150, 2003, Springer, 3-540-20145-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
38 | Kalyan Muthukumar, Gautam Doshi |
Software Pipelining of Nested Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 10th International Conference, CC 2001 Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2001 Genova, Italy, April 2-6, 2001, Proceedings, pp. 165-181, 2001, Springer, 3-540-41861-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
38 | Mikhail Smelyanskiy, Gary S. Tyson, Edward S. Davidson |
Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), Philadelphia, Pennsylvania, USA, October 15-19, 2000, pp. 3-12, 2000, IEEE Computer Society, 0-7695-0622-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
38 | Toshinori Sato |
A Simulation Study of Pipelining and Decoupling a Dynamic Instruction Scheduling Mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1178-1185, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
instruction reissue, instruction window design, instruction level parallelism, data speculation, dynamic instruction scheduling |
38 | Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses |
Some experiments about wave pipelining on FPGA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(2), pp. 232-237, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
38 | Chihong Zhang, Zhizhong Tang |
An Improvement on Data Dependence Analysis Supporting Software Pipelining Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APDC ![In: Proceedings of the 1997 Advances in Parallel and Distributed Computing Conference (APDC '97), March 19-21, 1997, Shanghai, China, pp. 378-382, 1997, IEEE Computer Society, 0-8186-7876-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
38 | Jian-Feng Shi, Liang-Fang Chao |
Resource-Constrained Algebraic Transformation for Loop Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), March 22-23, 1996, Ames, IA, USA, pp. 14-17, 1996, IEEE Computer Society, 0-8186-7502-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
38 | Derek C. Wong, Giovanni De Micheli, Michael J. Flynn |
Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(1), pp. 25-46, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
38 | Vincent Van Dongen, Guang R. Gao, Qi Ning |
A Polynomial Time Method for Optimal Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: Parallel Processing: CONPAR 92 - VAPP V, Second Joint International Conference on Vector and Parallel Processing, Lyon, France, September 1-4, 1992, Proceedings, pp. 613-624, 1992, Springer, 3-540-55895-0. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
38 | Bogong Su, Jian Wang 0046, Zhizhong Tang, Wei Zhao, Yimin Wu |
A software pipelining based VLIW architecture and optimizing compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990, Orlando, Florida, USA, November 27-29, 1990, pp. 17-27, 1990, ACM/IEEE, 0-89791-413-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP BibTeX RDF |
|
38 | Guang R. Gao, Herbert H. J. Hum, Yue-Bong Wong |
Towards efficient fine-grain software pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 4th international conference on Supercomputing, ICS 1990, Amsterdam, The Netherlands, June 11-15, 1990, pp. 369-379, 1990, ACM, 0-89791-369-8. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
38 | Alexander Aiken, Alexandru Nicolau |
Perfect Pipelining: A New Loop Parallelization Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESOP ![In: ESOP '88, 2nd European Symposium on Programming, Nancy, France, March 21-24, 1988, Proceedings, pp. 221-235, 1988, Springer, 3-540-19027-9. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
38 | Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha |
Timing Optimization of Nested Loops Considering Code Size for DSP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 33rd International Conference on Parallel Processing (ICPP 2004), 15-18 August 2004, Montreal, Quebec, Canada, pp. 475-482, 2004, IEEE Computer Society, 0-7695-2197-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
35 | Jean-Baptiste Tristan, Xavier Leroy |
A simple, verified validator for software pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
POPL ![In: Proceedings of the 37th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL 2010, Madrid, Spain, January 17-23, 2010, pp. 83-92, 2010, ACM, 978-1-60558-479-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
software pipelining, translation validation, verified compilers, symbolic evaluation |
35 | Ram Rangan, Neil Vachharajani, Guilherme Ottoni, David I. August |
Performance scalability of decoupled software pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 5(2), pp. 8:1-8:25, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Decoupled software pipelining, performance analysis |
35 | Sid Ahmed Ali Touati |
On the Periodic Register Need in Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(11), pp. 1493-1504, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Periodic Register Requirement, MAXLIVE, Periodic Register Sufficiency, Stage Scheduling, Instruction Level Parallelism, Software Pipelining |
35 | Sevin Fide, Stephen F. Jenks |
A middleware approach for pipelining communications in clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Clust. Comput. ![In: Clust. Comput. 10(4), pp. 409-424, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Cluster communications, Middleware, MPI, Pipelining |
35 | Anuja Jayraj Thakkar, Abdel Ejnioui |
Pipelining of double precision floating point division and square root operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Southeast Regional Conference ![In: Proceedings of the 44st Annual Southeast Regional Conference, 2006, Melbourne, Florida, USA, March 10-12, 2006, pp. 488-493, 2006, ACM, 1-59593-315-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FPGA, pipelining, floating point, division, square root |
35 | Noureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini, Yvon Savaria |
Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(2), pp. 187-204, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
multiphase, sequential circuit, software pipelining, clock, Retiming |
35 | Shih-Hao Wang, Wen-Hsiao Peng, Yuwen He, Guan-Yi Lin, Cheng-Yi Lin, Shih-Chien Chang, Chung-Neng Wang, Tihao Chiang |
A Software-Hardware Co-Implementation of MPEG-4 Advanced Video Coding (AVC) Decoder with Block Level Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 41(1), pp. 93-110, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
advanced video coding (AVC), joint video team (JVT), software-hardware co-implementation, MB level pipelining, H.264, MPEG-4, task partition |
35 | Daniel Kästner, Markus Pister 0002 |
Generic Software Pipelining at the Assembly Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCOPES ![In: Proceedings of the 9th International Workshop on Software and Compilers for Embedded Systems, Dallas, Texas, USA, September 29 - October 1, 2005, pp. 50-61, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
PROPAN, software pipelining, modulo scheduling, postpass optimization |
35 | François R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Michel Boyer |
Optimal design of synchronous circuits using software pipelining techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(4), pp. 516-532, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
software pipelining, retiming, Resynthesis |
35 | James K. Huggins, David Van Campenhout |
Specification and verification of pipelining in the ARM2 RISC microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 3(4), pp. 563-580, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
ARM processor, formal verification, pipelining, abstract state machines, design verification, pipelined processors |
35 | Soo-Mook Moon, Kemal Ebcioglu |
Parallelizing Nonnumerical Code with Selective Scheduling and Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 19(6), pp. 853-898, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
global instruction scheduling, speculative code motion, instruction-level parallelism, software pipelining, VLIW, superscalar |
35 | Ireneusz Karkowski, Henk Corporaal |
Design of Heterogenous Multi-Processor Embedded Systems: Applying Functional Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), San Francisco, CA, USA, October 11-15, 1997, pp. 156-165, 1997, IEEE Computer Society, 0-8186-8090-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
heterogenous multiprocessor embedded system design, functional pipelining, embedded program mapping, ANSI C program, application specific processor pipeline, frequency tracking system, two-processor system, highly optimized single core solution, architecture, multiprocessing systems, instruction level parallelism, speedup, efficient algorithm, loops |
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