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Publication years (Num. hits)
1993-1994 (32) 1995 (25) 1996 (21) 1997 (25) 1998 (20) 1999 (23) 2000 (23) 2001-2002 (30) 2003-2004 (34) 2005 (26) 2006 (26) 2007 (31) 2008 (30) 2009-2011 (15) 2012-2018 (6)
Publication types (Num. hits)
article(97) book(1) incollection(2) inproceedings(267)
Venues (Conferences, Journals, ...)
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The graphs summarize 375 occurrences of 273 keywords

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Found 367 publication records. Showing 367 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
134Farooq Butt Porting the mcc PowerPC C/C++ Compiler into an Interactive Development Environment. Search on Bibsonomy ACM SIGPLAN Notices The full citation details ... 1996 DBLP  DOI  BibTeX  RDF C++
101Charles D. Norton The International Workshop on Parallel C++ (IWPC++), Kanazawa, Ishikawa Prefecture, Japan. Search on Bibsonomy ACM SIGPLAN Notices The full citation details ... 1996 DBLP  DOI  BibTeX  RDF C++
85Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden Design and Analysis of Power Distribution Networks in PowerPC Microprocessors. Search on Bibsonomy DAC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF reliability, PowerPC, PowerPC, IR-drop, power distribution network
85Michael S. Allen, W. Kurt Lewchuk, J. D. Coddington A high performance bus and cache controller for PowerPC multiprocessing systems. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF high performance bus, cache controller, PowerPC 620 microprocessor, system bus interface, ECC protected, server-class systems, physical address bus, data bus, address transfer rates, address snoop response, direct cache-to-cache data transfers, 2 GByte/s, 133 MHz, 128 MB, performance evaluation, pipelining, multiprocessing systems, multiprocessing systems, pipeline processing, cache storage, microprocessor chips, coprocessors, cache coherency protocol, data transfer, PowerPC, system buses, co-processor
79Brian F. Veale, John K. Antonio, Monte P. Tull, Sean A. Jones Selection of instruction set extensions for an FPGA embedded processor core. Search on Bibsonomy IPDPS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
76Charles P. Roth, Frank E. Levine, Edward H. Welbon Performance monitoring on the PowerPC 604 microprocessor. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF PowerPC 604 microprocessor, multichip processors, Groupe Bull, performance evaluation, integrated circuit testing, workstations, performance monitoring, microprocessor chips, PCs, Microsoft, IBM, computer testing, Apple, Motorola
76Carlos Montemayor, Marie Sullivan, Jen-Tien Yen, Pete Wilson, Richard Evers, K. R. Kishore The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF PowerPC 603e microprocessor, low-power superscalar microprocessor, portable products, on-chip instruction, cache associativity, bus modes, 120 SPECint92, 105 SPECfp92, die size, software controllable power-down modes, power saving capability, 16 Kbyte, performance evaluation, performance, computer architecture, system design, power consumption, data cache, cache storage, microprocessor chips, frequency, system buses, portable computers, portable computers, transistors, 100 MHz
76Trung A. Diep, Christopher Nelson, John Paul Shen Performance Evaluation of the PowerPC 620 Microarchitecture. Search on Bibsonomy ISCA The full citation details ... 1995 DBLP  DOI  BibTeX  RDF PowerPC
68Harold W. Cain, Kevin M. Lepak, Mikko H. Lipasti A dynamic binary translation approach to architectural simulation. Search on Bibsonomy SIGARCH Comput. Archit. News The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
65Peter M. Behr, S. Pletner, Angela C. Sodan PowerMANNA: A Parallel Architecture Based on the PowerPC MPC620. Search on Bibsonomy HPCA The full citation details ... 2000 DBLP  DOI  BibTeX  RDF PowerPC MPC620, two-way nodes, crossbar interconnection network, distributed memory architecture
65Farooq Butt Rapid Development of a Source-Level Debugger for PowerPC Microprocessors. Search on Bibsonomy ACM SIGPLAN Notices The full citation details ... 1994 DBLP  DOI  BibTeX  RDF PowerPC
55Mahdi Fazeli, Reza Farivar 0003, Seyed Ghassem Miremadi Error Detection Enhancement in PowerPC Architecture-based Embedded Processors. Search on Bibsonomy J. Electron. Test. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Physical fault injection, Power supply disturbances, Concurrent error detection, Control flow checking
55Mahdi Fazeli, Reza Farivar 0003, Seyed Ghassem Miremadi A Software-Based Concurrent Error Detection Technique for PowerPC Processor-based Embedded Systems. Search on Bibsonomy DFT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
55Patrick J. Bohrer, James L. Peterson, E. N. Elnozahy, Ramakrishnan Rajamony, Ahmed Gheith, Ronald L. Rockhold, Charles Lefurgy, Hazim Shafi, Tarun Nakra, Richard O. Simpson, Evan Speight, Kartik Sudeep, Eric Van Hensbergen, Lixin Zhang 0002 Mambo: a full system simulator for the PowerPC architecture. Search on Bibsonomy SIGMETRICS Perform. Evaluation Rev. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
53Allon Adir, Hagit Attiya, Gil Shurek Information-Flow Models for Shared Memory with an Application to the PowerPC Architecture. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF PowerPC architecture, synchronization instructions, models, specification, consistency, Shared memory, multiprocessor systems, out-of-order execution
53Shantanu Ganguly, Shervin Hojat Clock distribution design and verification for PowerPC microprocessors. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF PowerPC
53Julie Shipnes, Mike Philip A Modular Approach to Motorola PowerPC Compilers. Search on Bibsonomy Commun. ACM The full citation details ... 1994 DBLP  DOI  BibTeX  RDF PowerPC
44Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. Search on Bibsonomy VTS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Microprocessor, Delay Testing
44Martin S. Schmookler, Michael Putrino, Anh Mather, Jon Tyler, Huy Van Nguyen, Charles Roth, Mukesh Sharma, Mydung N. Pham, Jeff Lent A Low-Power, High-Speed Implementation of a PowerPC(tm) Microprocessor Vector Extension. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
44Mario Porrmann, Ulrich Rückert 0001, Karl Michael Marks, Jörg Landmann HiBRIC-MEM, a Memory Controller for PowerPC Based Systems. Search on Bibsonomy EUROMICRO The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
43M. Armstead, Michael Cogswell, S. Halverson, T. Musta PowerPC Visual Simulator: Peeking Under the Hood of the PowerPC Engine. Search on Bibsonomy ICCD The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
42Li-C. Wang, Magdy S. Abadir, Nari Krishnamurthy Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation. Search on Bibsonomy DAC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF PowerPC
42Anthony Correale Jr. Overview of the power minimization techniques employed in the IBM PowerPC 4xx embedded controllers. Search on Bibsonomy ISLPD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF PowerPC
34Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis The Molen compiler for reconfigurable processors. Search on Bibsonomy ACM Trans. Embed. Comput. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF FPGA, reconfigurable computing, Instruction scheduling
34Pedro Trancoso Dynamic Split: Flexible Border Between Instruction and Data Cache. Search on Bibsonomy DSD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Valentina Salapura, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, Dong Chen 0005, Paul Coteus, Alan Gara, Mark Giampapa, Michael Gschwind, Manish Gupta 0002, Shawn Hall, Ruud A. Haring, Philip Heidelberger, Dirk Hoenicke, Gerard V. Kopcsay, Martin Ohmacht, Rick A. Rand, Todd Takken, Pavlos Vranas Power and performance optimization at the system level. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF BlueGene/L, application performance analysis, application scaling in multiprocessor systems, power/performance efficient systems, power/performance tradeos in systems, chip multiprocessors, supercomputers
34Amir Hekmatpour, James Coulter Coverage-Directed Management and Optimization of Random Functional Verification. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
34Gordon J. Brebner Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro. Search on Bibsonomy FCCM The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
34Pedro Furtado 0001, Henrique Madeira Fault Injection Evaluation of Assigned Signatures in a RISC Processor. Search on Bibsonomy EDCC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
34Bryan Black, Andrew S. Huang, Mikko H. Lipasti, John Paul Shen Can Trace-Driven Simulators Accurately Predict Superscalar Performance? Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
33Magnus O. Myreen, Michael J. C. Gordon Verified LISP Implementations on ARM, x86 and PowerPC. Search on Bibsonomy TPHOLs The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
33Joon Huang Chuah, Joel Knight VertiCal, a Universal Calibration System for eSys High Performance 32-Bit PowerPC Microcontrollers; Test Challenges & Solution. Search on Bibsonomy DELTA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Jayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors. Search on Bibsonomy MTV The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
33Weining Gu, Zbigniew Kalbarczyk, Ravishankar K. Iyer Error Sensitivity of the Linux Kernel Executing on PowerPC G4 and Pentium 4 Processors. Search on Bibsonomy DSN The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
33Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis The PowerPC Backend Molen Compiler. Search on Bibsonomy FPL The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
33Robert Bailey, A. Metayer, B. Svrcek, Nandu Tendolkar, E. Wolf, Eric Fiene, Mike Alexander, Rick Woltenberg, Rajesh Raina Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
33Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham Validating PowerPC Microprocessor Custom Memories. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
33Nandu Tendolkar, Robert F. Molyneaux, Carol Pyron, Rajesh Raina At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor. Search on Bibsonomy VTS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF delay testing, at-speed testing, microprocessor testing
33Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham Validation of PowerPC(tm) Custom Memories using Symbolic Simulation. Search on Bibsonomy VTS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Simulation, Validation, Memories, Assertions, Symbolic
33Alan J. Drake, Todd D. Basso, Spencer M. Gold, Keith L. Kraver, Phiroze N. Parakh, Claude R. Gauthier, P. Sean Stetson, Richard B. Brown CGaAs PowerPC FXU. Search on Bibsonomy DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF design methodology, microprocessors, testing methodology, Gallium Arsenide
33L. Robinson, G. Whisenhunt A PowerPC platform full system simulation-from the MOOSE up. Search on Bibsonomy IPCCC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
33Claude Limousin, Alexis Vartanian, Jean-Luc Béchennec PopSPY: A PowerPC Instrumentation Tool for Multiprocessor Simulation. Search on Bibsonomy Euro-Par The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
33Li-C. Wang, Magdy S. Abadir, Jing Zeng On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF assertion test generation, design error model, validation, ATPG, logic verification, symbolic trajectory evaluation
33Li-C. Wang, Magdy S. Abadir, Jing Zeng Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Design Error Models, Verification, Design Validation
33Rajesh Raina, Robert F. Molyneaux Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1998 DBLP  DOI  BibTeX  RDF High-Level Design Validation, Silicon Validation, Pseudo-Random Testing, Microprocessor Testing
33Craig Hunter, Justin Gaither Design and implementation of the "G2" PowerPC 603e-embedded microprocessor core. Search on Bibsonomy ITC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
33Lucas Aaron Womack A Study of Virtual Memory MTU Reassembly within the PowerPC Architectur. Search on Bibsonomy MASCOTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
33Sonya Gary, Pete Ippolito, Gianfranco Gerosa, Carl Dietz, Jim Eno, Hector Sanchez PowerPC 603, A Microprocessor for Portable Computers. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
32Alejandro Rico, Jeff H. Derby, Robert K. Montoye, Timothy H. Heil, Chen-Yong Cher, Pradip Bose Performance and power evaluation of an in-line accelerator. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2010 DBLP  DOI  BibTeX  RDF vmx, accelerator, powerpc, simd
32Joe Gebis, David A. Patterson 0001 Embracing and Extending 20th-Century Instruction Set Architectures. Search on Bibsonomy Computer The full citation details ... 2007 DBLP  DOI  BibTeX  RDF instruction set architectures, PowerPC, SIMD processors, vector architecture
32Jeff H. Derby, Robert K. Montoye, José E. Moreira VICTORIA: VMX indirect compute technology oriented towards in-line acceleration. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF VMX, SIMD, accelerators, powerPC
32Kazunori Ogata, Hideaki Komatsu, Toshio Nakatani Bytecode fetch optimization for a Java interpreter. Search on Bibsonomy ASPLOS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF pipelined interpreter, stack caching, Java, performance, superscalar processor, PowerPC, bytecode interpreter
32Dean E. Dauger, Viktor K. Decyk Numerically-Intensive "Plug-and-Play" Parallel Computing. Search on Bibsonomy CLUSTER The full citation details ... 2001 DBLP  DOI  BibTeX  RDF AppleSeed, plug and play, MacMPI, Pooch, easy, parallel computing, GUI, MPI, cluster computing, Unix, technology transfer, Macintosh, PowerPC, ease of use, Apple, Mac, plasma physics, AltiVec
32Yossi Malka, Avi Ziv Design Reliability - Estimation through Statistical Analysis of Bug Discovery Data. Search on Bibsonomy DAC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF 21264, coverage anaysis, verification, architecture, validation, microprocessor, PowerPC, pseudo-random, Alpha
32Thomas H. Einstein Mercury Computer Systems' modular heterogeneous RACE(R) multicomputer. Search on Bibsonomy Heterogeneous Computing Workshop The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Mercury Computer Systems, modular heterogeneous RACE multicomputer, heterogeneous multicomputer, Analog Devices, SHARC 21060, Apple PowerPC 603p, optimal processor, physical processing density, heterogeneity, distributed memory systems, programmability, IBM, hardware cost, Motorola
32Bruce L. Jacob, Trevor N. Mudge Software-Managed Address Translation. Search on Bibsonomy HPCA The full citation details ... 1997 DBLP  DOI  BibTeX  RDF software-managed address translation, memory management design, high clock-rate PowerPC implementation, OSF/1, superpages, sub-page protection, sparse address spaces, shared memory, storage management, Mach
32Chi-Hung Chi, Siu-Chung Lau Reducing data access penalty using intelligent opcode-driven cache prefetching. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF data access penalty, intelligent opcode-driven, LOAD-UPDATE, LOAD-MODIFY, IBM PowerPC, HP Precision Architecture, intelligent data prefetching, instruction decode unit, storage management, data cache, cache storage, cache prefetching
23Manoel T. F. Cunha, Jose C. F. Telles, Alvaro L. G. A. Coutinho On the Implementation of Boundary Element Engineering Codes on the Cell Broadband Engine. Search on Bibsonomy VECPAR The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Parallel Programming, SIMD, Vectorization, Cell Broadband Engine, Boundary Element Method, Boundary Elements
23Hiroshi Inoue, Takao Moriyama, Hideaki Komatsu, Toshio Nakatani AA-Sort: A New Parallel Sorting Algorithm for Multi-Core SIMD Processors. Search on Bibsonomy PACT The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
23Sándor Héman, Niels Nes, Marcin Zukowski, Peter A. Boncz Vectorized data processing on the cell broadband engine. Search on Bibsonomy DaMoN The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
23Marc Berndl, Benjamin Vitale, Mathew Zaleski, Angela Demke Brown Context Threading: A Flexible and Efficient Dispatch Technique for Virtual Machine Interpreters. Search on Bibsonomy CGO The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
23Akihiko Miyoshi, Charles Lefurgy, Eric Van Hensbergen, Ramakrishnan Rajamony, Raj Rajkumar Critical power slope: understanding the runtime effects of frequency scaling. Search on Bibsonomy ICS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF energy aware computing
23M. D. Bennett, Neil C. Audsley Predictable and Efficient Virtual Addressing for Safety-Critical Real-Time Systems. Search on Bibsonomy ECRTS The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
23Vivek Sarkar, Mauricio J. Serrano, Barbara B. Simons Register-sensitive selection, duplication, and sequencing of instructions. Search on Bibsonomy ICS The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
23Li-C. Wang, Magdy S. Abadir On Efficiently Producing Quality Tests for Custom Circuits in PowerPCTM Microprocessors. Search on Bibsonomy J. Electron. Test. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF custom circuits, high level circuit extraction, ATPG, DFT, time-to-market
23Li-C. Wang, Magdy S. Abadir Experience in Validation of PowerPCTM Microprocessor Embedded Arrays. Search on Bibsonomy J. Electron. Test. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF assertion test generation, assertion, array, design error, logic verification, symbolic trajectory evaluation
23Armin Biere, Edmund M. Clarke, Richard Raimi, Yunshan Zhu Verifiying Safety Properties of a Power PC Microprocessor Using Symbolic Model Checking without BDDs. Search on Bibsonomy CAV The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
23Esther Stümpel, Michael Thies, Uwe Kastens VLIW Compilation Techniques for Superscalar Architectures. Search on Bibsonomy CC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
23E. Kofi Vida-Torku, George Joos Designing for scan test of high performance embedded memories. Search on Bibsonomy ITC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
22Kun Cheng, Weiyue Liu, Qi Shen, Shengkai Liao Design and Implementation of High-throughput PCIe with DMA Architecture between FPGA and PowerPC. Search on Bibsonomy CoRR The full citation details ... 2018 DBLP  BibTeX  RDF
22Rui Zhou 0005, Qingguo Zhou, Yong Sheng, Kuan-Ching Li Erratum to: XtratuM/PPC: a hypervisor for partitioned system on PowerPC processors. Search on Bibsonomy J. Supercomput. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
22Rui Zhou 0005, Qingguo Zhou, Yong Sheng, Kuan-Ching Li XtratuM/PPC: a hypervisor for partitioned system on PowerPC processors. Search on Bibsonomy J. Supercomput. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
22Tareq M. Malas, Aron J. Ahmadia, Jed Brown, John A. Gunnels, David E. Keyes Optimizing the performance of streaming numerical kernels on the IBM Blue Gene/P PowerPC 450 processor. Search on Bibsonomy Int. J. High Perform. Comput. Appl. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
22Radisav Cojbasic, Omer Cogal, Pascal Andreas Meinerzhagen, Christian Senning, Conor Slater, Thomas Maeder, Andreas Burg, Yusuf Leblebici FireBird: PowerPC e200 based SoC for high temperature operation. Search on Bibsonomy CICC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
22Tareq M. Malas, Aron J. Ahmadia, Jed Brown, John A. Gunnels, David E. Keyes Optimizing the Performance of Streaming Numerical Kernels on the IBM Blue Gene/P PowerPC 450 Processor Search on Bibsonomy CoRR The full citation details ... 2012 DBLP  BibTeX  RDF
22 IBM PowerPC. Search on Bibsonomy Encyclopedia of Parallel Computing The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
22Mark Bucciero, John Paul Walters, Roger Moussalli, Shanyuan Gao, Matthew French The PowerPC 405 Memory Sentinel and Injection System. Search on Bibsonomy FCCM The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
22Rod Blaine Foist, Cristian Grecu, André Ivanov, Robin Turner An FPGA Design Project: Creating a PowerPC Subsystem Plus User Logic. Search on Bibsonomy IEEE Trans. Educ. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
22Rod Blaine Foist, André Ivanov, Robin Turner An FPGA Design Project: Creating a PowerPC Subsystem Plus User Logic. Search on Bibsonomy MSE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
22Stephen Barrett, Julie Spratt, Ralph Depping, Ramachandran Ranganathan PowerPC Kernel Implementation for GSM Radio Platform. Search on Bibsonomy ESA The full citation details ... 2007 DBLP  BibTeX  RDF
22Robert H. Bell Jr., Rajiv R. Bhatia, Lizy K. John, Jeff Stuecheli, John Griswell, Paul Tu, Louis Capps, Anton Blanchard, Ravel Thai Automatic testcase synthesis and performance model validation for high performance PowerPC processors. Search on Bibsonomy ISPASS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
22Arvind UNUM: A Tinker-Toy Approach to Building Multicore PowerPC Microarchitectures. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
22Nagu R. Dhanwada, Reinaldo A. Bergamaschi, William W. Dungan, Indira Nair, Paul Gramann, William E. Dougherty, Ing-Chao Lin Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems. Search on Bibsonomy Des. Autom. Embed. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
22Charles D. Wait IBM PowerPC 440 FPU with complex-arithmetic extensions. Search on Bibsonomy IBM J. Res. Dev. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
22Himyanshu Anand, Jayanta Bhadra, Alper Sen 0001, Magdy S. Abadir, Kenneth G. Davis Establishing latch correspondence for embedded circuits of PowerPC microprocessors. Search on Bibsonomy HLDVT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
22Waleed Al-Assadi, Thomas Dick Design for Test Methodology for the IBM PowerPC 440 Embedded Core. Search on Bibsonomy CDES The full citation details ... 2005 DBLP  BibTeX  RDF
22Shivakumar Swaminathan, Sanjay B. Patel, James Dieffenderfer, Joel Silberman Reducing Power Consumption during TLB Lookups in a PowerPC Embedded Processor. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
22Nandu Tendolkar, Dawit Belete, Ashutosh Razdan, Hereman Reyes, Bill Schwarz, Marie Sullivan Test methodology for Freescale's high performance e600 core based on PowerPC© instruction set architecture. Search on Bibsonomy ITC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
22Gerard Boudon, Alan Wall, Joe Foster, Barry Wolford, John Fakiris A 800 MHz PowerPC SOC with PCI-X DDR266, DDRII-667, and RAID assist. Search on Bibsonomy SoCC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
22 Micro News: Moving into the 90-nm chip market; PowerPC runs at up to 2.5 GHz. Search on Bibsonomy IEEE Micro The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
22Kevin J. Nowka, Gary D. Carpenter, Bishop Brock The design and application of the PowerPC 405LP energy-efficient system-on-a-chip. Search on Bibsonomy IBM J. Res. Dev. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
22Hazim Shafi, Patrick J. Bohrer, James Phelan, Cosmin Rusu, James L. Peterson Design and validation of a performance and power simulator for PowerPC systems. Search on Bibsonomy IBM J. Res. Dev. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
22Kevin J. Nowka, Gary D. Carpenter, Eric W. MacDonald, Hung C. Ngo, Bishop Brock, Koji I. Ishii, Tuyet Nguyen, Jeffrey L. Burns A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
22Richard Raimi, James Lear Silicon Debug of a PowerPC[tm] Microprocessor Using Model Checking. Search on Bibsonomy Formal Methods Syst. Des. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
22Daniel Grieg, Cedric Collins, Troy Benjegerdes, Brett M. Bode Linux Clustering using the PowerPC G4 Processor. Search on Bibsonomy IASTED PDCS The full citation details ... 2002 DBLP  BibTeX  RDF
22Paul Kartschoke, Shervin Hojat Techniques that Improved the Timing Convergence of the Gekko PowerPC Microprocessor. Search on Bibsonomy ISQED The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
22Gilbert Vandling Modeling and testing the Gekko microprocessor, an IBM PowerPC derivative for Nintendo. Search on Bibsonomy ITC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
22Keith Diefendorff, Pradeep K. Dubey, Ron Hochsprung, Hunter Scales AltiVec Extension to PowerPC Accelerates Media Processing. Search on Bibsonomy IEEE Micro The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
22Frank P. O'Connell, Steven W. White POWER3: The next generation of PowerPC processors. Search on Bibsonomy IBM J. Res. Dev. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
22John M. Borkenhagen, Richard J. Eickemeyer, Ronald N. Kalla, Steven R. Kunkel A multithreaded PowerPC processor for commercial servers. Search on Bibsonomy IBM J. Res. Dev. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
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