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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 167 occurrences of 116 keywords
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Results
Found 240 publication records. Showing 240 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
140 | Hai Zhou 0001 |
Retiming and resynthesis with sweep are complete for sequential transformation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, FMCAD 2009, 15-18 November 2009, Austin, Texas, USA, pp. 192-197, 2009, IEEE, 978-1-4244-4966-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
132 | Yu Hu 0002, Victor Shih, Rupak Majumdar, Lei He 0001 |
FPGA area reduction by multi-output function based sequential resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 24-29, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, logic synthesis, SAT, resynthesis |
95 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Fixing Design Errors With Counterexamples and Resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1), pp. 184-188, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
95 | Jie-Hong Roland Jiang, Wei-Lun Hung |
Inductive equivalence checking under retiming and resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 326-333, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
80 | Nikolaos D. Liveris, Hai Zhou 0001, Prithviraj Banerjee |
Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 636-641, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
80 | Jie-Hong Roland Jiang, Robert K. Brayton |
Retiming and Resynthesis: A Complexity Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 2674-2686, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
80 | Jie-Hong Roland Jiang |
On Some Transformation Invariants Under Retiming and Resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TACAS ![In: Tools and Algorithms for the Construction and Analysis of Systems, 11th International Conference, TACAS 2005, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2005, Edinburgh, UK, April 4-8, 2005, Proceedings, pp. 413-428, 2005, Springer, 3-540-25333-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
65 | Demetrios Cantzos, Athanasios Mouchtaris, Chris Kyriakakis |
Enhanced Multichannel Audio Resynthesis Through Residual Processing and Features Alignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICME ![In: Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007, July 2-5, 2007, Beijing, China, pp. 1267-1270, 2007, IEEE Computer Society, 1-4244-1017-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
65 | Irith Pomeranz, Sudhakar M. Reddy |
Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(5), pp. 679-689, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
65 | R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi |
Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(10), pp. 1101-1115, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
58 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Fixing Design Errors with Counterexamples and Resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 944-949, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
simulation-based verification, digital design errors, error-correction framework, resynthesis techniques, goal-directed search, entropy-guided search, counterexamples, digital designs, combinational equivalence-checking |
58 | Srivaths Ravi 0001, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey |
Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 13(2), pp. 201-212, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
controller resynthesis, test synthesis, high-level testing |
52 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Safe Delay Optimization for Physical Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 628-633, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
safe delay optimization, SafeResynth, safe resynthesis technique, immediately-measurable delay improvement, circuit timing, route length, physical synthesis, electronic design automation, route congestion, circuit delay |
50 | Martin Heckmann, Claudius Gläser, Miguel Vaz, Tobias Rodemann, Frank Joublin, Christian Goerick |
Listen to the parrot: Demonstrating the quality of online pitch and formant extraction via feature-based resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IROS ![In: 2008 IEEE/RSJ International Conference on Intelligent Robots and Systems, September 22-26, 2008, Acropolis Convention Center, Nice, France, pp. 1699-1704, 2008, IEEE, 978-1-4244-2057-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
50 | Yu Hu 0002, Zhe Feng 0002, Lei He 0001, Rupak Majumdar |
Robust FPGA resynthesis based on fault-tolerant Boolean matching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 706-713, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
50 | Srimat T. Chakradhar, Sujit Dey |
Resynthesis and retiming for optimum partial scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(5), pp. 621-630, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
50 | Christopher K. Lennard, A. Richard Newton |
On estimation accuracy for guiding low-power resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(6), pp. 644-664, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
50 | Heinz-Josef Eikerling, Ralf Hunstock, Raul Camposano |
Optimization of hierarchical designs using partitioning and resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 707-712, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
50 | Kaushik De, Prithviraj Banerjee |
PREST: a system for logic partitioning and resynthesis for testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 1(4), pp. 514-525, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
45 | Athanasios Mouchtaris, Shrikanth S. Narayanan, Chris Kyriakakis |
Multichannel audio synthesis by subband-based spectral conversion and parameter adaptation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Speech Audio Process. ![In: IEEE Trans. Speech Audio Process. 13(2), pp. 263-274, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Angela Krstic, Kwang-Ting Cheng |
Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(1), pp. 43-54, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
resynthesis for testability, timing defects, delay testing, path delay faults, VLSI testing |
43 | Alex Kondratyev, Michael Kishinevsky, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev |
Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands, pp. 240-253, 1997, IEEE Computer Society, 0-8186-7922-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
combinational decomposition, sequential decomposition, monotonous cover, signal insertion, factorization, hazards, resynthesis, Speed-independent circuit |
43 | Samir Lejmi, Bozena Kaminska, Bechir Ayari |
Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 434-439, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
segmentation cells, segmentation edges, logic testing, partitioning, timing, sequential circuits, sequential circuits, iterative methods, circuit analysis computing, retiming, iterative algorithm, circuit optimisation, logic partitioning, logic optimization, resynthesis, synchronous circuits, pseudo-exhaustive testing |
37 | Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour |
Towards automated ECOs in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 3-12, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
pst, optimization, fpga, boolean satisfiability, resynthesis |
37 | W. Knox Carey, Daniel B. Chuang, Sheila S. Hemami |
Regularity-Preserving Image Interpolation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (1) ![In: Proceedings 1997 International Conference on Image Processing, ICIP '97, Santa Barbara, California, USA, October 26-29, 1997, pp. 901-904, 1997, IEEE Computer Society, 0-8186-8183-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
regularity-preserving image interpolation, continuous signal, continuous derivatives, instantaneous luminance transitions, oversmoothed edges, wavelet-based interpolation method, wavelet transform coefficients decay, image resynthesis, average PSNR improvement, bicubic techniques, bilinear techniques, algorithm, image processing, natural images |
37 | Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev |
Decomposition and technology mapping of speed-independent circuits using Boolean relations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 220-227, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Boolean decomposition, decomposed logic sharing, design library, library matching, logic decomposition, logic resynthesis, signal insertion, two-input combinational gate, two-input sequential gate, optimization, technology mapping, circuit CAD, speed-independent circuits, netlist, complex gates, Boolean relations |
37 | Dominik Stoffel, Wolfgang Kunz |
Record & play: a structural fixed point iteration for sequential circuit verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 394-399, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
circuit resynthesis, circuit retiming, combinational verification techniques, instruction queue, iterative circuit array, local circuit transformation, sequential circuit verification, sequential logic equivalence checking, structural fixed point iteration, time frame equivalence, logic testing, finite state machine, logic design |
36 | Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang |
Scalable don't-care-based logic optimization and resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 151-160, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fpga, interpolation, windowing, technology mapping, boolean satisfiability, logic optimization |
36 | Suresh Raman, Mike Lubyanitsky |
Cone Resynthesis ECO Methodology for Multi-Million Gate Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 195-199, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
36 | Murtaza Bulut, Sungbok Lee, Shrikanth S. Narayanan |
Recognition for synthesis: Automatic parameter selection for resynthesis of emotional speech from neutral speech. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2008, March 30 - April 4, 2008, Caesars Palace, Las Vegas, Nevada, USA, pp. 4629-4632, 2008, IEEE, 1-4244-1484-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
36 | Smita Krishnaswamy, Stephen Plaza, Igor L. Markov, John P. Hayes |
Enhancing design robustness with reliability-aware resynthesis and logic simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 149-154, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou |
Incremental physical resynthesis for timing optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 99-108, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA, placement, logic synthesis, timing optimization |
36 | Tiberiu Chelcea, Steven M. Nowick |
Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 405-410, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
36 | Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin |
A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4), pp. 475-483, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
36 | Priyank Kalla, Maciej J. Ciesielski |
Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 638-642, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
36 | Srivaths Ravi 0001, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey |
Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 193-198, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Respecification, Synthesis for Testability, Don't Cares, High Level Testing |
36 | Subhrajit Bhattacharya, Franc Brglez, Sujit Dey |
Transformations and resynthesis for testability of RT-level control-data path specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 1(3), pp. 304-318, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
36 | Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(5), pp. 568-578, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
36 | Sujit Dey, Franc Brglez, Gershon Kedem |
Corolla Based Circuit Partitioning and Resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 607-612, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
30 | Jason Cong, Kirill Minkovich |
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007, pp. 139-147, 2007, ACM, 978-1-59593-600-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
logic synthesis, SAT, implicant, boolean matching, FPGA lookup table |
30 | L.-M. Reissell, Dinesh K. Pai |
High Resolution Analysis of Impact Sounds and Forces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WHC ![In: Second Joint EuroHaptics Conference and Symposium on Haptic Interfaces for Virtual Environment and Teleoperator Systems, WHC 2007, Tsukuba, Japan, March 22-24, 2007, pp. 255-260, 2007, IEEE Computer Society, 978-0-7695-2738-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Milenko Drinic, Darko Kirovski |
Behavioral synthesis via engineering change. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 18-21, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
engineering change, scheduling, transformations, register assignment |
30 | Enrique San Millán, Luis Entrena, José Alberto Espejo |
On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 292-299, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
30 | Huiqun Liu, Martin D. F. Wong |
Network-flow-based multiway partitioning with area and pin constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(1), pp. 50-59, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
30 | Chris J. Myers, Peter A. Beerel, Teresa H.-Y. Meng |
Technology mapping of timed circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 138-, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
gate library, C-elements, ATACS, timing, logic design, logic CAD, asynchronous circuits, asynchronous circuits, timing information, AND gates, synthesis tool, OR gates, timed circuits |
30 | Carl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton |
Multi-level synthesis for safe replaceability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 442-449, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
22 | Dominic Wist, Mark Schäfer, Walter Vogler, Ralf Wollowski |
STG Decomposition: Internal Communication for SI Implementability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 10th International Conference on Application of Concurrency to System Design, ACSD 2010, Braga, Portugal, 21-25 June 2010, pp. 13-23, 2010, IEEE Computer Society, 978-0-7695-4066-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
CSC, decomposition, STG, resynthesis, speed independent |
22 | Iris Hui-Ru Jiang, Hua-Yu Chang, Liang-Gi Chang, Huang-Bi Hung |
Matching-based minimum-cost spare cell selection for design changes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 408-411, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
spare cells, matching, physical synthesis, resynthesis, ECO |
22 | Hosung (Leo) Kim, John Lillis |
A framework for layout-level logic restructuring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008, pp. 87-94, 2008, ACM, 978-1-60558-048-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
logic resynthesis, timing optimization |
22 | Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown |
FPGA technology mapping: a study of optimality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 427-432, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
resynthesis optimization, FPGA, boolean satisfiability, lookup table, cone |
22 | Stephen A. Edwards |
Making cyclic circuits acyclic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 159-162, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
acyclic circuits, cyclic circuits, constructiveness, resynthesis |
22 | François R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Michel Boyer |
Optimal design of synchronous circuits using software pipelining techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(4), pp. 516-532, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
software pipelining, retiming, Resynthesis |
22 | Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija |
CMOS Combinational Circuit Sizing by Stage-wise Tapering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 985-986, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
tapering, Transistor sizing, resynthesis |
22 | Irith Pomeranz, Sudhakar M. Reddy |
On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 45(1), pp. 50-62, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Lower bound on test set size, pipelining, multipliers, path delay faults, resynthesis |
22 | Roman Kuznar, Franc Brglez |
PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 644-649, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
optimization, FPGA, partitioning, resynthesis, critical path delay |
22 | Demetri Terzopoulos, Keith Waters |
Analysis and Synthesis of Facial Image Sequences Using Physical and Anatomical Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 15(6), pp. 569-579, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
expressions resynthesis, facial image sequences, graphics workstation, physics-based synthetic facial tissue, anatomically motivated facial muscle actuators, dynamical facial muscle contractions, expressive human faces, deformable contour models, image sequences, computer animation, facial animation, video sequences, snakes, biomechanics, biomechanics, face model, anatomical models |
21 | Siang-Yun Lee, Giovanni De Micheli |
Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11), pp. 3958-3971, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Ünal Ege Gaznepoglu, Nils Peters |
Evaluation of the Speech Resynthesis Capabilities of the VoicePrivacy Challenge Baseline B1. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2308.11337, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Navin Raj Prabhu, Nale Lehmann-Willenbrock, Timo Gerkmann |
In-the-wild Speech Emotion Conversion Using Disentangled Self-Supervised Representations and Neural Vocoder-based Resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2306.01916, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Tu Anh Nguyen, Wei-Ning Hsu, Antony D'Avirro, Bowen Shi, Itai Gat, Maryam Fazel-Zarandi, Tal Remez, Jade Copet, Gabriel Synnaeve, Michael Hassid, Felix Kreuk, Yossi Adi, Emmanuel Dupoux |
EXPRESSO: A Benchmark and Analysis of Discrete Expressive Speech Resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2308.05725, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Arianne Meijer-van de Griend |
Towards a generic compilation approach for quantum circuits through resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2304.08814, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Felipe Almeida, Levent Aksoy, Quang-Linh Nguyen, Sophie Dupuis, Marie-Lise Flottes, Samuel Pagliarini |
Resynthesis-based Attacks Against Logic Locking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2301.04400, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Wei-Ning Hsu, Tal Remez, Bowen Shi, Jacob Donley, Yossi Adi |
ReVISE: Self-Supervised Speech Resynthesis with Visual Input for Universal and Generalized Speech Regeneration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CVPR ![In: IEEE/CVF Conference on Computer Vision and Pattern Recognition, CVPR 2023, Vancouver, BC, Canada, June 17-24, 2023, pp. 18796-18806, 2023, IEEE, 979-8-3503-0129-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Felipe Almeida, Levent Aksoy, Quang-Linh Nguyen, Sophie Dupuis, Marie-Lise Flottes, Samuel Pagliarini |
Resynthesis-based Attacks Against Logic Locking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 24th International Symposium on Quality Electronic Design, ISQED 2023, San Francisco, CA, USA, April 5-7, 2023, pp. 1-8, 2023, IEEE, 979-8-3503-3475-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Görkem Gök, Özgül Salor, Müslüm Cengiz Taplamacioglu |
An Electric Arc Furnace Model Based on Resynthesis Using Frequency Spectrum Distributions of EAF Currents. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IAS ![In: IEEE Industry Applications Society Annual Meeting, IAS 2023, Nashville, TN, USA, October 29 - Nov. 2, 2023, pp. 1-15, 2023, IEEE, 979-8-3503-2016-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Tianji Liu, Evangeline F. Y. Young |
Rethinking AIG Resynthesis in Parallel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 60th ACM/IEEE Design Automation Conference, DAC 2023, San Francisco, CA, USA, July 9-13, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-2348-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Federico Simonetta, Federico Avanzini, Stavros Ntalampiras |
A perceptual measure for evaluating the resynthesis of automatic music transcriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multim. Tools Appl. ![In: Multim. Tools Appl. 81(22), pp. 32371-32391, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich |
SCAR: Security Compliance Analysis and Resynthesis of Reconfigurable Scan Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12), pp. 5644-5656, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Federico Simonetta |
Music Interpretation Analysis. A Multimodal Approach To Score-Informed Resynthesis of Piano Recordings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2205.00941, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Federico Simonetta, Federico Avanzini, Stavros Ntalampiras |
A Perceptual Measure for Evaluating the Resynthesis of Automatic Music Transcriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2202.12257, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
21 | Wei-Ning Hsu, Tal Remez, Bowen Shi, Jacob Donley, Yossi Adi |
ReVISE: Self-Supervised Speech Resynthesis with Visual Input for Universal and Generalized Speech Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2212.11377, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Heinz Riener, Siang-Yun Lee, Alan Mishchenko, Giovanni De Micheli |
Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 27th Asia and South Pacific Design Automation Conference, ASP-DAC 2022, Taipei, Taiwan, January 17-20, 2022, pp. 395-402, 2022, IEEE, 978-1-6654-2135-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Adam Polyak, Yossi Adi, Jade Copet, Eugene Kharitonov, Kushal Lakhotia, Wei-Ning Hsu, Abdelrahman Mohamed, Emmanuel Dupoux |
Speech Resynthesis from Discrete Disentangled Self-Supervised Representations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2104.00355, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
21 | Siang-Yun Lee, Heinz Riener, Giovanni De Micheli |
Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 105-110, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Adam Polyak, Yossi Adi, Jade Copet, Eugene Kharitonov, Kushal Lakhotia, Wei-Ning Hsu, Abdelrahman Mohamed, Emmanuel Dupoux |
Speech Resynthesis from Discrete Disentangled Self-Supervised Representations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Interspeech ![In: Interspeech 2021, 22nd Annual Conference of the International Speech Communication Association, Brno, Czechia, 30 August - 3 September 2021., pp. 3615-3619, 2021, ISCA. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Jitka Kocnová, Zdenek Vasícek |
Resynthesis of logic circuits using machine learning and reconvergent paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 24th Euromicro Conference on Digital System Design, DSD 2021, Virtual Event / Palermo, Sicily, Italy, September 1-3, 2021, pp. 69-76, 2021, IEEE, 978-1-6654-2703-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Milos Ajcevic, Agostino Accardo, Maria Pia Francescato |
Modeling of glycogen resynthesis according to insulin concentration: towards a system for prevention of late-onset exercise-induced hypoglycemia in Type 1 diabetes patients. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES ![In: Knowledge-Based and Intelligent Information & Engineering Systems: Proceedings of the 25th International Conference KES-2021, Virtual Event / Szczecin, Poland, 8-10 September 2021., pp. 2903-2911, 2021, Elsevier. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich |
Testability-Enhancing Resynthesis of Reconfigurable Scan Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: IEEE International Test Conference, ITC 2021, Anaheim, CA, USA, October 10-15, 2021, pp. 20-29, 2021, IEEE, 978-1-6654-1695-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Wenting Dai, Marius Erdt, Alexei Sourin |
Anomaly Detection and Segmentation Based on Defect Repaired Image Resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CW ![In: International Conference on Cyberworlds, CW 2021, Caen, France, September 28-30, 2021, pp. 109-112, 2021, IEEE, 978-1-6654-4065-3. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Hao Shi, Wei Dong 0006, Rui Li 0050, Wanwei Liu |
Controller Resynthesis for Multirobot System When Changes Happen. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 53(12), pp. 69-79, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Jitka Kocnová, Zdenek Vasícek |
EA-based resynthesis: an efficient tool for optimization of digital circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Genet. Program. Evolvable Mach. ![In: Genet. Program. Evolvable Mach. 21(3), pp. 287-319, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Jeongwoo Heo, Taewhan Kim |
Lightening Asynchronous Pipeline Controller Through Resynthesis and Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 25th Asia and South Pacific Design Automation Conference, ASP-DAC 2020, Beijing, China, January 13-16, 2020, pp. 587-592, 2020, IEEE, 978-1-7281-4123-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Soumi Maiti, Michael I. Mandel |
Speaker Independence of Neural Vocoders and Their Effect on Parametric Resynthesis Speech Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: 2020 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2020, Barcelona, Spain, May 4-8, 2020, pp. 206-210, 2020, IEEE, 978-1-5090-6631-5. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Natalia Lylina, Ahmed Atteya, Chih-Hao Wang, Hans-Joachim Wunderlich |
Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: IEEE International Test Conference, ITC 2020, Washington, DC, USA, November 1-6, 2020, pp. 1-10, 2020, IEEE, 978-1-7281-9113-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman |
Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 24(4), pp. 42:1-42:19, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Soumi Maiti, Michael I. Mandel |
Speaker independence of neural vocoders and their effect on parametric resynthesis speech enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1911.06266, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
21 | Soumi Maiti, Michael I. Mandel |
Speech denoising by parametric resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1904.01537, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
21 | Soumi Maiti, Michael I. Mandel |
Parametric Resynthesis with neural vocoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1906.06762, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
21 | Krzysztof Lis, Krishna K. Nakka, Pascal Fua, Mathieu Salzmann |
Detecting the Unexpected via Image Resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1904.07595, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
21 | Krzysztof Lis, Krishna Kanth Nakka, Pascal Fua, Mathieu Salzmann |
Detecting the Unexpected via Image Resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCV ![In: 2019 IEEE/CVF International Conference on Computer Vision, ICCV 2019, Seoul, Korea (South), October 27 - November 2, 2019, pp. 2152-2161, 2019, IEEE, 978-1-7281-4803-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman |
Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, Florence, Italy, March 25-29, 2019, pp. 1022-1027, 2019, IEEE, 978-3-9819263-2-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Soumi Maiti, Michael I. Mandel |
Parametric Resynthesis With Neural Vocoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WASPAA ![In: 2019 IEEE Workshop on Applications of Signal Processing to Audio and Acoustics, WASPAA 2019, New Paltz, NY, USA, October 20-23, 2019, pp. 303-307, 2019, IEEE, 978-1-7281-1123-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Soumi Maiti, Michael I. Mandel |
Speech Denoising by Parametric Resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2019, Brighton, United Kingdom, May 12-17, 2019, pp. 6995-6999, 2019, IEEE, 978-1-4799-8131-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Christopher Beckham, Sina Honari, Vikas Verma, Alex Lamb, Farnoosh Ghadiri, R. Devon Hjelm, Yoshua Bengio, Chris Pal |
On Adversarial Mixup Resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NeurIPS ![In: Advances in Neural Information Processing Systems 32: Annual Conference on Neural Information Processing Systems 2019, NeurIPS 2019, December 8-14, 2019, Vancouver, BC, Canada., pp. 4348-4359, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
21 | Rafael Trapani Possignolo, Jose Renau |
SMatch: Structural Matching for Fast Resynthesis in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, Las Vegas, NV, USA, June 02-06, 2019, pp. 75, 2019, ACM, 978-1-4503-6725-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Hsin-Ho Huang, Huimei Cheng, Chris Chu, Peter A. Beerel |
Area Optimization of Timing Resilient Designs Using Resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6), pp. 1197-1210, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Soumi Maiti, Joey Ching, Michael I. Mandel |
Large Vocabulary Concatenative Resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INTERSPEECH ![In: Interspeech 2018, 19th Annual Conference of the International Speech Communication Association, Hyderabad, India, 2-6 September 2018., pp. 1190-1194, 2018, ISCA. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Ali Raza Syed, Viet Anh Trinh, Michael I. Mandel |
Concatenative Resynthesis with Improved Training Signals for Speech Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INTERSPEECH ![In: Interspeech 2018, 19th Annual Conference of the International Speech Communication Association, Hyderabad, India, 2-6 September 2018., pp. 1195-1199, 2018, ISCA. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Alexander L. Stempkovskiy, Dmitry V. Telpukhov, Vladislav Nadolenko |
Development of Resynthesis Flow for Improving Logical Masking Features of Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 2018 IEEE East-West Design & Test Symposium, EWDTS 2018, Kazan, Russia, September 14-17, 2018, pp. 1-7, 2018, IEEE, 978-1-5386-5710-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli |
Improvements to boolean resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018, pp. 755-760, 2018, IEEE, 978-3-9819263-0-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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