Search results for "routability"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
115	Zhe-Wei Jiang, Bor-Yiing Su, Yao-Wen Chang	Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs.	DAC	2008	DBLP DOI BibTeX RDF	placement, physical design, routability
82	Aiguo Lu, Erik L. Dagless, Jonathan M. Saul	DART: delay and routability driven technology mapping for LUT based FPGAs.	ICCD	1995	DBLP DOI BibTeX RDF	DART, delay driven technology mapping, LUT based FPGAs, two-phased approach, routability directed delay-optimal mapping, stochastic routability analysis, delay-optimal mapping, field programmable gate arrays, delays, logic design, programmable logic arrays, table lookup, minimisation of switching nets
73	Elaheh Bozorgzadeh, Seda Ogrenci Memik, Majid Sarrafzadeh	RPack: routability-driven packing for cluster-based FPGAs.	ASP-DAC	2001	DBLP DOI BibTeX RDF
73	Wei Li, Dilip K. Banerji	Routability Prediction for Hierarchical FPGAs.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
73	Kaushik Roy 0001, Sudip Nag	Automatic synthesis of FPGA channel architecture for routability and performance.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
72	Jin-Tai Yan, Chung-Wei Ke, Zhi-Wei Chen	Ordered escape routing via routability-driven pin assignment.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	pcb design, routability, escape routing, pin assignment
72	Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh	Routability driven white space allocation for fixed-die standard-cell placement.	ISPD	2002	DBLP DOI BibTeX RDF	placement, physical design, routability
72	PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia	On metrics for comparing routability estimation methods for FPGAs.	DAC	2002	DBLP DOI BibTeX RDF	RISA, fGREP, routability estimation, FPGA, congestion, rent's rule
62	Peter Spindler, Frank M. Johannes	Fast and accurate routing demand estimation for efficient routability-driven placement.	DATE	2007	DBLP DOI BibTeX RDF
62	Chiu-Wing Sham, Evangeline F. Y. Young	Routability-driven floorplanner with buffer block planning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
62	Chiu-Wing Sham, Evangeline F. Y. Young	Routability driven floorplanner with buffer block planning.	ISPD	2002	DBLP DOI BibTeX RDF
62	R. Glenn Wood, Rob A. Rutenbar	FPGA routing and routability estimation via Boolean satisfiability.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
62	Yuh-Sheng Lee, Allen C.-H. Wu	A performance and routability-driven router for FPGAs considering path delays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
62	Martine D. F. Schlag, Jackson Kong, Pak K. Chan	Routability-driven technology mapping for lookup table-based FPGA's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
62	Chih-Liang Eric Cheng	RISA: accurate and efficient placement routability modeling.	ICCAD	1994	DBLP DOI BibTeX RDF
62	Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic	A stochastic model to predict the routability of field-programmable gate arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
61	Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan	BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	VLSI, physical design, congestion, integer linear programming, global routing, routability, layer assignment
60	Samy M. Boshra, Hazem M. Abbas, Ahmed M. Darwish 0001, Ihab E. Talkhan	Performance and routability improvements for routability-driven FPGA routers.	ISCAS	2006	DBLP DOI BibTeX RDF
54	Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger	Optimal routing algorithms for rectilinear pin clusters in high-density multichip modules.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	multi-chip modules, network flow, Escape routing
54	Minsik Cho, David Z. Pan	BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
54	Elaheh Bozorgzadeh, Majid Sarrafzadeh	Customized regular channel design in FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF
54	Bo Hu 0006, Malgorzata Marek-Sadowska	Congestion minimization during placement without estimation.	ICCAD	2002	DBLP DOI BibTeX RDF
51	Akshay Sharma, Carl Ebeling, Scott Hauck	Architecture Adaptive Routability-Driven Placement for FPGAs (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
51	Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh	Routability-driven white space allocation for fixed-die standard-cell placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
51	PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia	Rapid and Reliable Routability Estimation for FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
51	Vicente Baena Lecuyer, M. A. Aguirre, Antonio Jesús Torralba Silgado, Leopoldo García Franquelo, Julio Faura	Decoder-driven switching matrices in multicontext FPGAs: area reduction and their effect on routability.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
51	Chi-Chou Kao, Yen-Tai Lai	A routability and performance driven technology mapping algorithm for LUT based FPGA designs.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
51	Kai Zhu 0001, Martin D. F. Wong	Switch bound allocation for maximizing routability in timing-driven routing of FPGA's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
51	Jianmin Li, Chung-Kuan Cheng	Routability improvement using dynamic interconnect architecture.	FCCM	1995	DBLP DOI BibTeX RDF
51	Michael D. Osterman, Michael G. Pecht	Placement for reliability and routability of convectively cooled PWBs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
51	Shigetoshi Nakatake, Zohreh Karimi, Taraneh Taghavi, Majid Sarrafzadeh	Block placement to ensure channel routability.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	routing space, placement, channel, routability
51	Man-Fai Yu, Wayne Wei-Ming Dai	Single-layer fanout routing and routability analysis for Ball Grid Arrays.	ICCAD	1995	DBLP DOI BibTeX RDF	package routing, ball grid array, pin grid array, planar routing, even wiring, fanout routing, routability
43	Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh	Creating and exploiting flexibility in rectilinear Steiner trees.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
42	Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He 0001, Robi Dutta, Xianlong Hong	Diffusion-driven congestion reduction for substrate topological routing.	ISPD	2009	DBLP DOI BibTeX RDF	congestion reduction, ic package, substrate routing, diffusion, routability
42	Ji Zhang, David A. J. Pearce	Proactive care-of address test for route optimization in FMIPv6.	WMASH	2005	DBLP DOI BibTeX RDF	care-of address, return routability test, handover, mobile IPv6, route optimization
42	Yao-Wen Chang, D. F. Wong 0001, C. K. Wong	Design and analysis of FPGA/FPIC switch modules.	ICCD	1995	DBLP DOI BibTeX RDF	FPGA/FPIC switch modules, routing resources, FPIC, network-flow techniques, field programmable interconnect chip, field programmable gate arrays, FPGA, field programmable gate arrays, logic design, heuristic algorithm, programmable logic arrays, routability
41	Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang	Metal-Density-Driven Placement for CMP Variation and Routability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
41	Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang	Metal-density driven placement for cmp variation and routability.	ISPD	2008	DBLP DOI BibTeX RDF	VLSI, placement, physical design, manufacturability
41	Chen Li 0004, Min Xie 0004, Cheng-Kok Koh, Jason Cong, Patrick H. Madden	Routability-Driven Placement and White Space Allocation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
41	Masaki Kobata, Masahiro Iida, Toshinori Sueyoshi	Effective clustering technique to optimize routability of outer cluster nets.	FPGA	2006	DBLP DOI BibTeX RDF
41	Xuan-Lun Huang, Jiun-Lang Huang	A routability constrained scan chain ordering technique for test power reduction.	ASP-DAC	2006	DBLP DOI BibTeX RDF
41	Taraneh Taghavi, Soheil Ghiasi, Majid Sarrafzadeh	Routing algorithms: enhancing routability & enabling ECO (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
41	William N. N. Hung, Xiaoyu Song, El Mostapha Aboulhamid, Andrew A. Kennings, Alan J. Coppola	Segmented channel routability via satisfiability.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	Satisfiability
41	Hu Huang 0001, Joseph B. Bernstein, Martin Peckerar, Ji Luo 0003	Combined Channel Segmentation and Buffer Insertion for Routability and Performance Improvement of Field.	ICCD	2004	DBLP DOI BibTeX RDF
40	Andrew Lim 0001, Sartaj K. Sahni, Venkat Thanvantri	A fast algorithm to test planar topological routability.	VLSI Design	1995	DBLP DOI BibTeX RDF	planar topological routability testing, pin nets, single layer routing, IC layout design, VLSI, network topology, network routing, circuit layout CAD, fast algorithm, VLSI layout, integrated circuit layout, linear time algorithm
38	Chia-Tung Ho, Alvin Ho, Matthew Fojtik, Minsoo Kim, Shang Wei, Yaguang Li, Brucek Khailany, Haoxing Ren	NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model.	ISPD	2023	DBLP DOI BibTeX RDF
38	I-Lun Tseng, Zhao Chuan Lee, Vikas Tripathi, Chun Ming Tommy Yip, Zhinan Chen, Jonathan Ong	A System for Standard Cell Routability Checking and Placement Routability Improvements.	APCCAS	2019	DBLP DOI BibTeX RDF
32	Chiu-Wing Sham, Evangeline F. Y. Young, Jingwei Lu	Congestion prediction in early stages of physical design.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	placement, Estimation, floorplanning
32	Jin-Tai Yan, Zhi-Wei Chen	IO connection assignment and RDL routing for flip-chip designs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
32	Dae Hyun Kim 0004, Sung Kyu Lim	Bus-aware microarchitectural floorplanning.	ASP-DAC	2008	DBLP DOI BibTeX RDF
32	Chih-Hung Liu 0001, Yao-Hsin Chou, Shih-Yi Yuan, Sy-Yen Kuo	Efficient multilayer routing based on obstacle-avoiding preferred direction steiner tree.	ISPD	2008	DBLP DOI BibTeX RDF	routing, spanning tree, physical design, steiner tree
32	Arijit Ganguly, P. Oscar Boykin, David Wolinsky, Renato J. O. Figueiredo	Improving peer connectivity in wide-area overlays of virtual workstations.	HPDC	2008	DBLP DOI BibTeX RDF	p2p, DHT, overlay, virtual network
32	Minsik Cho, David Z. Pan	BoxRouter: a new global router based on box expansion and progressive ILP.	DAC	2006	DBLP DOI BibTeX RDF	VLSI, congestion, global routing
32	Chiu-Wing Sham, Evangeline F. Y. Young	Congestion prediction in early stages.	SLIP	2005	DBLP DOI BibTeX RDF	placement, floorplanning, interconnect estimation
32	Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh	Pattern routing: use and theory for increasing predictability andavoiding coupling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
32	Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh	A Standard-Cell Placement Tool for Designs with High Row Utilization.	ICCD	2002	DBLP DOI BibTeX RDF
32	Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien	Spectral-based multiway FPGA partitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
32	Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien	Spectral-Based Multi-Way FPGA Partitioning.	FPGA	1995	DBLP DOI BibTeX RDF
31	Jin-Tai Yan, Zhi-Wei Chen	RDL pre-assignment routing for flip-chip designs.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	RDL routing, flip-chip design, routability, wirelength
31	Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma	An accurate and efficient probabilistic congestion estimation model in x architecture.	SLIP	2007	DBLP DOI BibTeX RDF	congestion estimation, dynamic resource assignment, the X architecture, routability
31	Lerong Cheng, Xiaoyu Song, Guowu Yang, Zhiwei Tang	A fast congestion estimator for routing with bounded detours.	ASP-DAC	2004	DBLP DOI BibTeX RDF	Congestion Estimation, Routing, Placement, Routability, Probabilistic Methods
31	Navaratnasothie Selvakkumaran, Phiroze N. Parakh, George Karypis	Perimeter-degree: a priori metric for directly measuring and homogenizing interconnection complexity in multilevel placement.	SLIP	2003	DBLP DOI BibTeX RDF	interconnection complexity, multilevel global placement, nonhomogeneity, perimeter-degree, congestion, routability
31	Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani	Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs.	ISPD	2002	DBLP DOI BibTeX RDF	floorplanning, routability, interconnect estimation
31	Michael Shyu, Yu-Dong Chang, Guang-Ming Wu, Yao-Wen Chang	Generic Universal Switch Blocks.	ICCD	1999	DBLP DOI BibTeX RDF	HFPGA, logic block, switch block, programmable switch, universal switch block, dimension constraint, FPGA, routing, flexibility, routability
31	Hans-Georg Martin, Wolfgang Rosenstiel	A Comparing Study of Technology Mapping for FPGA.	DATE	1998	DBLP DOI BibTeX RDF	mapping for routability, computation time, design alternatives, FPGA design
30	Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko	WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	area flow, cut enumeration, edge flow, FPGA, technology mapping
30	Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou 0001	Optimizing wirelength and routability by searching alternative packings in floorplanning.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	wirelength reduction, Floorplanning
30	Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko	WireMap: FPGA technology mapping for improved routability.	FPGA	2008	DBLP DOI BibTeX RDF	area flow, cut enumeration, edge flow, FPGA, technology mapping
30	Kanupriya Gulati, Sunil P. Khatri	Improving FPGA routability using network coding.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	FPGA, network coding
30	Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He 0001, Tianpei Zhang, Robi Dutta, Xianlong Hong	Topological routing to maximize routability for package substrate.	DAC	2008	DBLP DOI BibTeX RDF	IC package, substrate routing, system in package
30	Youngsong Mun, Kyunghye Lee, Seonggeun Ryu, Teail Shin	Using Return Routability for Authentication of Fast Handovers in Mobile IPv6.	ICCSA (2)	2007	DBLP DOI BibTeX RDF
30	Manuel Saldaña, Lesley Shannon, Paul Chow	The routability of multiprocessor network topologies in FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF
30	Manuel Saldaña, Lesley Shannon, Paul Chow	The routability of multiprocessor network topologies in FPGAs.	SLIP	2006	DBLP DOI BibTeX RDF	FPGA, multiprocessor, network-on-chip, topology, interconnect
30	Yu Hu 0002, Tong Jing, Xianlong Hong, Xiaodong Hu 0001, Guiying Yan	A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design.	SAMOS	2005	DBLP DOI BibTeX RDF
30	Ying Qiu, Jianying Zhou 0001, Robert H. Deng	Security Analysis and Improvement of Return Routability Protocol.	MADNES	2005	DBLP DOI BibTeX RDF	Redirect Attacks, Security, Authentication, MIPv6
30	William N. N. Hung, Xiaoyu Song, T. Kam, Lerong Cheng, Guowu Yang	Routability checking for three-dimensional architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
30	Chen Li 0004, Min Xie 0004, Cheng-Kok Koh, Jason Cong, Patrick H. Madden	Routability-driven placement and white space allocation.	ICCAD	2004	DBLP DOI BibTeX RDF
30	Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi	Routability and Fault Tolerance of FPGA Interconnect Architectures.	ITC	2004	DBLP DOI BibTeX RDF
30	Niwat Waropus, Rajendar Koltur, Malgorzata Chrzanowska-Jeske	Graph-based approach to evaluate net routability of a floorplan.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
30	Zhibin Dai, Dilip K. Banerji	Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy.	VLSI Design	2003	DBLP DOI BibTeX RDF
30	Shih-Ping Lin 0001, Yao-Wen Chang	A novel framework for multilevel routing considering routability and performance.	ICCAD	2002	DBLP DOI BibTeX RDF
30	Probir Sarkar, Cheng-Kok Koh	Routability-driven repeater block planning for interconnect-centricfloorplanning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
30	Mehdi M. Mechaik	Electrical Characterization of Signal Routability and Performance.	ISQED	2000	DBLP DOI BibTeX RDF
30	Toshiyuki Hama, Hiroaki Etoh	Topological routing path search algorithm with incremental routability test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
30	Jianmin Li, Chung-Kuan Cheng	Routability improvement using dynamic interconnect architecture.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
30	Jordan S. Swartz, Vaughn Betz, Jonathan Rose	A Fast Routability-Driven Router for FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF
21	Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li 0001, Charles J. Alpert, Shyam Ramji, Chris Chu	ITOP: integrating timing optimization within placement.	ISPD	2010	DBLP DOI BibTeX RDF	placement, timing optimization, physical synthesis
21	Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He 0001, Tianpei Zhang, Robi Dutta, Xianlong Hong	Substrate Topological Routing for High-Density Packages.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
21	Jinpeng Zhao, Qiang Zhou 0001, Yici Cai	Fast congestion-aware timing-driven placement for island FPGA.	DDECS	2009	DBLP DOI BibTeX RDF
21	Ke-Ren Dai, Wen-Hao Liu, Yih-Lang Li	Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing.	ASP-DAC	2009	DBLP DOI BibTeX RDF
21	Valerij Matrose, Carsten Gremzow	Improved placement for hierarchical FPGAs exploiting local interconnect resources.	SBCCI	2009	DBLP DOI BibTeX RDF	FPGA, interconnect, placement
21	Wenyi Feng, Sinan Kaptanoglu	Designing Efficient Input Interconnect Blocks for LUT Clusters Using Counting and Entropy.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	cluster, FPGAs, entropy, interconnect, counting, PLDs, LUT
21	Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu 0002, Zhe Feng 0002, Lei He 0001, Xianlong Hong	Fashion: A Fast and Accurate Solution to Global Routing Problem.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
21	Peter Spindler, Ulf Schlichtmann, Frank M. Johannes	Abacus: fast legalization of standard cell circuits with minimal movement.	ISPD	2008	DBLP DOI BibTeX RDF	minimal movement, standard cell circuits, dynamic programming, legalization
21	Wenyi Feng, Sinan Kaptanoglu	Designing efficient input interconnect blocks for LUT clusters using counting and entropy.	FPGA	2007	DBLP DOI BibTeX RDF	cluster, FPGAs, entropy, interconnect, counting, PLDs, LUT
21	Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan	BoxRouter 2.0: architecture and implementation of a hybrid and robust global router.	ICCAD	2007	DBLP DOI BibTeX RDF
21	Muhammet Mustafa Ozdal, Martin D. F. Wong	Archer: a history-driven global routing algorithm.	ICCAD	2007	DBLP DOI BibTeX RDF
21	Min Pan, Chris C. N. Chu	IPR: An Integrated Placement and Routing Algorithm.	DAC	2007	DBLP DOI BibTeX RDF
21	Jarrod A. Roy, Saurabh N. Adya, David A. Papa, Igor L. Markov	Min-cut floorplacement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
21	Joseph S. Kong, Jesse S. A. Bridgewater, Vwani P. Roychowdhury	A General Framework for Scalability and Performance Analysis of DHT Routing Systems.	DSN	2006	DBLP DOI BibTeX RDF