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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 9752 publication records. Showing 9752 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
131 | Jin Li, Chuan-lin Wu |
A modular growth architecture for an ATM switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCN ![In: Proceedings of the 4th International Conference on Computer Communications and Networks (ICCCN '95), September 20-23, 1995, Las Vegas, Nevada, USA, pp. 420, 1995, IEEE Computer Society, 0-8186-7180-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
modular growth architecture, growable ATM switch architecture, large scale ATM switch, switch size, nonuniform modular growth ATM switch, knockout switch, internal traffic, nonuniform concentration, connection pattern, performance, delay, throughput, telecommunication traffic |
106 | Hyoung-Il Lee, Seung-Woo Seo |
Matching output queueing with a multiple input/output-queued switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 14(1), pp. 121-132, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
combined input/output-queued (CIOQ) switch, multiple input/output-queued (MIOQ) switch, output queueing emulation, parallel switching architecture |
96 | Hongbing Fan, Yu-Liang Wu, Ray Chak-Chung Cheung, Jiping Liu |
Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(4), pp. 373-384, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
reconfigurable interconnection network, switch block, hyperuniversal, FPGA, universal, switch box |
89 | Cheng-Shang Chang, Duan-Shin Lee, Ching-Ming Lien |
Load balanced Birkhoff-von Neumann switches with resequencing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS Perform. Evaluation Rev. ![In: SIGMETRICS Perform. Evaluation Rev. 29(3), pp. 23-24, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
88 | Michael Shyu, Yu-Dong Chang, Guang-Ming Wu, Yao-Wen Chang |
Generic Universal Switch Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 311-314, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
HFPGA, logic block, switch block, programmable switch, universal switch block, dimension constraint, FPGA, routing, flexibility, routability |
80 | Sundar Iyer, Nick McKeown |
Analysis of the parallel packet switch architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 11(2), pp. 314-324, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
output queueing, load balancing, packet switch, Clos network, inverse multiplexing |
79 | Deng Pan, Yuanyuan Yang 0001 |
FIFO-Based Multicast Scheduling Algorithm for Virtual Output Queued Packet Switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(10), pp. 1283-1297, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
virtual output queued (VOQ) switch, head of line (HOL) blocking, scheduling, Multicast, crossbar switch, multicast switch |
78 | Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu |
A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 102-103, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Birkhoff-von Neumann symmetric TDM switch IC, SERDES interfaces, load-balanced TDM switch IC, digital TDM switch, 8B10B CODEC, analog SERDES I/O interfaces, dual-mode SERDES, half-rate architectures, all static CMOS gates, wide-band CML buffer, PMOS active load scheme, 20 Gbit/s, high speed networking, CMOS technology, low power consumption, 0.18 micron |
78 | Sushil Aryal, James S. Meditch |
Design of a large ATM switch with trunk grouping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCN ![In: Proceedings of the 4th International Conference on Computer Communications and Networks (ICCCN '95), September 20-23, 1995, Las Vegas, Nevada, USA, pp. 406, 1995, IEEE Computer Society, 0-8186-7180-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
load throughput value, dense VLSI implementation, large ATM switch with trunk grouping, LAST switch, IBSS, ideal bit by bit self routing switch, delay, topology, throughput, interconnections, communication complexity, modules, circuit complexity, cell loss |
73 | Aditya Agrawal, Anand Raju, Sachidanand Varadarajan, Magdy A. Bayoumi |
A scalable shared buffer ATM switch architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 256-261, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
electronic switching systems, field effect transistor switches, scalable shared buffer ATM switch architecture, memory bandwidth requirement, maximum crosspoint switch size, buffer memory size, access time reduction, multiple buffer memories, 8/spl times/8 switch, 1 mum, 622 Mbit/s, asynchronous transfer mode, asynchronous transfer mode, shared memory systems, buffer storage, CMOS technology, CMOS digital integrated circuits, B-ISDN, B-ISDN, switching circuits, parallel access |
73 | Cheng-Shang Chang, Duan-Shin Lee, Ying-Ju Shih, Chao-Lin Yu |
Mailbox switch: a scalable two-stage switch architecture for conflict resolution of ordered packets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 56(1), pp. 136-149, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
72 | Hagit Attiya, David Hay, Isaac Keslassy |
Packet-mode emulation of output-queued switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2006: Proceedings of the 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Cambridge, Massachusetts, USA, July 30 - August 2, 2006, pp. 138-147, 2006, ACM, 1-59593-452-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
CIOQ switch, output-queued, packet-mode scheduling, switch emulation, packet switching, queuing delay |
72 | Hongbing Fan, Yu-Liang Wu |
Crossbar based design schemes for switch boxes and programmable interconnection networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 910-915, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
switch matrix, FPGA, routing, interconnection network, layout, crossbar, switch box |
70 | Hongbing Fan, Jiping Liu, Yu-Liang Wu |
General Models and a Reduction Design Technique for FPGA Switch Box Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(1), pp. 21-30, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
hyper-universal, FPGA, global routing, detailed routing, reduction technique, optimum design, switch box |
69 | Byoung-Seok Park, Sung-Chun Kim |
Design and Analysis of a New Fast Packet Switching Fabric Supporting Multimedia Traffic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: Proceedings 21st Conference on Local Computer Networks, Minneapolis, Minnesota, USA, October 13-16, 1996, pp. 48-53, 1996, IEEE Computer Society, 0-8186-7617-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
fast packet switching fabric, ATM switch architecture, output queueing, switch analysis, FAB Banyan switching fabrics, Batcher sorter, double shuffle network, packet distributors, FAB networks, output buffer modules, compressed video data, performance evaluation, throughput, packet switching, hardware implementation, voice, multimedia traffic, packet delay, switch design, packet loss probability, text data |
68 | Guang-Ming Wu, Yao-Wen Chang |
Switch-matrix architecture and routing for FPDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 1998 International Symposium on Physical Design, ISPD 1998, Monterey, CA, USA, April 6-8, 1998, pp. 158-163, 1998, ACM, 1-58113-021-X. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
68 | Parimal Patel, Saad Zahid |
Design Considerations in an ATM Switch Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCN ![In: Proceedings of the International Conference On Computer Communications and Networks (ICCCN 1998), October 12-15, 1998, Lafayette, Louisiana, USA, pp. 92-98, 1998, IEEE Computer Society, 0-8186-9014-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
ATM switch design, packet switching, ATM Switch, Switch architecture |
68 | Chao-Ju Hou, Ching-Chih Han, Wun-Chun Chau |
Priority-based high-speed switch scheduling for ATM networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: Proceedings 20th Conference on Local Computer Networks (LCN'95), Minneapolis, Minnesota, USA, October 16-19, 1995, pp. 19-28, 1995, IEEE Computer Society, 0-8186-7162-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
iterated switching networks, priority-based high-speed switch scheduling, AN2 switch, parallel iterative matching algorithm, maximal input-output matching, priority lists, input/output pairs, probability analysis, switch size, high QoS requirements, simulation, scheduling, parallel algorithms, computational complexity, asynchronous transfer mode, probability, local area networks, iterative methods, time complexity, ATM networks, iterations, switches, high-performance distributed computing |
67 | Jin Li, Chuan-lin Wu |
A novel architecture for an ATM switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 340-345, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
multicast function, shared-buffer ATM switch, first-in and first-out shared buffer, FIFO address queue, cell-loss performance, performance evaluation, asynchronous transfer mode, ATM switch, B-ISDN, control logic, buffer utilization |
65 | Abdel Ejnioui, N. Ranganathan |
Routing on Switch Matrix Multi-FPGA Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 248-253, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
switch routing, Field programmable arrays, Multi-FPGA systems, Global routing, FPGA architecture, Interconnection structure |
64 | Mingyao Yang, Lionel M. Ni |
Design of Scalable and Multicast Capable Cut-Through Switches for High-Speed LANs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 1997 International Conference on Parallel Processing (ICPP '97), August 11-15, 1997, Bloomington, IL, USA, Proceedings, pp. 324-499, 1997, IEEE Computer Society, 0-8186-8108-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Intra-switch interconnect, Switch packaging, Multicast, Deadlock-free routing, Switch architecture, Cut-through switching |
63 | Yao-Wen Chang, D. F. Wong 0001, C. K. Wong |
Universal switch modules for FPGA design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 1(1), pp. 80-101, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
62 | Jin Li |
An output-shared buffer ATM switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 147-148, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
buffer ATM switch, output-shared, lower bandwidth, asynchronous transfer mode, ATM switch, buffer utilization |
60 | Ron Gabor, Shlomo Weiss, Avi Mendelson |
Fairness enforcement in switch on event multithreading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 4(3), pp. 15, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
SOE, Switch on Event multithreading, coarse-grained multithreading, weighted speedup, performance, fairness, throughput, multithreading |
60 | Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. Panda 0001 |
Implementing Multidestination Worms in Switch-Based Parallel Systems: Architectural Alternatives and Their Impact. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 11(8), pp. 794-812, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
switch/router architecture, performance evaluation, multicast, interconnection networks, broadcast, collective communication, wormhole switching, Parallel computer architecture, cut-through switching |
59 | Hakyong Kim, Kiseon Kim |
Performance analysis of the multiple input-queued packet switch with the restricted rule. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 11(3), pp. 478-487, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Multiple input queueing (MIQ), free rule, restricted rule |
59 | Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung |
On optimal hyperuniversal and rearrangeable switch box designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(12), pp. 1637-1649, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
59 | Michael Shyu, Guang-Ming Wu, Yu-Dong Chang, Yao-Wen Chang |
Generic Universal Switch Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(4), pp. 348-359, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
design, architecture, Analysis, digital, programmable logic array, gate array |
57 | Hongbing Fan, Jiping Liu, Yu-Liang Wu, C. K. Wong |
Reduction design for generic universal switch blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(4), pp. 526-546, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
FPGA architecture design, routing requirement, switch module, universal switch block, routing, decomposition |
57 | Latha A. Kant, William H. Sanders |
Loss process analysis of the knockout switch using stochastic activity networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCN ![In: Proceedings of the 4th International Conference on Computer Communications and Networks (ICCCN '95), September 20-23, 1995, Las Vegas, Nevada, USA, pp. 344, 1995, IEEE Computer Society, 0-8186-7180-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
loss process analysis, knockout switch, fast packet switches, consecutive cell losses, tagged port, telecommunication switch design, quality of service, performance, asynchronous transfer mode, asynchronous transfer mode, Markov processes, ATM networks, bursty traffic, B-ISDN, stochastic activity networks, cell loss probability |
55 | Fang Liu, Fei Guo, Yan Solihin, Seongbeom Kim, Abdulaziz Eker |
Characterizing and modeling the behavior of context switch misses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 17th International Conference on Parallel Architectures and Compilation Techniques, PACT 2008, Toronto, Ontario, Canada, October 25-29, 2008, pp. 91-101, 2008, ACM, 978-1-60558-282-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
context switch misses, stack distance profiling, prefetching, analytical model |
55 | Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang 0011, Michael Orshansky |
Architecting a reliable CMP switch architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 4(1), pp. 2, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
CMP switch, reliability, defect-tolerance |
55 | Man Chi Chan, Tony T. Lee |
Statistical performance guarantees in large-scale cross-path packet switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 11(2), pp. 325-337, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
cross-path switch, exponential bounded burstiness (EBB) processes, path switching, semioptical network, statistical performance guarantees, token assignment algorithm, quality of service (QoS), clos network, service curves |
55 | Yao-Wen Chang, D. F. Wong 0001, C. K. Wong |
Design and analysis of FPGA/FPIC switch modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 394-401, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
FPGA/FPIC switch modules, routing resources, FPIC, network-flow techniques, field programmable interconnect chip, field programmable gate arrays, FPGA, field programmable gate arrays, logic design, heuristic algorithm, programmable logic arrays, routability |
54 | Minsik Ahn, Chang-Ho Lee, Joy Laskar |
CMOS High Power SPDT Switch using Multigate Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3283-3286, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
54 | Yao-Wen Chang, Kai Zhu 0001, Guang-Ming Wu, D. F. Wong 0001, C. K. Wong |
Analysis of FPGA/FPIC switch modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 8(1), pp. 11-37, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
FPIC, FPGA, synthesis, layout, Computer-aided design of VLSI |
54 | Herman Schmit, Vikas Chandra |
FPGA switch block layout and evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2002, Monterey, CA, USA, February 24-26, 2002, pp. 11-18, 2002, ACM, 1-58113-452-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
VLSI layout, FPGA interconnect |
53 | Robert R. Henry 0002 |
A multicast ATM switch with slotted ring fabric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCN ![In: Proceedings of the International Conference On Computer Communications and Networks (ICCCN 1997), September 22-25, 1997 Las Vegas, NV, USA, pp. 500-503, 1997, IEEE Computer Society, 0-8186-8186-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
multicast ATM switch, slotted ring fabric, slotted ring ATM switch architecture, optical fiber switch, deterministic performance analysis equations, delay performance, zero blocking performance, 150 Mbit/s, asynchronous transfer mode, switching fabric |
53 | Syed Sohel Hussain, Yih-Chyun Jenq |
Analysis and Optimization of a Banyan-Based ATM Switch by Simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: Proceedings 21st Conference on Local Computer Networks, Minneapolis, Minnesota, USA, October 13-16, 1996, pp. 268-277, 1996, IEEE Computer Society, 0-8186-7617-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Banyan based ATM switch, switch optimization, switch analysis, delay variance, performanc analysis, uniform traffic, three-state model, nonblocking first stage, packet blocking, enhanced priority scheme, single buffer Banyan network, double buffer switching element, delay sensitive voice packet, asynchronous transfer mode, asynchronous transfer mode, delay, throughput, bandwidth, simulation results, voice traffic, data traffic |
53 | Yao-Wen Chang, D. F. Wong 0001, C. K. Wong |
FPGA global routing based on a new congestion metric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 372-378, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
FPGA global routing, congestion metric, routing capacity, switch block, switch-block capacity, congestion-control metric, global router, channel densities, field programmable gate arrays, congestion control, logic design, programmable logic arrays, circuit layout CAD, graph modeling |
52 | Y. Chang, Nada Golmie, David H. Su |
Study of interoperability between EFCI and ER switch mechanisms for ABR traffic in an ATM network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCN ![In: Proceedings of the 4th International Conference on Computer Communications and Networks (ICCCN '95), September 20-23, 1995, Las Vegas, Nevada, USA, pp. 310, 1995, IEEE Computer Society, 0-8186-7180-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
ABR traffic, rate-based flow control, transmission rate control, feedback information, resource management cells, network switching nodes, ATM Forum Traffic Management Specification, network switch mechanism, ATM switch vendor, bandwidth allocation fairness, explicit forward congestion indication, explicit rate mechanism, end system behavior, congestion notification, algorithms, interoperability, asynchronous transfer mode, asynchronous transfer mode, ATM network, simulation results, network performance, simulation study, performance characteristics, available bit rate, destination nodes |
51 | Bin Wu 0002, Kwan L. Yeung, Mounir Hamdi, Xin Li 0028 |
Minimizing internal speedup for performance guaranteed switches with optical fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 17(2), pp. 632-645, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
optical switch fabric, performance guaranteed switching, reconfiguration overhead, scheduling, speedup |
51 | Daqing Xu, Hisao Kameda |
Friend Pointer Registration Strategy and Its Scheme for Mobile Location Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA Workshops (2) ![In: 21st International Conference on Advanced Information Networking and Applications (AINA 2007), Workshops Proceedings, Volume 2, May 21-23, 2007, Niagara Falls, Canada, pp. 225-230, 2007, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
mobile tracking, mobile locating, old switch, new switch, home switch, friend switch, friend pointer, friend node and neighborhood, FPRMP |
50 | Vincent W. S. Wong 0001, Mark E. Lewis, Victor C. M. Leung |
Stochastic control of path optimization for inter-switch handoffs in wireless ATM networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 9(3), pp. 336-350, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
connection rerouting, inter-switch bandoff, path optimization, wireless ATM |
50 | Rajeev Sivaram, Ram Kesavan, Dhabaleswar K. Panda 0001, Craig B. Stunkel |
Where to Provide Support for Efficient Multicasting in Irregular Networks: Network Interface or Switch? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 1998 International Conference on Parallel Processing (ICPP '98), 10-14 August 1998, Minneapolis, Minnesota, USA, Proceedings, pp. 452-459, 1998, IEEE Computer Society, 0-8186-8650-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
cut-through routing, performance evaluation, multicast, broadcast, collective communication, Parallel computer architecture, irregular networks, switch-based networks |
50 | Youngbok Choi, Hideki Tode, Hiromi Okada, Hiromasa Ikeda |
A Large Capacity Photonic ATM Switch for Wavelength Division Multiplexing Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCN ![In: Proceedings of the 4th International Conference on Computer Communications and Networks (ICCCN '95), September 20-23, 1995, Las Vegas, Nevada, USA, pp. 414, 1995, IEEE Computer Society, 0-8186-7180-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Electronic Control, WDM Optical Buffer, ATM Switching, WDM Optical Networks, Photonic Switch |
49 | Alexander Kesselman, Kirill Kogan, Michael Segal 0001 |
Best Effort and Priority Queuing Policies for Buffered Crossbar Switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIROCCO ![In: Structural Information and Communication Complexity, 15th International Colloquium, SIROCCO 2008, Villars-sur-Ollon, Switzerland, June 17-20, 2008, Proceedings, pp. 170-184, 2008, Springer, 978-3-540-69326-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
49 | Josef Giglmayr |
All-optical multi-layer switching architectures: (I) MxN-gon prism switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCN ![In: Proceedings of the International Conference On Computer Communications and Networks (ICCCN 1998), October 12-15, 1998, Lafayette, Louisiana, USA, pp. 502-515, 1998, IEEE Computer Society, 0-8186-9014-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Optical waveguide, 2x2-switch, directional coupler, Mach-Zehnder interferometer, cycle structure, logical switch architecture, physical switch, all-optical 3-D grid, grid size, mapping, connectivity, multi-layer |
49 | Chih-Hao Liu, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yarsun Hsua |
Multi-mode message passing switch networks applied for QC-LDPC decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 752-755, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
49 | Ron Gabor, Shlomo Weiss, Avi Mendelson |
Fairness and Throughput in Switch on Event Multithreading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 9-13 December 2006, Orlando, Florida, USA, pp. 149-160, 2006, IEEE Computer Society, 0-7695-2732-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
49 | Chia-Lung Liu, Woei Lin, Chin-Chi Wu |
Speedup Requirements for Output Queuing Emulation with a Sliding-Window Parallel Packet Switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science (4) ![In: Computational Science - ICCS 2006, 6th International Conference, Reading, UK, May 28-31, 2006, Proceedings, Part IV, pp. 49-56, 2006, Springer, 3-540-34385-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
49 | Ding-Jyh Tsaur, Hsuan-Kuei Cheng, Chia-Lung Liu, Woei Lin |
A Study of Matching Output Queueing with a 3D-VOQ Switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICOIN ![In: Information Networking, Advances in Data Communications and Wireless Networks, International Conference, ICOIN 2006, Sendai, Japan, January 16-19, 2006, Revised Selected Papers, pp. 429-439, 2006, Springer, 3-540-48563-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
output queueing emulation, 3D-VOQ, QoS, switching system |
49 | Donghyun Kim, Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo |
A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2369-2372, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
49 | Abhijit M. Lele, S. K. Nandy 0001 |
Architecture of Reconfigurable a Low Power Gigabit AT Switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 242-247, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
49 | Terry Bearly, Jagan P. Agrawal |
A split input sunshine switch architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPCCC ![In: Proceedings of the IEEE International Performance Computing and Communications Conference, IPCCC 1999, Phoenix/Scottsdale, Arizona, USA, 10-12 February 1999, pp. 349-355, 1999, IEEE, 0-7803-5258-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
49 | Jin Li, Chuan-lin Wu |
Design and implementation of a multicast-buffer ATM switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNP ![In: 1995 International Conference on Network Protocols, ICNP 1995, November 7-10, 1995, Tokyo, Japan, pp. 84-91, 1995, IEEE Computer Society, 0-8186-7216-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
48 | Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi |
Using the inter- and intra-switch regularity in NoC switch testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 361-366, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
48 | Eiji Oki, Zhigang Jing, Roberto Rojas-Cessa, H. Jonathan Chao |
Concurrent round-robin-based dispatching schemes for Clos-network switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 10(6), pp. 830-844, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Clos-network switch, throughput, packet switch, arbitration, dispatching |
48 | Byoung Seob Park, Sung Chun Kim |
FBSF: a new fast packet switching fabric based-on multistage interconnection network with multiple outlets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), June 12-14, 1996, Beijing, China, pp. 320-325, 1996, IEEE Computer Society, 0-8186-7460-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
packet switching fabric, FBSF, multiple outlets, ATM switch architecture, FAB Banyan Switching Fabrics, Batcher sorter, radix-r double shuffle network, r-packet distributors, parallel architectures, packet switching, multistage interconnection networks, multistage interconnection network, switch fabrics |
48 | Nabanita Das 0001, Jayasree Dattagupta |
A fault location technique and alternate routing in Benes network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 71-, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
fault location technique, single switch fault, recirculation, source-destination path, routing technique, exact locations, multiple switch fault detection, one bit test vectors, equivalent fault set, fault diagnosis, fault tolerant computing, reconfiguration, reconfigurable architectures, multistage interconnection networks, multistage interconnection networks, network routing, Benes network, rearrangeable network, alternate routing |
47 | Steven E. Butner, David A. Skirmont |
Architecture and design of a 40 gigabit per second ATM switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 352-357, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
ATM links, buffering scheme, 40 Gbit/s, asynchronous transfer mode, multiprocessor interconnection networks, optical interconnections, ATM switch, optical communication, switch architecture |
46 | Rajeev Sivaram, Ram Kesavan, Dhabaleswar K. Panda 0001, Craig B. Stunkel |
Architectural Support for Efficient Multicasting in Irregular Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 12(5), pp. 489-513, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
cut-through routing, performance evaluation, multicast, broadcast, collective communication, Parallel computer architecture, irregular networks, switch-based networks |
45 | Gaspar Mora, José Flich, José Duato, Pedro López 0001, Elvira Baydal, Olav Lysne |
Towards an efficient switch architecture for high-radix switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANCS ![In: Proceedings of the 2006 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2006, San Jose, California, USA, December 3-5, 2006, pp. 11-20, 2006, ACM, 1-59593-580-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
arbiter efficiency, partitioned crossbar, switch organization |
45 | Hongbing Fan, Yu-Liang Wu, Chak-Chung Cheung, Jiping Liu |
On Optimal Irregular Switch Box Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 189-199, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA, Configurable computing, on-chip network, switch box |
45 | Ali Reza Ejlali, Seyed Ghassem Miremadi |
Switch-level emulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 644-649, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
FPGA chips, gate-level models, emulation, switch-level models |
45 | Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. Panda 0001 |
HIPIQS: A High-Performance Switch Architecture Using Input Queuing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 13(3), pp. 275-289, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
switch/router design, interconnection networks, parallel architectures, networks of workstations, high-speed interconnects |
45 | Ram Kesavan, Dhabaleswar K. Panda 0001 |
Efficient Multicast on Irregular Switch-Based Cut-Through Networks with Up-Down Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 12(8), pp. 808-828, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
cut-through routing, multicast, broadcast, wormhole routing, collective communication, networks of workstations, Parallel computer architecture, irregular networks, switch-based networks |
45 | Joseph Kee-Yin Ng, Shibin Song, Wei Zhao 0001 |
Integrated delay analysis of regulated ATM switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 18th IEEE Real-Time Systems Symposium (RTSS '97), December 3-5, 1997, San Francisco, CA, USA, pp. 285-296, 1997, IEEE Computer Society, 0-8186-8268-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
integrated delay analysis, regulated ATM switch, worst case delay, hard real-time connection, real-time connection traffic, arrival functions, priority driven scheduling, FIFO scheduling, admission probability, cell delay estimation, performance, asynchronous transfer mode, deadline, simulation experiments, service functions, piecewise linear functions |
45 | Michael Jurczyk |
Performance and Implementation Aspects of Higher Order Head-of-Line Blocking Switch Boxes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 1997 International Conference on Parallel Processing (ICPP '97), August 11-15, 1997, Bloomington, IL, USA, Proceedings, pp. 49-55, 1997, IEEE Computer Society, 0-8186-8108-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
central memory buffering, higher order blocking effects, multistage cube network, nonuniform traffic patterns, switch box implementation |
44 | Cheng-Shang Chang, Jay Cheng, Duan-Shin Lee, Chi-Feung Wu |
Quasi-Output-Buffered Switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INFOCOM ![In: INFOCOM 2008. 27th IEEE International Conference on Computer Communications, Joint Conference of the IEEE Computer and Communications Societies, 13-18 April 2008, Phoenix, AZ, USA, pp. 306-310, 2008, IEEE, 978-1-4244-2026-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
44 | Aditya Dua, Benjamin Yolken, Nicholas Bambos |
Power Managed Packet Switching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICC ![In: Proceedings of IEEE International Conference on Communications, ICC 2007, Glasgow, Scotland, UK, 24-28 June 2007, pp. 357-362, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
44 | Ching-Te Chiu, Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu |
A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2754-2757, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
44 | Herman Schmit, Vikas Chandra |
Layout techniques for FPGA switch blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(1), pp. 96-105, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
44 | Ching-Te Chiu, Chun-Chieh Chang, Shih-Min Chen, Hou-Cheng Tzeng, Ming-Chang Du, Yu-Ho Hsu, Jen-Ming Wu, Kai-Ming Feng |
A 20 Gbps Scalable Load-Balanced TDM Switch with CODEC for High Speed Networking Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 508-513, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
44 | Satyen Sukhtankar, Diana Hecht, Warren Rosen |
A Novel Switch Architecture for High-Performance Computing and Signal Processing Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NCA ![In: 3rd IEEE International Symposium on Network Computing and Applications (NCA 2004), 30 August - 1 September 2004, Cambridge, MA, USA, pp. 215-222, 2004, IEEE Computer Society, 0-7695-2242-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
44 | Gagan Aggarwal, Rajeev Motwani 0001, Devavrat Shah, An Zhu |
Switch Scheduling via Randomized Edge Coloring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 44th Symposium on Foundations of Computer Science (FOCS 2003), 11-14 October 2003, Cambridge, MA, USA, Proceedings, pp. 502-512, 2003, IEEE Computer Society, 0-7695-2040-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
44 | Seyed Ghassem Miremadi, Ali Reza Ejlali |
Switch Level Fault Emulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 849-858, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
44 | Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung |
On Optimum Designs of Universal Switch Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 142-151, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
44 | Tamaree Nalin, Isobe Takashi, Hiroaki Morino, Hitoshi Aida, Tadao Saito |
A Scalable and High Capacity Router on Multi-Dimension Crossbar Switch Principle. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: 26th Annual IEEE Conference on Local Computer Networks (LCN 2001), 14-16 November 2001, Tampa, Florida, USA, Proceedings, pp. 375-376, 2001, IEEE Computer Society, 0-7695-1321-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
44 | Thai Thach Bao, Hiroaki Morino, Hitoshi Aida, Tadao Saito |
Distributed Input and Deflection Routing Based Packet Switch Using Shuffle Pattern Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NETWORKING ![In: NETWORKING 2000, Broadband Communications, High Performance Networking, and Performance of Communication Networks, IFIP-TC6 / European Commission International Conference, Paris, France, May 14-19, 2000, Proceedings, pp. 74-84, 2000, Springer, 3-540-67506-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
44 | Shinichiro Mutoh, Satoshi Shigematsu, Yoshinori Gotoh, Shinsuke Konaka |
Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 113-116, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
44 | Craig B. Stunkel, Rajeev Sivaram, Dhabaleswar K. Panda 0001 |
Implementing Multidestination Worms in Switch-Based Parallel Systems: Architectural Alternatives and their Impact. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 24th International Symposium on Computer Architecture, Denver, Colorado, USA, June 2-4, 1997, pp. 50-61, 1997, ACM, 0-89791-901-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
43 | Xiaoliang Wang 0001, Xiaohong Jiang 0001, Susumu Horiguchi |
CBX-1 Switch: An Effective Load Balanced Switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDCAT ![In: Eighth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2007), 3-6 December 2007, Adelaide, Australia, pp. 391-397, 2007, IEEE Computer Society, 0-7695-3049-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Erol Basturk, Alexander Birman, G. Delp, Roch Guérin, R. Haas, Sanjay Kamat, Dilip D. Kandlur, P. Pan, Dimitrios E. Pendarakis, Vinod G. J. Peris, Raju Rajan, Debanjan Saha, Doug Williams |
Design and implementation of a QoS capable switch-router. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCN ![In: Proceedings of the International Conference On Computer Communications and Networks (ICCCN 1997), September 22-25, 1997 Las Vegas, NV, USA, pp. 276-284, 1997, IEEE Computer Society, 0-8186-8186-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
QoS capable switch-router, core ATM switch fabric, intelligent adapters, RSVP signalling, prototype network, UNIX hosts, network performance measurements, Internet, Internet, design, architecture, resource management, implementation, service differentiation, high throughput, IETF, control engine |
42 | Wilbert H. F. J. Körver |
A universal formalization of the effects of threshold voltages for discrete switch-level circuit models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 266-, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
field effect transistor switches, threshold voltage effects, discrete switch-level circuit models, universal formalization, switch imperfection, CMOS design, demolition degree, CMOS digital integrated circuits, state transitions, integrated circuit modelling, switching circuits |
41 | Isaac Keslassy, Murali S. Kodialam, T. V. Lakshman, Dimitrios Stiliadis |
On guaranteed smooth scheduling for input-queued switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 13(6), pp. 1364-1375, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
scheduling, router, switch, jitter |
41 | Laxmi N. Bhuyan, Ravi R. Iyer 0001, Hu-Jun Wang, Akhilesh Kumar |
Impact of CC-NUMA Memory Management Policies on the Application Performance of Multistage Switching Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 11(3), pp. 230-246, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Memory management, shared-memory multiprocessor, wormhole routing, scientific applications, execution-driven simulation, switch design |
40 | Chuanpeng Li, Chen Ding 0001, Kai Shen |
Quantifying the cost of context switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Experimental Computer Science ![In: Proceedings of the Workshop on Experimental Computer Science, Part of ACM FCRC, San Diego, CA, USA, 13-14 June 2007, pp. 2, 2007, ACM, 978-1-59593-751-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
context switch, cache interference |
40 | Wenjie Li, Bin Liu 0001, Yang Xu 0010, Heng Liao |
Parallel Switch System with QoS Guarantee for Real-Time Traffic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 21(6), pp. 1012-1021, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
QoS, load-balancing, parallel, priority, switch system |
40 | Simon Jolly, Atanas N. Parashkevov, Tim McDougall |
Automated equivalence checking of switch level circuits . ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 299-304, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
MOS circuits, custom design, switch level analysis, formal verification, VLSI design, equivalence checking |
40 | Marius Pirvu, Nan Ni, Laxmi N. Bhuyan |
Exploring the Switch Design Space in a CC-NUMA Multiprocessor Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), Cancun, Mexico, May 1-5, 2000, pp. 703-710, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
input buffer management, CC-NUMA multiprocessors, performance evaluation, arbitration, execution driven simulation, switch design |
40 | Chris Plate, Jack Tan |
Performance Analysis of a Fault-Tolerant B-Tree ATM Switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: Proceedings 21st Conference on Local Computer Networks, Minneapolis, Minnesota, USA, October 13-16, 1996, pp. 295-304, 1996, IEEE Computer Society, 0-8186-7617-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
fault-tolerant B-tree ATM switch, ATM switching fabrics, buffering methods, simulation, performance analysis, asynchronous transfer mode, asynchronous transfer mode, routing algorithm, ATM networks, traffic models, multiplexing, real-time traffic, computer industry, telecommunications industry, data packets |
40 | Gee-Swee Poo, Yinzhu Zhou |
A, new multicast wavelength assignment algorithm in wavelength-routed WDM networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Sel. Areas Commun. ![In: IEEE J. Sel. Areas Commun. 24(S-4), pp. 2-12, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Hongyun Zheng, Yongxiang Zhao, Changjia Chen |
Design and Implementation of Switches in Network Simulator (ns2). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICIC (1) ![In: First International Conference on Innovative Computing, Information and Control (ICICIC 2006), 30 August - 1 September 2006, Beijing, China, pp. 721-724, 2006, IEEE Computer Society, 0-7695-2616-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Xiaoming Liu 0003, Robbert van Renesse |
Fast protocol transition in a distributed environment (brief announcement). ![Search on Bibsonomy](Pics/bibsonomy.png) |
PODC ![In: Proceedings of the Nineteenth Annual ACM Symposium on Principles of Distributed Computing, July 16-19, 2000, Portland, Oregon, USA., pp. 341, 2000, ACM, 1-58113-183-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
39 | Qixin Wang, Sathish Gopalakrishnan, Xue Liu 0001, Lui Sha |
A Switch Design for Real-Time Industrial Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real-Time and Embedded Technology and Applications Symposium ![In: Proceedings of the 14th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2008, April 22-24, 2008, St. Louis, Missouri, USA, pp. 367-376, 2008, IEEE Computer Society, 978-0-7695-3146-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Hoa Le Minh, Fary Ghassemlooy, Wai Pang Ng |
An Ultrafast with High Contrast Ratio 12 All-optical Switch based on Tri-arm Mach-Zehnder employing All-optical Flip-flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICC ![In: Proceedings of IEEE International Conference on Communications, ICC 2007, Glasgow, Scotland, UK, 24-28 June 2007, pp. 2257-2262, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
39 | Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew |
Soft Error Mitigation in Switch Modules of SRAM-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 141-144, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
39 | David Marche, Yves Gagnon, Yvon Savaria |
. A new switch compensation technique for inverted R-2R ladder DACs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 196-199, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
39 | Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi |
Probabilistic Analysis of Fault Tolerance of FPGA Switch Block Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
fault tolerance, FPGA, routing, testing |
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