Search results for "switch-level"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
60	Ali Reza Ejlali, Seyed Ghassem Miremadi	Switch-level emulation.	DAC	2003	DBLP DOI BibTeX RDF	FPGA chips, gate-level models, emulation, switch-level models
59	Seyed Ghassem Miremadi, Ali Reza Ejlali	Switch Level Fault Emulation.	FPL	2003	DBLP DOI BibTeX RDF
58	Peter Lidén, Peter Dahlgren	Switch-level modeling of transistor-level stuck-at faults.	VTS	1995	DBLP DOI BibTeX RDF	transistor-level stuck-at faults, switch-level algorithms, fault modeling capability, fault detection measures, confidence degradation, unknown output values, uncertainty quantification, node model, fault diagnosis, logic testing, integrated circuit testing, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, switch-level modeling
54	Simon Jolly, Atanas N. Parashkevov, Tim McDougall	Automated equivalence checking of switch level circuits .	DAC	2002	DBLP DOI BibTeX RDF	MOS circuits, custom design, switch level analysis, formal verification, VLSI design, equivalence checking
45	Magdy S. Abadir, Jing Zeng, Carol Pyron, Juhong Zhu	Automated Test Model Generation from Switch Level Custom Circuits.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
45	Christopher A. Ryan, Joseph G. Tront	FX: a fast approximate fault simulator for the switch-level using VHDL.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
44	Kent L. Einspahr, Sharad C. Seth	A switch-level test generation system for synchronous and asynchronous circuits.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	reverse time processing, stuck-open and stuck-at faults, time-frame expansion, sequential circuits, Automatic test generation
43	Wilbert H. F. J. Körver	A universal formalization of the effects of threshold voltages for discrete switch-level circuit models.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	field effect transistor switches, threshold voltage effects, discrete switch-level circuit models, universal formalization, switch imperfection, CMOS design, demolition degree, CMOS digital integrated circuits, state transitions, integrated circuit modelling, switching circuits
39	Lawrence P. Huang, Randal E. Bryant	Intractability in linear switch-level simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
39	Peter Dahlgren, Peter Lidén	A fault model for switch-level simulation of gate-to-drain shorts.	VTS	1996	DBLP DOI BibTeX RDF	switch-level simulation, gate-to-drain shorts, transistor-level bridging faults, network primitive, electrical-level analysis, algorithm, fault diagnosis, fault model, iteration, integrated circuit modelling, subnetworks
38	Wolfgang Meyer 0002, Raul Camposano	Active timing multilevel fault-simulation with switch-level accuracy.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
37	Rochit Rajsuman, Yashwant K. Malaiya, Anura P. Jayasumana	On Accuracy of Switch-Level Modeling of Bridging Faults in Complex Gates.	DAC	1987	DBLP DOI BibTeX RDF
37	Lluís Ribas, Jordi Carrabina	On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits.	DATE	1998	DBLP DOI BibTeX RDF	incremental simulation, switch-level circuit analysis, symbolic circuit traversal
37	V. Ashok, Roger L. Costello, P. Sadayappan	Modeling switch-level simulation using data flow.	DAC	1985	DBLP DOI BibTeX RDF	data-driven computation, switch-level simulation, distributed processing, data-flow
34	Reiner Hähnle, Werner Kernig	Verification of Switch-Level Designs with Many-Valued Logic.	LPAR	1993	DBLP DOI BibTeX RDF
33	Rochit Rajsuman, Yashwant K. Malaiya, Anura P. Jayasumana	Limitations of switch level analysis for bridging faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
32	Venkatram Krishnaswamy, Jeremy Casas, Thomas Tetzlaff	A switch level fault simulation environment.	DAC	2000	DBLP DOI BibTeX RDF
32	Teresa Nachiondo Frinós, José Flich, José Duato	Efficient Reduction of HOL Blocking in Multistage Networks.	IPDPS	2005	DBLP DOI BibTeX RDF
31	Salvador Mir, Adoración Rueda, Diego Vázquez, José Luis Huertas	Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems.	DATE	1998	DBLP DOI BibTeX RDF
31	Peter Dahlgren	Switch-level bridging fault simulation in the presence of feedbacks.	ITC	1998	DBLP DOI BibTeX RDF
31	Andrew T. Yang, Yu-Hsu Chang, Daniel G. Saab, Ibrahim N. Hajj	Switch-level timing simulation of bipolar ECL circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
31	Eduard Cerny, John P. Hayes, Nicholas C. Rumin	Accuracy of magnitude-class calculations in switch-level modeling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
31	Chun-Hung Chen, Jacob A. Abraham	Generation and evaluation of current and logic tests for switch-level sequential circuits.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	logic tests, test generation, Current tests, I DDQ
31	Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar	Massively parallel switch-level simulation: a feasibility study.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
31	Prathima Agrawal, Scott H. Robinson, Thomas G. Szymanski	Automatic modeling of switch-level networks using partial orders [MOS circuits].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
31	Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar	Massively Parallel Switch-Level Simulation: A Feasibility Study.	DAC	1989	DBLP DOI BibTeX RDF
31	Christer Svensson, Robert Tjärnström	Switch-level simulation and the pass transistor EXOR gate.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
31	Radu Negulescu	Event-Driven Verification of Switch-Level Correctness Concerns.	ACSD	1998	DBLP DOI BibTeX RDF	switch-level, Verification, concurrency, safety, deadlock, asynchronous, event-driven, speed-independence, process spaces
31	Peter Dahlgren	Switch-level modeling of feedback faults using global oscillation control.	VTS	1997	DBLP DOI BibTeX RDF	global oscillation control, asynchronous behavior, fault diagnosis, fault diagnosis, bridging fault, logic simulation, feedback loop, switch-level model
31	Randal E. Bryant	A Switch-Level Model and Simulator for MOS Digital Systems.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	MOS logic simulation, VLSI, switch-level model
30	Dan Adler	Switch-level simulation using dynamic graph algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
29	Lluís Ribas, Jordi Carrabina	Digital MOS Circuit Partitioning with Symbolic Modeling.	DATE	1999	DBLP DOI BibTeX RDF	switch-level circuit analysis, symbolic circuit traversal, circuit partitioning, symbolic modeling
29	Genhong Ruan, Jirí Vlach, James A. Barby	Current-limited switch-level timing simulator for MOS logic networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
27	Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer	SWiTEST: a switch level test generation system for CMOS combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
27	Gaspar Mora, José Flich, José Duato, Pedro López 0001, Elvira Baydal, Olav Lysne	Towards an efficient switch architecture for high-radix switches.	ANCS	2006	DBLP DOI BibTeX RDF	arbiter efficiency, partitioned crossbar, switch organization
26	Larry G. Jones	An incremental zero/integer delay switch-level simulation environment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
26	Latha A. Kant, William H. Sanders	Loss process analysis of the knockout switch using stochastic activity networks.	ICCCN	1995	DBLP DOI BibTeX RDF	loss process analysis, knockout switch, fast packet switches, consecutive cell losses, tagged port, telecommunication switch design, quality of service, performance, asynchronous transfer mode, asynchronous transfer mode, Markov processes, ATM networks, bursty traffic, B-ISDN, stochastic activity networks, cell loss probability
25	Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham	Towards The Complete Elimination of Gate/Switch Level Simulations.	VLSI Design	2004	DBLP DOI BibTeX RDF
25	Yuan Chen, Vikas Jha, Rajive L. Bagrodia	A Multidimensional Study on the Feasibility of Parallel Switch-Level Circuit Simulation.	Workshop on Parallel and Distributed Simulation	1997	DBLP DOI BibTeX RDF
25	Larry G. Jones, David T. Blaauw	A cache-based method for accelerating switch-level simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
25	H. Warmers, D. Sass, Ernst-Helmut Horneber	Switch-level timing models in the MOS simulator BRASIL.	EURO-DAC	1990	DBLP DOI BibTeX RDF
25	David T. Blaauw, Daniel G. Saab, Junsheng Long, Jacob A. Abraham	Derivation of signal flow for switch-level simulation.	EURO-DAC	1990	DBLP DOI BibTeX RDF
25	Carles Ferrer 0001, Joan Oliver, Elena Valderrama	A new switch-level test pattern generation algorithm based on single path over a graph representation.	EURO-DAC	1990	DBLP DOI BibTeX RDF
25	Edward H. Frank	Exploiting parallelism in a switch-level simulation machine.	DAC	1986	DBLP DOI BibTeX RDF
25	Seung Ho Hwang, Young Hwan Kim, A. Richard Newton	An accuration delay modeling technique for switch-level timing verification.	DAC	1986	DBLP DOI BibTeX RDF
24	Sasha Novakovsky, Shy Shyman, Ziyad Hanna	High capacity and automatic functional extraction tool for industrial VLSI circuit designs.	ICCAD	2002	DBLP DOI BibTeX RDF	Formal Equivalence Verification (FEV), Hardware Description Languages (HDL), Switch Level Analysis, functional abstraction, satisfiability procedures, synthesis, Design For Testability (DFT), logic simulation, Binary Decision Diagrams (BDDs)
24	Chung Len Lee 0001, Ching Ping Wu, Wen-Zen Shen, Tyh-Song Hwang, Shueng Dar Hwang	MT-SIM a mixed-level transition fault simulator based on parallel patterns.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	mixed-level, parallel pattern, Fault simulation, transition fault
24	Dan Adler	A Dynamically-Directed Switch Model for MOS Logic Simulation.	DAC	1988	DBLP BibTeX RDF
23	Marly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri	CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder.	ASYNC	2000	DBLP DOI BibTeX RDF	pulse logic, switch-level fault simulation, Cellular Automata, BIST, asynchronous circuits, testability, stuck-at faults, domino logic, self-timed circuits, dynamic circuits
23	Pranav Ashar, Sharad Malik	Fast functional simulation using branching programs.	ICCAD	1995	DBLP DOI BibTeX RDF	compiled code simulation, cycle-based functional simulation, fast functional simulation, functional delay-independent logic simulation, levelized compiled-code, switch level functional simulation, synchronous digital systems, Boolean functions, system design, logic design, logic CAD, decision theory, circuit analysis computing, benchmark circuits, branching programs
22	Mou Hu, Kenneth C. Smith	Application of Multiple-Valued Switch-Level Algebra to the Design and Analysis of Pass-Transistor Switch Networks.	ISMVL	1990	DBLP DOI BibTeX RDF
22	Dan Adler	SIMMOS: a multiple-delay switch-level simulator.	DAC	1986	DBLP DOI BibTeX RDF
21	Peter Dahlgren	A multiple-dominance switch-level model for simulation of short faults.	ICCAD	1995	DBLP DOI BibTeX RDF	intermediate logic values, Fault simulation, Logic simulation
20	Clayton B. McDonald, Randal E. Bryant	CMOS circuit verification with symbolic switch-level timingsimulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
20	Salvador Mir, Adoración Rueda, Thomas Olbrich, Eduardo J. Peralías, José Luis Huertas	SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems.	DAC	1997	DBLP DOI BibTeX RDF
20	David T. Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh	Automatic Generation of Behavioral Models from Switch-Level Descriptions.	DAC	1989	DBLP DOI BibTeX RDF
20	Randal E. Bryant, Michael Dd. Schuster	Performance evaluation of FMOSSIM, a concurrent switch-level fault simulator.	DAC	1985	DBLP DOI BibTeX RDF
19	Peter C. Maxwell, Jeff Rearick	Estimation of defect-free IDDQ in submicron circuits using switch level simulation.	ITC	1998	DBLP DOI BibTeX RDF
19	Randal E. Bryant	Formal verification of memory circuits by switch-level simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
19	Robert B. Mueller-Thuns, Daniel G. Saab, Jacob A. Abraham	Design of a scalable parallel switch-level simulator for VLSI.	SC	1990	DBLP DOI BibTeX RDF
19	Bharat L. Bhuva, John J. Paulos, Ronald S. Gyurcsik, Sherra E. Kerns	Switch-level simulation of total dose effects on CMOS VLSI circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
19	A. Salz, Mark Horowitz	IRSIM: An Incremental MOS Switch-Level Simulator.	DAC	1989	DBLP DOI BibTeX RDF
19	Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman	SLS-a fast switch-level simulator [for MOS].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
19	M. T. Smith	A Hardware Switch Level Simulator for Large MOS Circuits.	DAC	1987	DBLP DOI BibTeX RDF
19	Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman	SLS - a fast switch level simulator for verification and fault coverage analysis.	DAC	1986	DBLP DOI BibTeX RDF
19	Edward H. Frank	Switch-level simulation of VLSI using a special-purpose data-driven computer.	DAC	1985	DBLP DOI BibTeX RDF
18	Jeremy Casas, Hannah Honghua Yang, Manpreet Khaira, Mandar Joshi, Thomas Tetzlaff, Steve W. Otto, Erik Seligman	Logic Verification of Very Large Circuits Using Shark.	VLSI Design	1999	DBLP DOI BibTeX RDF
18	Russell Kao, Mark Horowitz	Timing analysis for piecewise linear Rsim.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
18	Kyeongsoon Cho, Randal E. Bryant	Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation.	DAC	1989	DBLP DOI BibTeX RDF
18	Soumitra Bose	Modeling Custom Digital Circuits for Test.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	ATPG, fault simulation, logic simulation, switch-level modeling
18	Christoph Kern, Tarik Ono-Tesfaye, Mark R. Greenstreet	A light-weight framework for hardware verification.	Int. J. Softw. Tools Technol. Transf.	2001	DBLP DOI BibTeX RDF	Refinement, Theorem-proving, Timing verification, Switch-level models, SRT division
18	K. J. Singh, P. A. Subrahmanyam	Extracting RTL models from transistor netlists.	ICCAD	1995	DBLP DOI BibTeX RDF	Switch-level simulation, Formal verification, Extraction, RTL model
18	Jyh-Charn Liu, Kang G. Shin	Polynomial Testing of Packet Switching Networks.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	polynomial testing, multiple stuck-at fault model, functional testing method, network level, switch level, network-level testing, built-in tester, multiprocessor interconnection networks, packet switching, multiprocessor systems, automatic testing, polynomials, multistage interconnection networks, packet switching networks, routing dynamic
18	Eduard Cerny, Jan Gecsei	Functional Description of Connector-Switch-Attenuator Networks.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	connector-switch-attenuator networks, switch-level abstraction, digital MOS circuits, functional description, electron device testing, formal verification, logic testing, failure analysis, switching networks, characteristic functions, field effect integrated circuits
18	John P. Hayes	Uncertainty, Energy, and Multiple-Valued Logics.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	unknown values, pseudo- Boolean algebra, switch-level simulation, multiple-valued logic, Logic simulation, switching theory
17	Wolfgang Meyer 0002, Raul Camposano	Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy.	DAC	1993	DBLP DOI BibTeX RDF
17	Terry Lee, Ibrahim N. Hajj	A Switch-Level Matrix Approach to Transistor-Level Fault Simulation.	ICCAD	1991	DBLP DOI BibTeX RDF
17	Alok Jain, Randal E. Bryant	Mapping Switch-Level Simulation onto Gate-Level Hardware Accelerators.	DAC	1991	DBLP DOI BibTeX RDF
17	Uwe Gläser, Heinrich Theodor Vierhaus	Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
17	Boris Nechaev, Vern Paxson, Mark Allman, Andrei V. Gurtov	On calibrating enterprise switch measurements.	Internet Measurement Conference	2009	DBLP DOI BibTeX RDF	network traces, switch-based packet capture, trace calibration, enterprise networks
16	József Sziray	Test Calculation for Logic and Delay Faults in Digital Circuits.	MTV	2006	DBLP DOI BibTeX RDF	Test-pattern calculation, logic faults, CMOS transistor structures, functional testing, delay faults, multi-valued logic
16	Tyh-Song Hwang, Chung Len Lee 0001, Wen-Zen Shen, Ching Ping Wu	A Parallel Pattern Mixed-Level Fault Simulator.	DAC	1990	DBLP DOI BibTeX RDF
14	Uwe Hübner, Heinrich Theodor Vierhaus, Raul Camposano	Partitioning and analysis of static digital CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
14	Peter Odryna, Kevin Nazareth, Carl Christensen	A workstation-mixed model circuit simulator.	DAC	1986	DBLP DOI BibTeX RDF
13	Eric Schneider, Hans-Joachim Wunderlich	Switch Level Time Simulation of CMOS Circuits with Adaptive Voltage and Frequency Scaling.	VTS	2020	DBLP DOI BibTeX RDF
13	Eric Schneider, Hans-Joachim Wunderlich	SWIFT: Switch-Level Fault Simulation on GPUs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2019	DBLP DOI BibTeX RDF
13	Po-Yao Chuang, Cheng-Wen Wu, Harry H. Chen	Cell-aware test generation time reduction by using switch-level ATPG.	ITC-Asia	2017	DBLP DOI BibTeX RDF
13	Harry H. Chen, Simon Y.-H. Chen, Po-Yao Chuang, Cheng-Wen Wu	Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation.	ATS	2016	DBLP DOI BibTeX RDF
13	John Sonchack, Adam J. Aviv, Eric Keller, Jonathan M. Smith	POSTER: OFX: Enabling OpenFlow Extensions for Switch-Level Security Applications.	CCS	2015	DBLP DOI BibTeX RDF
13	Michele Favalli, Marcello Dalpasso	Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits.	J. Electron. Test.	2014	DBLP DOI BibTeX RDF
13	Ming Zhang, Lijun Hang, Wenxi Yao, Zhengyu Lu, Leon M. Tolbert	A Novel Strategy for Three-Phase/Switch/Level (Vienna) Rectifier Under Severe Unbalanced Grids.	IEEE Trans. Ind. Electron.	2013	DBLP DOI BibTeX RDF
13	Angela Souto Vieites, Roberto R. Osorio	Architecture and Implementation of a Data Compression System at Switch-Level in ATA-over-Ethernet Storage Networks.	DSD	2013	DBLP DOI BibTeX RDF
13	Reza Sedaghat, M. Reza Javaheri, Prabhleen K. Kalkat, Jalal Mohammad Chikhe	Switch-level emulation of strength-base soft error detection.	Microelectron. Reliab.	2011	DBLP DOI BibTeX RDF
13	Reza Sedaghat, M. Reza Javaheri, Prabhleen K. Kalkat, Jalal Mohammad Chikhe	Switch-level soft error emulation for SET-induced pulses of variable strengths.	Microelectron. J.	2010	DBLP DOI BibTeX RDF
13	József Sziray	Switch-Level Test Calculation for CMOS Circuits.	MTV	2009	DBLP DOI BibTeX RDF
13	Leomar S. da Rosa Jr., Felipe Ribeiro Schneider, Renato P. Ribas, André Inácio Reis	Switch level optimization of digital CMOS gate networks.	ISQED	2009	DBLP DOI BibTeX RDF
13	Nesrine Bel Haj Youssef, Kamal Al-Haddad, Hadi Youssef Kanaan	Large-Signal Modeling and Steady-State Analysis of a 1.5-kW Three-Phase/Switch/Level (Vienna) Rectifier With Experimental Validation.	IEEE Trans. Ind. Electron.	2008	DBLP DOI BibTeX RDF
13	Nesrine Bel Haj Youssef, Kamal Al-Haddad, Hadi Youssef Kanaan	Real-Time Implementation of a Discrete Nonlinearity Compensating Multiloops Control Technique for a 1.5-kW Three-Phase/Switch/Level Vienna Converter.	IEEE Trans. Ind. Electron.	2008	DBLP DOI BibTeX RDF
13	Peter Ming-Han Lee, Reza Sedaghat	FPGA-based switch-level fault emulation using module-based dynamic partial reconfiguration.	Microelectron. Reliab.	2008	DBLP DOI BibTeX RDF
13	Joshua Lawrence, Xin Yuan 0001	An MPI tool for automatically discovering the switch level topologies of Ethernet clusters.	IPDPS	2008	DBLP DOI BibTeX RDF