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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 140 occurrences of 112 keywords
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Results
Found 235 publication records. Showing 235 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
60 | Ali Reza Ejlali, Seyed Ghassem Miremadi |
Switch-level emulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 644-649, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
FPGA chips, gate-level models, emulation, switch-level models |
59 | Seyed Ghassem Miremadi, Ali Reza Ejlali |
Switch Level Fault Emulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 849-858, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
58 | Peter Lidén, Peter Dahlgren |
Switch-level modeling of transistor-level stuck-at faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 208-215, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
transistor-level stuck-at faults, switch-level algorithms, fault modeling capability, fault detection measures, confidence degradation, unknown output values, uncertainty quantification, node model, fault diagnosis, logic testing, integrated circuit testing, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, switch-level modeling |
54 | Simon Jolly, Atanas N. Parashkevov, Tim McDougall |
Automated equivalence checking of switch level circuits . ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 299-304, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
MOS circuits, custom design, switch level analysis, formal verification, VLSI design, equivalence checking |
45 | Magdy S. Abadir, Jing Zeng, Carol Pyron, Juhong Zhu |
Automated Test Model Generation from Switch Level Custom Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 184-189, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
45 | Christopher A. Ryan, Joseph G. Tront |
FX: a fast approximate fault simulator for the switch-level using VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 4(3), pp. 336-345, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
44 | Kent L. Einspahr, Sharad C. Seth |
A switch-level test generation system for synchronous and asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(1), pp. 59-73, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
reverse time processing, stuck-open and stuck-at faults, time-frame expansion, sequential circuits, Automatic test generation |
43 | Wilbert H. F. J. Körver |
A universal formalization of the effects of threshold voltages for discrete switch-level circuit models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 266-, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
field effect transistor switches, threshold voltage effects, discrete switch-level circuit models, universal formalization, switch imperfection, CMOS design, demolition degree, CMOS digital integrated circuits, state transitions, integrated circuit modelling, switching circuits |
39 | Lawrence P. Huang, Randal E. Bryant |
Intractability in linear switch-level simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(6), pp. 829-836, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
39 | Peter Dahlgren, Peter Lidén |
A fault model for switch-level simulation of gate-to-drain shorts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 414-421, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
switch-level simulation, gate-to-drain shorts, transistor-level bridging faults, network primitive, electrical-level analysis, algorithm, fault diagnosis, fault model, iteration, integrated circuit modelling, subnetworks |
38 | Wolfgang Meyer 0002, Raul Camposano |
Active timing multilevel fault-simulation with switch-level accuracy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(10), pp. 1241-1256, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
37 | Rochit Rajsuman, Yashwant K. Malaiya, Anura P. Jayasumana |
On Accuracy of Switch-Level Modeling of Bridging Faults in Complex Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 244-250, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
37 | Lluís Ribas, Jordi Carrabina |
On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 624-629, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
incremental simulation, switch-level circuit analysis, symbolic circuit traversal |
37 | V. Ashok, Roger L. Costello, P. Sadayappan |
Modeling switch-level simulation using data flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 637-644, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
data-driven computation, switch-level simulation, distributed processing, data-flow |
34 | Reiner Hähnle, Werner Kernig |
Verification of Switch-Level Designs with Many-Valued Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LPAR ![In: Logic Programming and Automated Reasoning,4th International Conference, LPAR'93, St. Petersburg, Russia, July 13-20, 1993, Proceedings, pp. 158-169, 1993, Springer, 3-540-56944-8. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
33 | Rochit Rajsuman, Yashwant K. Malaiya, Anura P. Jayasumana |
Limitations of switch level analysis for bridging faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(7), pp. 807-811, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
32 | Venkatram Krishnaswamy, Jeremy Casas, Thomas Tetzlaff |
A switch level fault simulation environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 780-785, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
32 | Teresa Nachiondo Frinós, José Flich, José Duato |
Efficient Reduction of HOL Blocking in Multistage Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Salvador Mir, Adoración Rueda, Diego Vázquez, José Luis Huertas |
Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 810-814, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
31 | Peter Dahlgren |
Switch-level bridging fault simulation in the presence of feedbacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 363-371, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
31 | Andrew T. Yang, Yu-Hsu Chang, Daniel G. Saab, Ibrahim N. Hajj |
Switch-level timing simulation of bipolar ECL circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(4), pp. 516-530, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
31 | Eduard Cerny, John P. Hayes, Nicholas C. Rumin |
Accuracy of magnitude-class calculations in switch-level modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(4), pp. 443-452, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
31 | Chun-Hung Chen, Jacob A. Abraham |
Generation and evaluation of current and logic tests for switch-level sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(4), pp. 359-366, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
logic tests, test generation, Current tests, I DDQ |
31 | Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar |
Massively parallel switch-level simulation: a feasibility study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(7), pp. 871-894, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
31 | Prathima Agrawal, Scott H. Robinson, Thomas G. Szymanski |
Automatic modeling of switch-level networks using partial orders [MOS circuits]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(7), pp. 696-707, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
31 | Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar |
Massively Parallel Switch-Level Simulation: A Feasibility Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 91-97, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
31 | Christer Svensson, Robert Tjärnström |
Switch-level simulation and the pass transistor EXOR gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(9), pp. 994-997, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
31 | Radu Negulescu |
Event-Driven Verification of Switch-Level Correctness Concerns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 1st International Conference on Application of Concurrency to System Design (ACSD '98), 23-26 March 1998, Fukushima, Japan, pp. 213-223, 1998, IEEE Computer Society, 0-8186-8350-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
switch-level, Verification, concurrency, safety, deadlock, asynchronous, event-driven, speed-independence, process spaces |
31 | Peter Dahlgren |
Switch-level modeling of feedback faults using global oscillation control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 117-122, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
global oscillation control, asynchronous behavior, fault diagnosis, fault diagnosis, bridging fault, logic simulation, feedback loop, switch-level model |
31 | Randal E. Bryant |
A Switch-Level Model and Simulator for MOS Digital Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 33(2), pp. 160-177, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
MOS logic simulation, VLSI, switch-level model |
30 | Dan Adler |
Switch-level simulation using dynamic graph algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(3), pp. 346-355, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
29 | Lluís Ribas, Jordi Carrabina |
Digital MOS Circuit Partitioning with Symbolic Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 503-508, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
switch-level circuit analysis, symbolic circuit traversal, circuit partitioning, symbolic modeling |
29 | Genhong Ruan, Jirí Vlach, James A. Barby |
Current-limited switch-level timing simulator for MOS logic networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(6), pp. 659-667, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
27 | Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer |
SWiTEST: a switch level test generation system for CMOS combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(5), pp. 625-637, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
27 | Gaspar Mora, José Flich, José Duato, Pedro López 0001, Elvira Baydal, Olav Lysne |
Towards an efficient switch architecture for high-radix switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANCS ![In: Proceedings of the 2006 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2006, San Jose, California, USA, December 3-5, 2006, pp. 11-20, 2006, ACM, 1-59593-580-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
arbiter efficiency, partitioned crossbar, switch organization |
26 | Larry G. Jones |
An incremental zero/integer delay switch-level simulation environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(9), pp. 1131-1139, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
26 | Latha A. Kant, William H. Sanders |
Loss process analysis of the knockout switch using stochastic activity networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCN ![In: Proceedings of the 4th International Conference on Computer Communications and Networks (ICCCN '95), September 20-23, 1995, Las Vegas, Nevada, USA, pp. 344, 1995, IEEE Computer Society, 0-8186-7180-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
loss process analysis, knockout switch, fast packet switches, consecutive cell losses, tagged port, telecommunication switch design, quality of service, performance, asynchronous transfer mode, asynchronous transfer mode, Markov processes, ATM networks, bursty traffic, B-ISDN, stochastic activity networks, cell loss probability |
25 | Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham |
Towards The Complete Elimination of Gate/Switch Level Simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 115-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Yuan Chen, Vikas Jha, Rajive L. Bagrodia |
A Multidimensional Study on the Feasibility of Parallel Switch-Level Circuit Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Workshop on Parallel and Distributed Simulation ![In: Proceedings of the Eleventh Workshop on Parallel and Distributed Simulation, PADS '97, Lockenhaus, Austria, June 10-13, 1997, pp. 46-54, 1997, IEEE Computer Society, 0-8186-7965-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
25 | Larry G. Jones, David T. Blaauw |
A cache-based method for accelerating switch-level simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(2), pp. 211-218, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
25 | H. Warmers, D. Sass, Ernst-Helmut Horneber |
Switch-level timing models in the MOS simulator BRASIL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 568-572, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
25 | David T. Blaauw, Daniel G. Saab, Junsheng Long, Jacob A. Abraham |
Derivation of signal flow for switch-level simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 301-305, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
25 | Carles Ferrer 0001, Joan Oliver, Elena Valderrama |
A new switch-level test pattern generation algorithm based on single path over a graph representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 402-406, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
25 | Edward H. Frank |
Exploiting parallelism in a switch-level simulation machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 20-26, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
25 | Seung Ho Hwang, Young Hwan Kim, A. Richard Newton |
An accuration delay modeling technique for switch-level timing verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 227-233, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
24 | Sasha Novakovsky, Shy Shyman, Ziyad Hanna |
High capacity and automatic functional extraction tool for industrial VLSI circuit designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 520-525, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Formal Equivalence Verification (FEV), Hardware Description Languages (HDL), Switch Level Analysis, functional abstraction, satisfiability procedures, synthesis, Design For Testability (DFT), logic simulation, Binary Decision Diagrams (BDDs) |
24 | Chung Len Lee 0001, Ching Ping Wu, Wen-Zen Shen, Tyh-Song Hwang, Shueng Dar Hwang |
MT-SIM a mixed-level transition fault simulator based on parallel patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(1), pp. 67-78, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
mixed-level, parallel pattern, Fault simulation, transition fault |
24 | Dan Adler |
A Dynamically-Directed Switch Model for MOS Logic Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 506-511, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
23 | Marly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri |
CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 62-72, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
pulse logic, switch-level fault simulation, Cellular Automata, BIST, asynchronous circuits, testability, stuck-at faults, domino logic, self-timed circuits, dynamic circuits |
23 | Pranav Ashar, Sharad Malik |
Fast functional simulation using branching programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 408-412, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
compiled code simulation, cycle-based functional simulation, fast functional simulation, functional delay-independent logic simulation, levelized compiled-code, switch level functional simulation, synchronous digital systems, Boolean functions, system design, logic design, logic CAD, decision theory, circuit analysis computing, benchmark circuits, branching programs |
22 | Mou Hu, Kenneth C. Smith |
Application of Multiple-Valued Switch-Level Algebra to the Design and Analysis of Pass-Transistor Switch Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: Proceedings of the 20th International Symposium on Multiple-Valued Logic, ISMVL 1990, Charlotte, NC, USA, May 23-25, 1990, pp. 196-201, 1990, IEEE Computer Society, 0-8186-2046-3. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
22 | Dan Adler |
SIMMOS: a multiple-delay switch-level simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 159-163, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
21 | Peter Dahlgren |
A multiple-dominance switch-level model for simulation of short faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 674-680, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
intermediate logic values, Fault simulation, Logic simulation |
20 | Clayton B. McDonald, Randal E. Bryant |
CMOS circuit verification with symbolic switch-level timingsimulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(3), pp. 458-474, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
20 | Salvador Mir, Adoración Rueda, Thomas Olbrich, Eduardo J. Peralías, José Luis Huertas |
SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 281-286, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
20 | David T. Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh |
Automatic Generation of Behavioral Models from Switch-Level Descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 179-184, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
20 | Randal E. Bryant, Michael Dd. Schuster |
Performance evaluation of FMOSSIM, a concurrent switch-level fault simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 715-719, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
19 | Peter C. Maxwell, Jeff Rearick |
Estimation of defect-free IDDQ in submicron circuits using switch level simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 882-889, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Randal E. Bryant |
Formal verification of memory circuits by switch-level simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(1), pp. 94-102, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
19 | Robert B. Mueller-Thuns, Daniel G. Saab, Jacob A. Abraham |
Design of a scalable parallel switch-level simulator for VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings Supercomputing '90, New York, NY, USA, November 12-16, 1990, pp. 615-624, 1990, IEEE Computer Society, 0-89791-412-0. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
19 | Bharat L. Bhuva, John J. Paulos, Ronald S. Gyurcsik, Sherra E. Kerns |
Switch-level simulation of total dose effects on CMOS VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(9), pp. 933-938, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
19 | A. Salz, Mark Horowitz |
IRSIM: An Incremental MOS Switch-Level Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 173-178, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
19 | Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman |
SLS-a fast switch-level simulator [for MOS]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(8), pp. 838-849, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
19 | M. T. Smith |
A Hardware Switch Level Simulator for Large MOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 95-100, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
19 | Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman |
SLS - a fast switch level simulator for verification and fault coverage analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 164-170, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
19 | Edward H. Frank |
Switch-level simulation of VLSI using a special-purpose data-driven computer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 735-738, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
18 | Jeremy Casas, Hannah Honghua Yang, Manpreet Khaira, Mandar Joshi, Thomas Tetzlaff, Steve W. Otto, Erik Seligman |
Logic Verification of Very Large Circuits Using Shark. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 310-317, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Russell Kao, Mark Horowitz |
Timing analysis for piecewise linear Rsim. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(12), pp. 1498-1512, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
18 | Kyeongsoon Cho, Randal E. Bryant |
Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 418-423, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
18 | Soumitra Bose |
Modeling Custom Digital Circuits for Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(6), pp. 591-609, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ATPG, fault simulation, logic simulation, switch-level modeling |
18 | Christoph Kern, Tarik Ono-Tesfaye, Mark R. Greenstreet |
A light-weight framework for hardware verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 3(3), pp. 286-313, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Refinement, Theorem-proving, Timing verification, Switch-level models, SRT division |
18 | K. J. Singh, P. A. Subrahmanyam |
Extracting RTL models from transistor netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 11-17, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Switch-level simulation, Formal verification, Extraction, RTL model |
18 | Jyh-Charn Liu, Kang G. Shin |
Polynomial Testing of Packet Switching Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(2), pp. 202-217, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
polynomial testing, multiple stuck-at fault model, functional testing method, network level, switch level, network-level testing, built-in tester, multiprocessor interconnection networks, packet switching, multiprocessor systems, automatic testing, polynomials, multistage interconnection networks, packet switching networks, routing dynamic |
18 | Eduard Cerny, Jan Gecsei |
Functional Description of Connector-Switch-Attenuator Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(1), pp. 111-114, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
connector-switch-attenuator networks, switch-level abstraction, digital MOS circuits, functional description, electron device testing, formal verification, logic testing, failure analysis, switching networks, characteristic functions, field effect integrated circuits |
18 | John P. Hayes |
Uncertainty, Energy, and Multiple-Valued Logics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(2), pp. 107-114, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
unknown values, pseudo- Boolean algebra, switch-level simulation, multiple-valued logic, Logic simulation, switching theory |
17 | Wolfgang Meyer 0002, Raul Camposano |
Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 30th Design Automation Conference. Dallas, Texas, USA, June 14-18, 1993., pp. 515-519, 1993, ACM Press, 0-89791-577-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Terry Lee, Ibrahim N. Hajj |
A Switch-Level Matrix Approach to Transistor-Level Fault Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1991 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1993, Santa Clara, CA, USA, November 11-14, 1991. Digest of Technical Papers, pp. 554-557, 1991, IEEE Computer Society, 0-8186-2157-5. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
17 | Alok Jain, Randal E. Bryant |
Mapping Switch-Level Simulation onto Gate-Level Hardware Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 28th Design Automation Conference, San Francisco, California, USA, June 17-21, 1991., pp. 219-222, 1991, ACM, 0-89791395-7. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
17 | Uwe Gläser, Heinrich Theodor Vierhaus |
Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(4), pp. 410-423, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
17 | Boris Nechaev, Vern Paxson, Mark Allman, Andrei V. Gurtov |
On calibrating enterprise switch measurements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Internet Measurement Conference ![In: Proceedings of the 9th ACM SIGCOMM Internet Measurement Conference, IMC 2009, Chicago, Illinois, USA, November 4-6, 2009, pp. 143-155, 2009, ACM, 978-1-60558-771-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
network traces, switch-based packet capture, trace calibration, enterprise networks |
16 | József Sziray |
Test Calculation for Logic and Delay Faults in Digital Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), Common Challenges and Solutions, 4-5 December 2006, Austin, Texas, USA, pp. 20-32, 2006, IEEE Computer Society, 978-0-7695-2839-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Test-pattern calculation, logic faults, CMOS transistor structures, functional testing, delay faults, multi-valued logic |
16 | Tyh-Song Hwang, Chung Len Lee 0001, Wen-Zen Shen, Ching Ping Wu |
A Parallel Pattern Mixed-Level Fault Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 716-719, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
14 | Uwe Hübner, Heinrich Theodor Vierhaus, Raul Camposano |
Partitioning and analysis of static digital CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11), pp. 1292-1310, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
14 | Peter Odryna, Kevin Nazareth, Carl Christensen |
A workstation-mixed model circuit simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 186-192, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
13 | Eric Schneider, Hans-Joachim Wunderlich |
Switch Level Time Simulation of CMOS Circuits with Adaptive Voltage and Frequency Scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 38th IEEE VLSI Test Symposium, VTS 2020, San Diego, CA, USA, April 5-8, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-5359-9. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Eric Schneider, Hans-Joachim Wunderlich |
SWIFT: Switch-Level Fault Simulation on GPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(1), pp. 122-135, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
13 | Po-Yao Chuang, Cheng-Wen Wu, Harry H. Chen |
Cell-aware test generation time reduction by using switch-level ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC-Asia ![In: International Test Conference in Asia, ITC-Asia 2017, Taipei, Taiwan, September 13-15, 2017, pp. 27-32, 2017, IEEE, 978-1-5386-3051-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
13 | Harry H. Chen, Simon Y.-H. Chen, Po-Yao Chuang, Cheng-Wen Wu |
Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 25th IEEE Asian Test Symposium, ATS 2016, Hiroshima, Japan, November 21-24, 2016, pp. 197-202, 2016, IEEE Computer Society, 978-1-5090-3809-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
13 | John Sonchack, Adam J. Aviv, Eric Keller, Jonathan M. Smith |
POSTER: OFX: Enabling OpenFlow Extensions for Switch-Level Security Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCS ![In: Proceedings of the 22nd ACM SIGSAC Conference on Computer and Communications Security, Denver, CO, USA, October 12-16, 2015, pp. 1678-1680, 2015, ACM, 978-1-4503-3832-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
13 | Michele Favalli, Marcello Dalpasso |
Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 30(1), pp. 41-55, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
13 | Ming Zhang, Lijun Hang, Wenxi Yao, Zhengyu Lu, Leon M. Tolbert |
A Novel Strategy for Three-Phase/Switch/Level (Vienna) Rectifier Under Severe Unbalanced Grids. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 60(10), pp. 4243-4252, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
13 | Angela Souto Vieites, Roberto R. Osorio |
Architecture and Implementation of a Data Compression System at Switch-Level in ATA-over-Ethernet Storage Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2013 Euromicro Conference on Digital System Design, DSD 2013, Los Alamitos, CA, USA, September 4-6, 2013, pp. 799-802, 2013, IEEE Computer Society, 978-1-4799-2978-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
13 | Reza Sedaghat, M. Reza Javaheri, Prabhleen K. Kalkat, Jalal Mohammad Chikhe |
Switch-level emulation of strength-base soft error detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 51(3), pp. 692-702, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
13 | Reza Sedaghat, M. Reza Javaheri, Prabhleen K. Kalkat, Jalal Mohammad Chikhe |
Switch-level soft error emulation for SET-induced pulses of variable strengths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 41(10), pp. 651-661, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
13 | József Sziray |
Switch-Level Test Calculation for CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: 10th International Workshop on Microprocessor Test and Verification, MTV 2009, Austin, Texas, USA, 7-9 December 2009, pp. 41-48, 2009, IEEE Computer Society, 978-0-7695-4000-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
13 | Leomar S. da Rosa Jr., Felipe Ribeiro Schneider, Renato P. Ribas, André Inácio Reis |
Switch level optimization of digital CMOS gate networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 324-329, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
13 | Nesrine Bel Haj Youssef, Kamal Al-Haddad, Hadi Youssef Kanaan |
Large-Signal Modeling and Steady-State Analysis of a 1.5-kW Three-Phase/Switch/Level (Vienna) Rectifier With Experimental Validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 55(3), pp. 1213-1224, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Nesrine Bel Haj Youssef, Kamal Al-Haddad, Hadi Youssef Kanaan |
Real-Time Implementation of a Discrete Nonlinearity Compensating Multiloops Control Technique for a 1.5-kW Three-Phase/Switch/Level Vienna Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 55(3), pp. 1225-1234, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Peter Ming-Han Lee, Reza Sedaghat |
FPGA-based switch-level fault emulation using module-based dynamic partial reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 48(10), pp. 1724-1733, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Joshua Lawrence, Xin Yuan 0001 |
An MPI tool for automatically discovering the switch level topologies of Ethernet clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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