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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 82 occurrences of 64 keywords
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Results
Found 280 publication records. Showing 280 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
85 | Georgios Karakonstantis, Kaushik Roy 0001 |
Low-Power and Variation-Tolerant Application-Specific System Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 249-292, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
85 | Hamid Mahmoodi |
Low-Power and Variation-Tolerant Memory Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 151-183, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
85 | Meeta Sharma Gupta, Pradip Bose |
Variation-Tolerant Microprocessor Architecture at Low Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 211-247, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
71 | Sachin S. Sapatnekar |
Statistical Design of Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 109-149, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
71 | Shreyas Sen, Vishwanath Natarajan, Abhijit Chatterjee |
Low-Power Adaptive Mixed Signal/RF Circuits and Systems and Self-Healing Solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 293-333, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
71 | Swaroop Ghosh |
Effect of Variations and Variation Tolerance in Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 83-108, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
71 | Benjamin Gojman, Nikil Mehta, Raphael Rubin, André DeHon |
Component-Specific Mapping for Low-Power Operation in the Presence of Variation and Aging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 381-432, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
71 | Wei Zhang 0012, James Williamson, Li Shang |
Power Dissipation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 41-80, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
71 | Aditya Bansal, Rahul M. Rao |
Variations: Sources and Characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 3-39, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
71 | Nikil Mehta, André DeHon |
Low-Power Techniques for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 337-363, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
71 | Bipul C. Paul, Arijit Raychowdhury |
Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 185-207, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
71 | Nikil Mehta, André DeHon |
Variation and Aging Tolerance in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 365-380, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
52 | David Wolpert 0001, Paul Ampadu |
Normal and Reverse Temperature Dependence in Variation-Tolerant Nanoscale Systems with High-k Dielectrics and Metal Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NanoNet ![In: Nano-Net - Third International ICST Conference, NanoNet 2008, Boston, MA, USA, September 14-16, 2008, Revised Selected Papers, pp. 14-18, 2008, Springer, 978-3-642-02426-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Reverse temperature dependence, high-k dielectric, variation-tolerant, metal gate |
39 | Jason Cong, Albert Liu, Bin Liu 0006 |
A variation-tolerant scheduler for better than worst-case behavioral synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 221-228, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
scheduling, variation, behavioral synthesis |
38 | Mohammed Abid Hussain, Madhu Mutyam |
Block remap with turnoff: A variation-tolerant cache design technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 783-788, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Shreyas Sen, Abhijit Chatterjee |
Design of process variation tolerant radio frequency low noise amplifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 392-395, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Marshnil Vipin Dave, Maryam Shojaei Baghini, Dinesh Kumar Sharma |
A process variation tolerant, high-speed and low-power current mode signaling scheme for on-chip interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 389-392, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
current mode singnaling, dynamic overdriving, process variation tolerant |
34 | Aarti Choudhary, Sandip Kundu |
A process variation tolerant self-compensating FinFET based sense amplifier design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 161-164, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
sense amplifier, robustness, process -variation, yield, sram, finfet |
31 | Qikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy 0001 |
Process Variation Tolerant Online Current Monitor for Robust Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 171-176, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos |
Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 330-333, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David M. Brooks |
Process Variation Tolerant 3T1D-Based Cache Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA, pp. 15-26, 2007, IEEE Computer Society, 0-7695-3047-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Osman S. Unsal, James W. Tschanz, Keith A. Bowman, Vivek De, Xavier Vera, Antonio González 0001, Oguz Ergin |
Impact of Parameter Variations on Circuits and Microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 26(6), pp. 30-39, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
variation-tolerant design, impact of VLSI on system design, processor architectures, performance and reliability |
28 | Pei-Hsin Ho |
Industrial clock design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 139-140, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low power, variability, physical design, clock tree synthesis |
28 | Shubhankar Basu, Priyanka Thakore, Ranga Vemuri |
Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 814-820, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Simone Medardoni, Marcello Lajolo, Davide Bertozzi |
Variation tolerant NoC design by means of self-calibrating links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1402-1407, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones |
Variation-tolerant, low-power PN-code acquisition using stochastic sensor NOC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 380-383, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos |
A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 47-52, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
flash adc, nano-cmos, ti comparator, process variation, analog-to-digital converter, low voltage, high speed |
27 | David Wolpert 0001, Paul Ampadu |
A Low-Power Safety Mode for Variation Tolerant Systems-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 33-41, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Xin Fu, Tao Li, José A. B. Fortes |
Soft error vulnerability aware process variation mitigation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 93-104, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Spandana Remarsu, Sandip Kundu |
On process variation tolerant low cost thermal sensor design in 32nm CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 487-492, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
self compensating comparator, dithering, thermal sensor |
23 | Swaroop Ghosh, Swarup Bhunia, Kaushik Roy 0001 |
CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11), pp. 1947-1956, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy 0001 |
Low-power process-variation tolerant arithmetic units using input-based elastic clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 74-79, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
elastic clocking, process tolerant, low power |
23 | Anand Rajaram, David Z. Pan |
Variation tolerant buffered clock network synthesis with cross links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006, pp. 157-164, 2006, ACM, 1-59593-299-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
non-tree clocks, physical design, VLSI CAD, clock network |
23 | James W. Tschanz, Keith A. Bowman, Vivek De |
Variation-tolerant circuits: circuit solutions and techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 762-763, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
parameter variation, body bias, high-performance design |
22 | Jin-O. Seo, Mingoo Seok, SeongHwan Cho |
A 44.2-TOPS/W CNN Processor With Variation-Tolerant Analog Datapath and Variation Compensating Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(5), pp. 1603-1611, May 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
22 | Samane Firouzi, Sepehr Tabrizchi, Fazel Sharifi, Abdel-Hameed A. Badawy |
High performance, variation-tolerant CNFET ternary full adder a process, voltage, and temperature variation-resilient design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 77, pp. 205-216, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Abhishek Mishra, Kamal Kishor Jha, Manisha Pattanaik |
Parameter variation aware hybrid TFET-CMOS based power gating technique with a temperature variation tolerant sleep mode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 45(11), pp. 1515-1521, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
21 | Keith A. Bowman, James W. Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar |
Circuit techniques for dynamic variation tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 4-7, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dynamic variations, error-detection sequential, replica paths, resilient circuits, variation sensors, variation-tolerant circuits, error detection, error correction, error recovery, parameter variations, timing errors |
21 | Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De |
Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 79-84, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
intra-die variations, multi-cycle interconnect, parameter fluctuations, time borrowing, interconnect, parameter variations, within-die variations, variation tolerant |
16 | Nilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy 0001 |
Coping with Variations through System-Level Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 581-586, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Wookjin Shin, Hyeongmin Seo, Sangwan Lee, Dong-Ho Choi, Young-Ho Kwak, Soon-Jae Won, Jaeduk Han |
A Variation-Tolerant Voltage-Mode Transmitter With 3+1 Tap FFE in 28-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 71(4), pp. 1819-1823, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Shohei Imai, Hideyuki Sato, Kenji Mukai, Hiroshi Okabe |
32.3 A Load-Variation-Tolerant Doherty Power Amplifier with Dual-Adaptive-Bias Scheme for 5G Handsets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, pp. 524-526, 2024, IEEE, 979-8-3503-0620-0. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Jiahao Song, Zihan Wu, Xiyuan Tang, Bocheng Xu, Haoyang Luo, Youming Yang 0002, Yuan Wang 0001, Runsheng Wang, Ru Huang |
30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, pp. 490-492, 2024, IEEE, 979-8-3503-0620-0. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Mao Li, Zhaoqing Wang, Sanu K. Mathew, Vivek De, Mingoo Seok |
16.6 PACTOR: A Variation-Tolerant Probing-Attack Detector for a 2.5Gb/s×4-Channel Chip-to-Chip Interface in 28nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, pp. 306-308, 2024, IEEE, 979-8-3503-0620-0. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Yong Lim, Jaehoon Lee, Jongmi Lee, Kwangmin Lim, Seunghyun Oh, Jongwoo Lee, Sung-Ung Kwak |
9.2 A 2.08mW 64.4dB SNDR 400MS/s 12b Pipelined-SAR ADC using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8nm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, pp. 170-172, 2024, IEEE, 979-8-3503-0620-0. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Jieun Park, Yong Ki Lee, Bohdan Karpinskyy, Yunhyeok Choi, Jonghoon Shin, Hyo-Gyuem Rhew, Jongshin Shin |
16.8 A 60Mb/s TRNG with PVT-Variation-Tolerant Design Based on STR in 4nm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, pp. 310-312, 2024, IEEE, 979-8-3503-0620-0. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Ayush Dahiya, Poornima Mittal, Rajesh Rohilla |
Variation-Tolerant Sense Amplifier Using Decoupling Transistors for Enhanced SRAM Read Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 42(10), pp. 5799-5810, October 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Xuliang Wang, Xiaosen Liu, Wing-Hung Ki |
A Self-Clocked and Variation-Tolerant Unified Voltage-and-Frequency Regulator for In-Order Executed Digital Loads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 70(11), pp. 4627-4640, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Kangning Wang, Huidong Zhao, Jiliang Liu, Jialu Yin, Zhi Li, Shushan Qiao |
A low-overhead in-situ timing-error prediction technique with wide-voltage-range transition-detector for variation-tolerant digital circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 20(11), pp. 20230145, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Jongmin Lee, Minsun Kim, Minhyeok Jeong, Gicheol Shin, Yoonmyung Lee |
A 20F2/Bit Current-Integration-Based Differential nand-Structured PUF for Stable and V/T Variation-Tolerant Low-Cost IoT Security. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(10), pp. 2957-2968, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Mithilesh Kumar 0008, Alak Majumder, Abir J. Mondal, Arijit Raychowdhury, Bidyut K. Bhattacharyya |
A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 87, pp. 364-377, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Bhawna Rawat, Poornima Mittal |
A Reliable and Temperature Variation Tolerant 7T SRAM Cell with Single Bitline Configuration for Low Voltage Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 41(5), pp. 2779-2801, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Soyoun Jeong, Jaerok Kim, Minhyeok Jeong, Yoonmyung Lee |
Variation-Tolerant and Low R-Ratio Compute-in-Memory ReRAM Macro With Capacitive Ternary MAC Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 69(7), pp. 2845-2856, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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15 | Vipul Bhatnagar, Manoj Kumar Pandey, Sujata Pandey |
A Variation Tolerant Nanoscale SRAM for Low Power Wireless Sensor Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Pers. Commun. ![In: Wirel. Pers. Commun. 124(4), pp. 3235-3251, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Tomofumi Tsuchida, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine |
Supply-Variation-Tolerant Transimpedance Amplifier Using Non-Inverting Amplifier in 180-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 27th Asia and South Pacific Design Automation Conference, ASP-DAC 2022, Taipei, Taiwan, January 17-20, 2022, pp. 96-97, 2022, IEEE, 978-1-6654-2135-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Jin-O. Seo, Mingoo Seok, SeongHwan Cho |
ARCHON: A 332.7TOPS/W 5b Variation-Tolerant Analog CNN Processor Featuring Analog Neuronal Computation Unit and Analog Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2022, San Francisco, CA, USA, February 20-26, 2022, pp. 258-260, 2022, IEEE, 978-1-6654-2800-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Md Mahadi Masnad, Guowu Zhang, Dan-Xia Xu, Yuri Grinberg, Odile Liboiron-Ladouceur |
Dimensional Variation Tolerant Inverse Designed Broadband Mode Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OFC ![In: Optical Fiber Communications Conference and Exhibition, OFC 2022, San Diego, CA, USA, March 6-10, 2022, pp. 1-3, 2022, IEEE, 978-1-55752-466-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
15 | Samuel J. Engers, Cheng Chu, Dawen Xu 0002, Ying Wang 0001, Fan Chen 0001 |
MOCCA: A Process Variation Tolerant Systolic DNN Accelerator using CNFETs in Monolithic 3D. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6 - 8, 2022, pp. 379-382, 2022, ACM, 978-1-4503-9322-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Sungju Ryu, Jongeun Koo, Wook Kim, Yonghwan Kim, Jae-Joon Kim |
Variation-Tolerant Elastic Clock Scheme for Low-Voltage Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 56(7), pp. 2245-2255, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Neha Sharma, Rajeevan Chandel |
Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Model. Simul. Sci. Comput. ![In: Int. J. Model. Simul. Sci. Comput. 12(4), pp. 2150029:1-2150029:17, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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15 | Dongyeon Kang, Jun Tae Jang, Shinyoung Park, Md. Hasan Raza Ansari, Jong-Ho Bae, Sung-Jin Choi, Dong Myong Kim, Changwook Kim, Seongjae Cho, Dae Hwan Kim |
Threshold-Variation-Tolerant Coupling-Gate α-IGZO Synaptic Transistor for More Reliably Controllable Hardware Neuromorphic System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 59345-59352, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Hasita Veluri, Yida Li, Jessie Xuhua Niu, Evgeny Zamburg, Aaron Voon-Yew Thean |
High-Throughput, Area-Efficient, and Variation-Tolerant 3-D In-Memory Compute System for Deep Convolutional Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Internet Things J. ![In: IEEE Internet Things J. 8(11), pp. 9219-9232, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Monica Gupta, Kirti Gupta, Neeta Pandey |
A novel PVT-variation-tolerant Schmitt-trigger-based 12T SRAM cell with improved write ability and high ION/IOFF ratio in sub-threshold region. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 49(11), pp. 3789-3810, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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15 | Hyungyo Kim, Joon Hwang, Dongseok Kwon, Jangsaeng Kim, Min Kyu Park, Jiseong Im, Byung-Gook Park, Jong-Ho Lee 0002 |
Direct Gradient Calculation: Simple and Variation-Tolerant On-Chip Training Method for Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Adv. Intell. Syst. ![In: Adv. Intell. Syst. 3(8), pp. 2170059, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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15 | Hyungyo Kim, Joon Hwang, Dongseok Kwon, Jangsaeng Kim, Min-Kyu Park, Jiseong Im, Byung-Gook Park, Jong-Ho Lee 0002 |
Direct Gradient Calculation: Simple and Variation-Tolerant On-Chip Training Method for Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Adv. Intell. Syst. ![In: Adv. Intell. Syst. 3(8), pp. 2100064, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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15 | Byungkyu Song, Sehee Lim, Seung-Hyuk Kang, Seong-Ook Jung |
Environmental-Variation-Tolerant Magnetic Tunnel Junction-Based Physical Unclonable Function Cell With Auto Write-Back Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Forensics Secur. ![In: IEEE Trans. Inf. Forensics Secur. 16, pp. 2843-2853, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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15 | Kangqiang Pan, Amr M. S. Tosson, Norman Y. Zhou, Lan Wei |
A Novel Programmable Variation-Tolerant RRAM-based Delay Element Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2021, AB, Canada, November 8-10, 2021, pp. 1-2, 2021, IEEE, 978-1-6654-0959-9. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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15 | Dewei Wang, Sung Justin Kim, Minhao Yang, Aurel A. Lazar, Mingoo Seok |
A Background-Noise and Process-Variation-Tolerant 109nW Acoustic Feature Extractor Based on Spike-Domain Divisive-Energy Normalization for an Always-On Keyword Spotting Device. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2021, San Francisco, CA, USA, February 13-22, 2021, pp. 160-162, 2021, IEEE, 978-1-7281-9549-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Arijit Raychowdhury, Mijung Noh, Keith A. Bowman |
Session 35 Overview: Adaptive Digital Techniques for Variation Tolerant Systems Digital Circuits Subcommittee. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2021, San Francisco, CA, USA, February 13-22, 2021, pp. 488-489, 2021, IEEE, 978-1-7281-9549-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Jongmin Lee, Yoonmyung Lee |
A current-integrated differential NAND-structured PUF for stable and V/T variation-tolerant low-cost IoT security. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2021, Busan, Korea, Republic of, November 7-10, 2021, pp. 1-3, 2021, IEEE, 978-1-6654-4350-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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15 | Wen-Jie Lin, Jeng-Han Tsai, Jen-Hao Cheng, Wei-Heng Lin, Tung-Tsen Chiang, Tian-Wei Huang |
A 67-86 GHz Spectrum-Efficient CMOS Transmitter Supporting 1024-QAM With a Process-Variation-Tolerant Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 74458-74471, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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15 | Gwang Hui Choi, Taehui Na |
Novel MTJ-Based Sensing Inverter Variation Tolerant Nonvolatile Flip-Flop in the Near-Threshold Voltage Region. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 191057-191066, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
15 | Prakhar Sharma, Shourya Gupta, Kirti Gupta, Neeta Pandey |
A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 97, pp. 104703, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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15 | Song Jin, Songwei Pei, Yu Wang |
A variation tolerant scheme for memristor crossbar based neural network designs via two-phase weight mapping and memristor programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Future Gener. Comput. Syst. ![In: Future Gener. Comput. Syst. 106, pp. 270-276, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
15 | Jooyoon Kim, Jongsun Park 0001 |
Variation-Tolerant Separated Pre-Charge Sense Amplifier for Resistive Non-Volatile logic circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2020, Yeosu, South Korea, October 21-24, 2020, pp. 147-148, 2020, IEEE, 978-1-7281-8331-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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15 | Junyoung Ko, Younghwi Yang, Jisu Kim, Cheon An Lee, Young-Sun Min, Jin-Young Chun, Moosung Kim, Seong-Ook Jung |
Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(8), pp. 1828-1839, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
15 | Yongmin Lee, Yoonmyung Lee |
A PVT variation-tolerant static single-phase clocked dual-edge triggered flip-flop for aggressive voltage scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 16(20), pp. 20190528, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
15 | Marco Lanuzza, Raffaele De Rose, Felice Crupi, Massimo Alioto |
An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019, Genoa, Italy, November 27-29, 2019, pp. 158-161, 2019, IEEE, 978-1-7281-0996-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
15 | Jinseok Kim 0004, Jongeun Koo, Taesu Kim, Yulhwa Kim, Hyungjun Kim, Seunghyun Yoo, Jae-Joon Kim |
Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, pp. 118-, 2019, IEEE, 978-4-86348-720-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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15 | Lih-Yih Chiou, Chi-Ray Huang, Chang-Chieh Cheng, Jing-Yu Huang, Wei-Suo Ling |
A Variation-Tolerant Bitline Leakage Sensing Scheme for Near-Threshold SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-DAT ![In: International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Hsinchu, Taiwan, April 22-25, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-0655-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
15 | Furkan Peker, Mustafa Altun |
A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Multi Scale Comput. Syst. ![In: IEEE Trans. Multi Scale Comput. Syst. 4(4), pp. 522-532, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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15 | Sujan K. Gonugondla, Mingu Kang, Naresh R. Shanbhag |
A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 53(11), pp. 3163-3173, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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15 | Weiwei Shan, Xinning Liu, Minyi Lu, Liang Wan, Jun Yang 0006 |
A Low-Overhead Timing Monitoring Technique for Variation-Tolerant Near-Threshold Digital Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 6, pp. 138-145, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
15 | Jaeyoung Park, Young Uk Yim |
Two-Phase Read Strategy for Low Energy Variation-Tolerant STT-RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 26(12), pp. 2584-2590, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
15 | Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula |
Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 26(12), pp. 2628-2640, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
15 | Shinichi Nishizawa, Hidetoshi Onodera |
Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(12), pp. 2222-2230, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
15 | Yi Xu, Jun Yang 0002, Rami G. Melhem |
A Process-Variation-Tolerant Method for Nanophotonic On-Chip Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 14(2), pp. 22:1-22:23, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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15 | Taehui Na, Byungkyu Song, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung |
Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1), pp. 163-174, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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15 | Shourya Gupta, Kirti Gupta, Neeta Pandey |
Pentavariate Vmin Analysis of a Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write and Divided Bit-Line Read. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10), pp. 3326-3337, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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15 | Woo-Rham Bae, Kyung Jean Yoon, Taeksang Song, Borivoje Nikolic |
A Variation-Tolerant, Sneak-Current-Compensated Readout Scheme for Cross-Point Memory Based on Two-Port Sensing Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 65-II(12), pp. 1839-1843, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
15 | Yi Yu, Jia Yuan, Lin-Lin Xie, Shushan Qiao, Yong Hei |
A practical, low-overhead, one-cycle correction design method for variation-tolerant digital circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 15(2), pp. 20171202, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
15 | Asghar Bahramali, Marisa López-Vallejo |
A Temperature Variation Tolerant CMOS-Only Voltage Reference for RFID Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 28th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2018, Platja d'Aro, Spain, July 2-4, 2018, pp. 62-67, 2018, IEEE, 978-1-5386-6365-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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15 | Jeongbin Kim 0001, Ki Tae Kim, Eui-Young Chung |
CAD Tool Flow for Variation-Tolerant Non-Volatile STT-MRAM LUT based FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSCA ![In: Proceedings of the 7th International Conference on Software and Computer Applications, ICSCA 2018, Kuantan, Malaysia, February 08-10, 2018, pp. 312-316, 2018, ACM. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
15 | Khawar Sarfraz, Jin He 0003, Mansun Chan |
A 140-mV Variation-Tolerant Deep Sub-Threshold SRAM in 65-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 52(8), pp. 2215-2220, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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15 | Sheng Wang 0005, Chen Chen 0058, Xiaoyan Xiang, Jian-Yi Meng |
A Variation-Tolerant Near-Threshold Processor With Instruction-Level Error Correction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(7), pp. 1993-2006, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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15 | Abdullah El-Bayoumi, Hassan Mostafa, Ahmed M. Soliman |
A Novel MIM-Capacitor-Based 1-GS/s 14-bit Variation-Tolerant Fully-Differential Voltage-to-Time Converter (VTC) Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 26(5), pp. 1750073:1-1750073:35, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
15 | Yi Wang 0003, Lisha Dong, Rui Mao 0001 |
P-Alloc: Process-Variation Tolerant Reliability Management for 3D Charge-Trapping Flash Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 16(5s), pp. 142:1-142:19, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
15 | Kangwook Jo, Hongil Yoon |
Variation-Tolerant Sensing Circuit for Ultralow-Voltage Operation of Spin-Torque Transfer Magnetic RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 64-II(5), pp. 570-574, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
15 | Sheng Wang 0005, Chen Chen 0058, Xiaoyan Xiang, Jianyi Meng |
A metastability-immune error-resilient flip-flop for near-threshold variation-tolerant designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 14(11), pp. 20170353, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
15 | Yimai Peng, Haobo Zhao, Xun Sun, Chen Sun |
A Side-Channel Attack Resistant AES with 500Mbps, 1.92pJ/Bit PVT Variation Tolerant True Random Number Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017, pp. 249-254, 2017, IEEE Computer Society, 978-1-5090-6762-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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