Search results for "ISSS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Kokichi Futatsugi, Fumio Mizoguchi, Naoki Yonezaki (eds.)	Software Security - Theories and Systems, Second Mext-NSF-JSPS International Symposium, ISSS 2003, Tokyo, Japan, November 4-6, 2003, Revised Papers	ISSS	2004	DBLP DOI BibTeX RDF
1	Osamu Sato, Richard Potter, Mitsuharu Yamamoto, Masami Hagiya	UML Scrapbook and Realization of Snapshot Programming Environment.	ISSS	2003	DBLP DOI BibTeX RDF
1	Kazuhiro Ogata 0001, Kokichi Futatsugi	Formal Analysis of the NetBill Electronic Commerce Protocol.	ISSS	2003	DBLP DOI BibTeX RDF	NetBill, OTS, verification, electronic commerce, security protocol, algebraic specification, CafeOBJ
1	Frederick Butler, Iliano Cervesato, Aaron D. Jaggard, Andre Scedrov	Verifying Confidentiality and Authentication in Kerberos 5.	ISSS	2003	DBLP DOI BibTeX RDF
1	Hiroyuki Nishiyama, Yukinobu Mine, Fumio Mizoguchi	The Design of a Secure Distributed Devices System Based on Immunity.	ISSS	2003	DBLP DOI BibTeX RDF
1	Weijiang Yu, Aloysius K. Mok	Formal Specification and Verification of Resource Bound Security Using PVS.	ISSS	2003	DBLP DOI BibTeX RDF
1	Bart Jacobs 0001, Erik Poll	Java Program Verification at Nijmegen: Developments and Perspective.	ISSS	2003	DBLP DOI BibTeX RDF
1	Yasushi Shinjo, Yoshinori Nakata, Kozo Itano	Securing RPC with a Reference Monitor for System Calls.	ISSS	2003	DBLP DOI BibTeX RDF
1	Fabrizio Baiardi, Alessandro Falleni, Riccardo Granchi, Fabio Martinelli, Marinella Petrocchi, Anna Vaccarelli	SEAS: A Secure E-Voting Applet System.	ISSS	2003	DBLP DOI BibTeX RDF
1	Kohei Suenaga, Yutaka Oiwa, Eijiro Sumii, Akinori Yonezawa	The Interface Definition Language for Fail-Safe C.	ISSS	2003	DBLP DOI BibTeX RDF
1	Koji Hasebe, Mitsuhiro Okada	Inferences on Honesty in Compositional Logic for Protocol Analysis.	ISSS	2003	DBLP DOI BibTeX RDF
1	Daigo Tomioka, Shin-ya Nishizaki, Ritsuya Ikeda	A Cost Estimation Calculus for Analyzing the Resistance to Denial-of-Service Attack.	ISSS	2003	DBLP DOI BibTeX RDF
1	Ashraf Bhery, Shigeki Hagihara, Naoki Yonezaki	A Formal System for Analysis of Cryptographic Encryption and Their Security Properties.	ISSS	2003	DBLP DOI BibTeX RDF	unjudgment, symmetric-content-non-malleability, symmetric-content-indistinguishability, symmetric-key-indistinguishablity, symmetric-content-length-indistinguishability, encryption, judgment, deduction systems
1	David P. Gilliam	Managing Information Technology Security Risk.	ISSS	2003	DBLP DOI BibTeX RDF
1	Noriaki Yoshiura	Decision Procedures for Several Properties of Reactive System Specifications.	ISSS	2003	DBLP DOI BibTeX RDF	Specification Description, Temporal Logic, Reactive System
1	Mitsuhiro Okada, Benjamin C. Pierce, Andre Scedrov, Hideyuki Tokuda, Akinori Yonezawa (eds.)	Software Security -- Theories and Systems, Mext-NSF-JSPS International Symposium, ISSS 2002, Tokyo, Japan, November 8-10, 2002, Revised Papers	ISSS	2003	DBLP DOI BibTeX RDF
1	Matthew Harren, George C. Necula	Lightweight Wrappers for Interfacing with Binary Code in CCured.	ISSS	2003	DBLP DOI BibTeX RDF
1	Andrei Sabelfeld, Andrew C. Myers	A Model for Delimited Information Release.	ISSS	2003	DBLP DOI BibTeX RDF	Computer security, information flow, security policies, confidentiality, noninterference, declassification, security-type systems
1	Akira Mori	Detecting Unknown Computer Viruses - A New Approach.	ISSS	2003	DBLP DOI BibTeX RDF
1	Hirotake Abe, Kazuhiko Kato	Security Policy Descriptions Through the Use of Control Structure of a Target Program.	ISSS	2003	DBLP DOI BibTeX RDF
1	Kazuhiko Kato, Yoshihiro Oyama	SoftwarePot: An Encapsulated Transferable File System for Secure Software Circulation.	ISSS	2002	DBLP DOI BibTeX RDF
1	Dan S. Wallach	A Survey of Peer-to-Peer Security Issues.	ISSS	2002	DBLP DOI BibTeX RDF
1	Andrew D. Gordon 0001, Alan Jeffrey	Typing One-to-One and One-to-Many Correspondences in Security Protocols.	ISSS	2002	DBLP DOI BibTeX RDF
1	Hiroyuki Nishiyama, Fumio Mizoguchi	Design and Implementation of Security System Based on Immune System.	ISSS	2002	DBLP DOI BibTeX RDF
1	Kazuhiro Ogata 0001, Kokichi Futatsugi	Formal Analysis of the iKP Electronic Payment Protocols.	ISSS	2002	DBLP DOI BibTeX RDF
1	Takahiro Shinagawa, Kenji Kono, Takashi Masuda	Flexible and Efficient Sandboxing Based on Fine-Grained Protection Domains.	ISSS	2002	DBLP DOI BibTeX RDF
1	Masami Hagiya, Ryo Takemura, Koichi Takahashi, Takamichi Saito	Verification of Authentication Protocols Based on the Binding Relation.	ISSS	2002	DBLP DOI BibTeX RDF
1	George C. Necula, Robert R. Schneck	Proof-Carrying Code with Untrusted Proof Rules.	ISSS	2002	DBLP DOI BibTeX RDF
1	Iliano Cervesato	Data Access Specification and the Most Powerful Symbolic Attacker in MSR.	ISSS	2002	DBLP DOI BibTeX RDF
1	Yutaka Oiwa, Tatsurou Sekiguchi, Eijiro Sumii, Akinori Yonezawa	Fail-Safe ANSI-C Compiler: An Approach to Making C Programs Secure: Progress Report.	ISSS	2002	DBLP DOI BibTeX RDF
1	Lujo Bauer, Jarred Ligatti, David Walker 0001	Types and Effects for Non-interfering Program Monitors.	ISSS	2002	DBLP DOI BibTeX RDF
1	Koji Hasebe, Mitsuhiro Okada	A Logical Verification Method for Security Protocols Based on Linear Logic and BAN Logic.	ISSS	2002	DBLP DOI BibTeX RDF
1	Stanislaw Jarecki, Patrick Lincoln, Vitaly Shmatikov	Negotiated Privacy: (Extended Abstract).	ISSS	2002	DBLP DOI BibTeX RDF
1	Frank Stajano	Security for Whom?: The Shifting Security Assumptions of Pervasive Computing.	ISSS	2002	DBLP DOI BibTeX RDF
1	J. D. Tygar	Privacy in Sensor Webs and Distributed Information Systems.	ISSS	2002	DBLP DOI BibTeX RDF
1	Wataru Yamazaki, Fumio Mizoguchi	Design and Implementation of Access Control System for Smart Office Environment.	ISSS	2002	DBLP DOI BibTeX RDF
1	Kenta Matsumiya, Soko Aoki, Masana Murase, Hideyuki Tokuda	Active Authentication for Pervasive Computing Environments.	ISSS	2002	DBLP DOI BibTeX RDF
1	Roy H. Campbell, Jalal Al-Muhtadi, Prasad Naldurg, Geetanjali Sampemane, M. Dennis Mickunas	Towards Security and Privacy for Pervasive Computing.	ISSS	2002	DBLP DOI BibTeX RDF
1	John C. Mitchell, Vanessa Teague	Autonomous Nodes and Distributed Mechanisms.	ISSS	2002	DBLP DOI BibTeX RDF
1	Algis Rudys, Dan S. Wallach	Enforcing Java Run-Time Properties Using Bytecode Rewriting.	ISSS	2002	DBLP DOI BibTeX RDF
1	Cédric Fournet, Martín Abadi	Hiding Names: Private Authentication in the Applied Pi Calculus.	ISSS	2002	DBLP DOI BibTeX RDF
1	Iliano Cervesato, Nancy A. Durgin, Patrick Lincoln, John C. Mitchell, Andre Scedrov	A Comparison between Strand Spaces and Multiset Rewriting for Security Protocol Analysis.	ISSS	2002	DBLP DOI BibTeX RDF
1	Ran Canetti, Catherine Meadows 0001, Paul F. Syverson	Environmental Requirements for Authentication Protocols.	ISSS	2002	DBLP DOI BibTeX RDF
1	Reynald Affeldt, Naoki Kobayashi 0001	Formalization and Verification of a Mail Server in Coq.	ISSS	2002	DBLP DOI BibTeX RDF
1	Akira Mori, Kokichi Futatsugi	CafeOBJ as a Tool for Behavioral System Verification.	ISSS	2002	DBLP DOI BibTeX RDF
1	Etsuya Shibayama, Shigeki Hagihara, Naoki Kobayashi 0001, Shin-ya Nishizaki, Kenjiro Taura, Takuo Watanabe	AnZenMail: A Secure and Certified E-mail System.	ISSS	2002	DBLP DOI BibTeX RDF
1	Paolo Ienne, Patrick Thiran, Giovanni De Micheli, Frederic Worm	An Adaptive Low-Power Transmission Scheme for On-Chip Networks.	ISSS	2002	DBLP DOI BibTeX RDF	low-power, systems-on-chip, networks-on-chip
1	Rudy Lauwereins, Chun Wong, Paul Marchal, Johan Vounckx, Patrick David, Stefaan Himpe, Francky Catthoor, Peng Yang	Managing Dynamic Concurrent Tasks in Embedded Real-Time Multimedia Systems.	ISSS	2002	DBLP DOI BibTeX RDF	scheduling, embedded system, low-power, multiprocessor
1	Rainer Dömer, Andreas Gerstlauer, Wolfgang Müller 0003	The Formal Execution Semantics of SpecC.	ISSS	2002	DBLP DOI BibTeX RDF	SpecC, simulation, formal specifications, ASMs
1	Oliver Bringmann 0001, Wolfgang Rosenstiel, Carsten Menn	Controller Estimation for FPGA Target Architectures during High-Level Synthesis.	ISSS	2002	DBLP DOI BibTeX RDF	FPGA, controller, high-level synthesis, area estimation
1	Carles Rodoreda Sala, Natalino G. Busá	A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor.	ISSS	2002	DBLP DOI BibTeX RDF	VLIW processors, reconfigurable logic, architectural synthesis
1	Nader Bagherzadeh, Pai H. Chou, Jinfeng Liu 0006	Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable Processors.	ISSS	2002	DBLP DOI BibTeX RDF	communication speed selection, communication/computation trade-offs, embedded multi-processor, low-power design, functional partitioning
1	Guido Araujo, Sharad Malik, Zhining Huang, Nahri Moreano	Datapath Merging and Interconnection Sharing for Reconfigurable Architectures.	ISSS	2002	DBLP DOI BibTeX RDF	high level and architectural synthesis, reconfigurable computing
1	Alexandru Nicolau, Nikil D. Dutt, Aviral Shrivastava, Partha Biswas, Ashok Halambi	A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design .	ISSS	2002	DBLP DOI BibTeX RDF	compressed instruction set, dual Instruction set, rISA, reduced bit-width instruction set, thumb, design space exploration, register pressure
1	M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha	A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units.	ISSS	2002	DBLP DOI BibTeX RDF	Trimaran, performance, design space exploration, VLIW, ASIP
1	M. Balakrishnan, Peter Marwedel, Lars Wehmeyer, Nils Grunwald, Rajeshwari Banakar, Stefan Steinke	Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip Memory.	ISSS	2002	DBLP DOI BibTeX RDF	onchip memory, energy optimization
1	Ingo Sander, Axel Jantsch, Zhonghai Lu	A Case Study of Hardware and Software Synthesis in ForSyDe.	ISSS	2002	DBLP DOI BibTeX RDF	system design, design methodology, software synthesis, hardware synthesis
1	Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta 0001, Nick Savoiu, Mehrdad Reshadi, Sumit Gupta	Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis.	ISSS	2002	DBLP DOI BibTeX RDF	common sub-expression elimination, dynamic CSE, parallelizing transformations, high-level synthesis
1	Andrew S. Cassidy, Christopher P. Andrews, Donald E. Thomas, JoAnn M. Paul	System-Level Modeling of a Network Switch SoC.	ISSS	2002	DBLP DOI BibTeX RDF	memory visualization level design, network switch, computer-aided design, performance modeling, system modeling
1	Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin	An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems.	ISSS	2002	DBLP DOI BibTeX RDF	design of custom embedded systems, pruning of design exploration space
1	Satoshi Matsushita	Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification.	ISSS	2002	DBLP DOI BibTeX RDF	deign experience, CMP, chip multiprocessor, functional verification, speculative multithreading
1	Anand Raghunathan, Nachiketh R. Potlapally, Srivaths Ravi 0001	Securing Wireless Data: System Architecture Challenges.	ISSS	2002	DBLP DOI BibTeX RDF	WTLS, security, performance, mobile computing, embedded system, wireless communications, encryption, AES, RSA, design methodology, system architecture, platform, DES, IPSec, SSL, decryption, handset, 3DES, security processing
1	Frank Vahid, Susan Cotterell	Tuning of Loop Cache Architectures to Programs in Embedded System Design.	ISSS	2002	DBLP DOI BibTeX RDF	customized architectures, embedded systems, low power, synthesis, memory hierarchy, cores, low energy, tuning, instruction fetching, architecture tuning, loop cache, filter cache
1	Hiroto Yasuura, Hiroyuki Tomiyama, Takanori Okuma, Yun Cao	Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems.	ISSS	2002	DBLP DOI BibTeX RDF	WTLS, security, performance, mobile computing, embedded system, wireless communications, encryption, AES, RSA, design methodology, system architecture, platform, DES, IPSec, SSL, decryption, handset, 3DES, security processing
1	Takao Onoye, Yukihiro Nakamura, Atsuhito Shigiya, Keishi Chikamura, Kosuke Tsujino, Tomonori Izumi, Hirofumi Yamamoto	System-Level Design of IEEE1394 Bus Segment Bridge.	ISSS	2002	DBLP DOI BibTeX RDF	HW/SW co-simulation, IEEE1394, PLI, bus bridge, C/C++, verilog-HDL
1	Daniel Gajski, Andreas Gerstlauer	System-Level Abstraction Semantics.	ISSS	2002	DBLP DOI BibTeX RDF	design semantics, modeling, methodology, system-level design, abstraction levels
1	Juan Carlos López 0001, Fernando Rincón, Francisco Moya, José Manuel Moya	Improving Embedded System Design by Means of HW-SW Compilation on Reconfigurable Coprocessors.	ISSS	2002	DBLP DOI BibTeX RDF	reconfigurable datapaths, hardware-software codesign
1	Erwin A. de Kock	Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study.	ISSS	2002	DBLP DOI BibTeX RDF	multiprocessor mapping, system design method, data parallelism, code transformation, process network, task-level parallelism
1	Nikil D. Dutt, Daniel S. Hirschberg, Mahesh Mamidipaka	Efficient Power Reduction Techniques for Time Multiplexed Address Buses.	ISSS	2002	DBLP DOI BibTeX RDF	address encoding techniques, time-multiplexed addressing, low power
1	Mitsuhisa Sato	OpenMP: Parallel Programming API for Shared Memory Multiprocessors and On-Chip Multiprocessors.	ISSS	2002	DBLP DOI BibTeX RDF	deign experience, CMP, chip multiprocessor, functional verification, speculative multithreading
1	Shuichi Sakai	CMP on SoC: Architect's View.	ISSS	2002	DBLP DOI BibTeX RDF	CMP (Chip Multiprocessor), I/O centric, SoC (System on Chip), parallel processing, dependability
1	Daniel Gajski, Junyu Peng	Optimal Message-Passing for Data Coherency in Distributed Architecture.	ISSS	2002	DBLP DOI BibTeX RDF	architecture refinement, automatic variable refinement, system level design
1	Luciano Lavagno, Mihai T. Lazarescu, Stefano Quer, Sergio Nocco, Claudio Passerone, Gianpiero Cabodi	A Symbolic Approach for the Combined Solution of Scheduling and Allocation.	ISSS	2002	DBLP DOI BibTeX RDF	scheduling, high-level synthesis, automata, BDD, allocation
1	Alex Orailoglu, Peter Petrov	Low-Power Data Memory Communication for Application-Specific Embedded Processors.	ISSS	2002	DBLP DOI BibTeX RDF	onchip memory, energy optimization
1	Hiroto Yasuura, Naofumi Takagi, Srivaths Ravi 0001, Michael Torla, Catherine H. Gebotys	Special Session: Security on SoC.	ISSS	2002	DBLP DOI BibTeX RDF	sequence charts, simulation, validation methodology
1	Haris Lekatsas, Wayne H. Wolf, Yuan Xie 0001	Code Compression for VLIW Processors Using Variable-to-Fixed Coding.	ISSS	2002	DBLP DOI BibTeX RDF	assembly-level analysis, performance estimation, superscalar architectures
1	Jürgen Ruf, Thomas Kropf, Jochen Klose	A Visual Approach to Validating System Level Designs.	ISSS	2002	DBLP DOI BibTeX RDF	sequence charts, simulation, validation methodology
1	Vincent John Mooney III, George F. Riley, Eung S. Shin	Round-Robin Arbiter Design and Generation.	ISSS	2002	DBLP DOI BibTeX RDF	distributed arbiter, round-robin token passing, terabit switch, synthesis, arbiter
1	Soonhoi Ha, Sungchan Kim, Chan-Eun Rhee, Hyunguk Jung, Youngmin Yi, Dohyung Kim 0007	Virtual Synchronization for Fast Distributed Cosimulation of Dataflow Task Graphs.	ISSS	2002	DBLP DOI BibTeX RDF	time accurate simulation, virtual synchronization, distributed simulation, cosimulation
1	El Mostapha Aboulhamid, Yukihiro Nakamura (eds.)	Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan	ISSS	2002	DBLP DOI BibTeX RDF
1	Rajesh K. Gupta 0001, Sandeep K. Shukla, Nick Savoiu	Efficient Simulation of Synthesis-Oriented System Level Designs.	ISSS	2002	DBLP DOI BibTeX RDF	simulation, SystemC, system-level design
1	Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima, Gabriela Nicolescu	Validation in a Component-Based Design Flow for Multicore SoCs.	ISSS	2002	DBLP DOI BibTeX RDF	validation, SoC, abstraction levels, component-based design, cosimulation
1	Ahmed Amine Jerraya, Damien Lyonnard, Samy Meftali, Frédéric Rousseau 0001, Ferid Gharsalli	Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design.	ISSS	2002	DBLP DOI BibTeX RDF	memory wrapper generation, system-on-chip, embedded memory, memory access
1	Abhijit Chatterjee, Peeter Ellervee, Vincent John Mooney III, Jun-Cheol Park, Kyu-won Choi, Kiran Puttaswamy	System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory.	ISSS	2002	DBLP DOI BibTeX RDF	voltage/frequency scaling, embedded systems, design space, power-performance trade-offs
1	Catherine H. Gebotys	Security-Driven Exploration of Cryptography in DSP Cores.	ISSS	2002	DBLP DOI BibTeX RDF	methodology, DSP, low energy, power analysis attack
1	Abhik Roychoudhury, Xianfeng Li, Tulika Mitra	Timing Analysis of Embedded Software for Speculative Processors.	ISSS	2002	DBLP DOI BibTeX RDF	worst case execution time, branch prediction
1	M. Balakrishnan, Anshul Kumar, C. P. Joshi	A New Performance Evaluation Approach for System Level Design Space Exploration.	ISSS	2002	DBLP DOI BibTeX RDF	design space exploration, system level design, statistical simulation
1	Petru Eles, Zebo Peng, Daniel Karlsson	Formal Verification in a Component-Based Reuse Methodology.	ISSS	2002	DBLP DOI BibTeX RDF	model checking, formal verification, reuse, IP, timed petri-nets
1	Sanjay V. Rajopadhye, Steven Derrien	Energy/Power Estimation of Regular Processor Arrays.	ISSS	2002	DBLP DOI BibTeX RDF	processor array partitioning, design space exploration, power estimation, programmable logic
1	William Fornaciari, Vito Trianni, Carlo Brandolese, Donatella Sciuto, Fabio Salice, Giovanni Beltrame	Modeling Assembly Instruction Timing in Superscalar Architectures.	ISSS	2002	DBLP DOI BibTeX RDF	assembly-level analysis, performance estimation, superscalar architectures
1	Tsuneo Nakata, Akio Matsuda, Minoru Shoji, Shinya Kuwamura, Qiang Zhu 0005	An Object-Oriented Design Process for System-on-Chip Using UML.	ISSS	2002	DBLP DOI BibTeX RDF	system level performance evaluation, UML, design process, system level design, object-oriented analysis and design
1	Bin Xiao 0001, Zili Shao, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Qingfeng Zhuge	Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops.	ISSS	2002	DBLP DOI BibTeX RDF	rotation scheduling, software pipelining, retiming, unfolding
1	Giovanni Beltrame, Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto, Vito Trianni	Dynamic modeling of inter-instruction effects for execution time estimation.	ISSS	2001	DBLP DOI BibTeX RDF
1	Tommy Kuhn, Tobias Oppold, C. Schulz-Key, Markus Winterholer, Wolfgang Rosenstiel, Mark Edwards, Yaron Kashai	Object oriented hardware synthesis and verification.	ISSS	2001	DBLP DOI BibTeX RDF
1	Qin Zhao, Twan Basten, Bart Mesman, C. A. J. van Eijk, Jochen A. G. Jess	Static resource models of instruction sets.	ISSS	2001	DBLP DOI BibTeX RDF
1	Zhong Wang, Qingfeng Zhuge, Edwin Hsing-Mean Sha	Scheduling and partitioning for multiple loop nests.	ISSS	2001	DBLP DOI BibTeX RDF
1	Brian Bailey, Daniel Gajski	RTL semantics and methodology.	ISSS	2001	DBLP DOI BibTeX RDF
1	Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay	Combined instruction and loop parallelism in array synthesis for FPGAs.	ISSS	2001	DBLP DOI BibTeX RDF
1	Joonseok Park, Pedro C. Diniz	Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines.	ISSS	2001	DBLP DOI BibTeX RDF
1	Hung-Pin Wen, Chien-Yu Lin, Youn-Long Lin	Concurrent-simulation-based remote IP evaluation over the internet for system-on-a-chip design.	ISSS	2001	DBLP DOI BibTeX RDF

Publications at "ISSS"( http://dblp.L3S.de/Venues/ISSS )