Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Abhishek Maurya, Ayush Singh, Syed Farah Naz, Ambika Prasad Shah |
Metastable SR Flip-Flop Based True Random Number Generator Using QCA Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 292-304, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Aniket Gupta, Govind Bajpai, Navjeet Bagga, Shashank Banchhor, Sudeb Dasgupta, Anand Bulusu, Nitanshu Chauhan |
Unveiling the Impact of Interface Traps Induced on Negative Capacitance Nanosheet FET: A Reliability Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 85-96, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Panasa Srikanth, B. Srinivasu |
High Performance Ternary Full Adder in CNFET-Memristor Logic Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 420-434, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Jitesh Choudhary, Vishesh Bindal, Soumya J. |
MANA: Multi-Application Mapping onto Mesh Network-on-Chip using ANN. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 277-291, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Neha Bajpai, Yogesh Singh Chauhan |
A GaN Based Reverse Recovery Time Limiter Circuit Integrated with a Low Noise Amplifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 212-221, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Mohd Asim Saeed, Deep Sehgal, Surinder Singh |
Four Differential Channels, Programmable Gain, Programmable Data Rate Delta Sigma ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 172-184, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Shivangi Chandrakar, Kunal Kranti Das, Deepika Gupta, Manoj Kumar Majumder |
Signal Integrity and Power Loss Analysis for Different Bump Structures in Cylindrical TSV. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 358-372, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Chanchal, Ajay Kumar Visvkarma, Hardhyan Sheoran, Amit Malik, Robert Laishram, Dipendra Singh Rawal, Manoj Saxena |
Investigation of Traps in AlGaN/GaN HEMT Epitaxial Structure Using Conductance Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 76-84, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Shubham Singhania, Neelam Sharma, Varun Venkitaraman, Chandan Kumar Jha 0001 |
CAR: Community Aware Graph Reordering for Efficient Cache Utilization in Graph Analytics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 453-467, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Bappaditya Mondal, Udit Narayana Kar, Chandan Bandyopadhyay, Debashri Roy, Hafizur Rahaman 0001 |
An Online Testing Technique for the Detection of Control Nodes Displacement Faults (CNDF) in Reversible Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 249-261, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Vivek Kumar, Jyoti Patel, Arnab Datta, Sudeb Dasgupta |
FEM Modeling of Thermal Aspect of Dielectric Inserted Under Source & Drain of 5 nm Nanosheet. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 3-11, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Priyank H. Prajapati, Anand D. Darji |
Hardware Design of Two Stage Reference Free Adaptive Filter for ECG Denoising. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 305-319, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Divya Singh, Sajal K. Paul |
Novel Configuration of Multi-mode Universal Shadow Filter Employing a New Active Block. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 222-233, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Shivendra Yadav, Deepak Joshi, Sanjib Kalita, Tushita Singh |
Quantum Tunnelling and Themonic Emission, Transistor Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 118-125, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Subrata Das, Debesh Kumar Das, Soumya Pandit |
Reliability Aware Global Routing of Graphene Nanoribbon Based Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 373-386, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Syed Farah Naz, Sajid Khan 0001, Ambika Prasad Shah |
Pass Transistor XOR Gate Based Radiation Hardened RO-PUF. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 331-344, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Ajay Kumar, Rohit Dhiman |
Differential Multi-bit Through Glass Vias for Three-Dimensional Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 12-26, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | M. K. Aparna Nair, Vishwas Vasuki Gautam, Abhishek Revinipati, J. Soumya |
Implementation and Analysis of Convolution Image Filtering with RISC-V Based Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 515-526, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Aranya Gupta, Sanjeev Manhas, Bishnu Prasad Das |
Highly Non-linear Feed-Forward Arbiter PUF Against Machine Learning Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 234-248, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Rahul Sharma, Harshal B. Nemade |
Fabrication, Optimization and Testing of Photoconductively Tuned SAW Device Using CBD Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 139-149, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Neelkamal, Sonal Yadav, Hemangee K. Kapoor |
i-MAX: Just-In-Time Wakeup of Maximally Gated Router for Power Efficient Multiple NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 107-117, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Ashwin Sanjay Lele, Srivatsava Jandhyala, Saurabh Gangurde, Virendra Singh, Sreenivas Subramoney, Udayan Ganguly |
Disrupting Low-Write-Energy vs. Fast-Read Dilemma in RRAM to Enable L1 Instruction Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 499-512, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Kunal Kranti Das, Aditya Japa, Deepika Gupta |
A Reconfigurable Arbiter PUF Based on VGSOT MTJ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 320-330, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Hariveer Inumarty, M. Mohamed Asan Basiri |
Low Cost Hardware Design of ECC Scalar Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 387-396, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Chiragkumar B. Patel, Ganesh A. Mulay, Himanshu N. Patel, Pooja Dhankher |
Tile Serial Protocol (TSP) ASIC for Distributed Controllers of Space-Borne RADAR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 540-550, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Rahul Kumar Gupta, Sanjeev Kumar Manhas |
Design, Simulation and Optimization of Aluminum Nitride Based Accelerometer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 39-52, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Wasi Uddin, Ankit Bende, Avinash Singh, Tarun Malviya, Rohit Ranjan, Kumar Priyadarshi, Udayan Ganguly |
Indigenous Fab-Lab Hybrid Device Integration for Phase Change Memory for In-Memory Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 468-477, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Mahesh Vaidya, Alok Naugarhiya, Shrish Verma, Guru Prasad Mishra |
Low Loss Enabled Semi-superjunction 4H-SiC IGBT for High Voltage and Current Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 53-64, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Rudresh Pratap Singh, Shreyam Kumar, Jai Gopal Pandey |
An Overlap-and-Add Based Time Domain Acceleration of CNNs on FPGA-CPU Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 573-583, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Anshul Verma, Bishnu Prasad Das |
Low Power Dual-Band Current Reuse-based LC-Voltage Controlled Oscillator with Shared Inductor for IoT Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 185-198, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Khushwant Sehra, Jeffin Shibu, Meena Mishra, Mridula Gupta, Dipendra Singh Rawal, Manoj Saxena |
Implications of Field Plate HEMT Towards Power Performance at Microwave X - Band. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 65-75, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Anuj Srivastava, Nishant Kumar, Nihar Ranjan Mohapatra, Hari Shankar Gupta |
High Resolution Temperature Sensor Signal Processing ASIC for Cryo-Cooler Electronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 150-157, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Shalu Saini, Anil Lodhi, Anurag Dwivedi, Arpit Khandelwal, Shree Prakash Tiwari |
Resistive Switching Behavior of TiO2/(PVP: MoS2) Nanocomposite Bilayer Hybrid RRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 478-485, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Narnindi Ramani, Saroj Mondal |
A Deep Dive into CORDIC Architectures to Implement Trigonometric Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 551-561, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Rajeewa Kumar Jaisawal, Sunil Rathore, P. N. Kondekar, Navjeet Bagga |
Impact of Temperature on NDR Characteristics of a Negative Capacitance FinFET: Role of Landau Parameter (α). ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 97-106, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Ramesh Kumar, Ajay Kumar Singh, Chiragkumar Patel, S. Vinay Kumar, Himanshu N. Patel, B. Saravana Kumar |
Development of Distributed Controller for Electronic Beam Steering Using Indigenous Rad-Hard ASIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 527-539, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Ambika Prasad Shah, Sudeb Dasgupta, Anand D. Darji, Jaynarayan T. Tudu (eds.) |
VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![Springer, 978-3-031-21513-1 The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Prateek Sinha, Aniket Sharma, Nilay Naharas, Syed Farah Naz, Ambika Prasad Shah |
QCA Technology Based 8-Bit TRNG Design for Cryptography Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 345-357, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | S. Kavitha, Santosh Kumar Vishvakarma, Bhupendra Singh Reniwal |
An Approach Towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 262-274, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Pramod Kumar Bharti, Joycee Mekie |
RTQCC-14T: Radiation Tolerant Quadruple Cross Coupled Robust SRAM Design for Radiation Prone Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 486-498, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Kailash Prasad, Jinay Dagli, Neel Shah, Mallikarjun Pidagannavar, Joycee Mekie |
Impact of Operand Ordering in Approximate Multiplication in Neural Network and Image Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 562-572, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Pooja Choudhary, Lava Bhargava, Masahiro Fujita, Virendra Singh |
Synthesis of LUT Based Approximating Adder Circuits with Formal Error Guarantees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 435-449, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Kanika Monga, Eesha Karnawat, Nitin Chaturvedi, S. Gurunarayanan 0001 |
Design of a Programmable Delay Line with On-Chip Calibration to Achieve Immunity Against Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 408-419, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Anishetti Venkatesh, Chandan Kumar Jha 0001, G. U. Vinod, Masahiro Fujita, Virendra Singh |
Scalable Construction of Formal Error Guaranteed LUT-Based Approximate Multipliers with Analytical Worst-Case Error Bound. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 397-407, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Anmol Verma, Shubhang Srivastava, Ambika Prasad Shah |
Aging Resilient and Energy Efficient Ring Oscillator for PUF Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 199-211, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Arvind Bisht, Yogendra Pratap Pundir, Pankaj Kumar Pal |
Electro-Thermal Analysis of Vertically Stacked Gate All Around Nano-sheet Transistor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 126-136, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Puneet Singh, Saroj Mondal, Krishnan S. Rengarajan |
Low Power, Wideband SiGe HBT LNA Covering 57-64 GHz Band. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 161-171, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Kingsuk Bag, Kislay Deep, Sharad Verma, Shashi Prabha Yadav, Manish Goswami, Kavindra Kandpal |
Design of a Low-Voltage Charge-Sensitive Preamplifier Interfaced with Piezoelectric Tactile Sensor for Tumour Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 27-38, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Gaurav Kumar, Anuj Kumar, Satyadev Ahlawat, Yamuna Prasad |
Low Cost Implementation of Deep Neural Network on Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 584-594, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | T. R. Varun, Rajasekhar Nagulapalli, Immanuel Raja |
A 82μW Mixed-Mode sub-1V Bandgap reference with 25 ppm/°C Temperature Co-efficient with Simultaneous PTAT Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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1 | Yatin Kumar Gupta, Yash Agrawal, Rutu Parekh, Bakul Gohel |
Assessment of Emerging Graphene based Network-on-chip for Integrated Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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1 | Venkata Reddy Kolagatla, J. Mervin, Shabbir Darbar, David Selvakumar, Sankha Saha |
A Randomized Montgomery Powering Ladder Exponentiation for Side-Channel Attack Resilient RSA and Leakage Assessment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-5, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Jay Pathak, Anand D. Darji |
Analysis of Standard Cells performance for In0.53Ga0.47As FinFET with underlap fin length for High Speed Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Rahul Mukherjee, Joydeep Basu, Prasanta Kumar Guha |
High Sensitivity and Power Efficient Heater Structure for Bulk Micromachined Thermal Accelerometer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Sarita Yadav, Nitanshu Chauhan, Archana Pandey, Rajendra Pratap, Anand Bulusu |
Behaviour of FinFET Inverter's Effective Capacitances in Low-Voltage Domain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-5, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Mythrai, Pragna, Kavitha S, P. Singh, A. P. Shah, S. K. Vishwakarma, Bhupendra Singh Reniwal |
Energy Efficient, Hamming Code Technique for Error Detection/Correction Using In-Memory Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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1 | Takshashila Pathade, Yash Agrawal, Rutu Parekh, Girish Kumar Mekala |
CNTFET Based Low Power Repeaters for On-Chip Interconnect System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Abi K. Krishnan, M. H. Supriya, Nalesh Sivanandan |
A Hardware-Software Co-design based Approach for Development of a Distributed DAQ System using FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Saurabh Katre, Shubham Tirmanwar, Debapratim Ghosh |
Broadband CMOS RF Logarithmic Power Detector for sub-6 GHz 5G Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | P. Saravanan 0001, J. Jenitha, S. R. Aasish, S. Sanjana |
Quantum Circuit Design of RECTANGLE Lightweight Cipher. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Shubham, Chetan Pathak, Saurabh Kumar Pandey |
Comprehensive Study and Photovoltaic Performance Analysis of Eco-friendly Perovskite Solar Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-5, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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1 | Deepak K. Sharma, J. John, G. Supriya, Ashwini Jambhalikar, M. S. Giridhar |
Process Development for Very Deep Etching of Silicon Using Two Layer Masks for Fabrication of Mechanically Decoupled MEMS Gyroscope. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Alish Kanani, Swar Vaidya, Harshit Agarwal |
LightFPGA: Scalable and Automated FPGA Acceleration of LightGBM for Machine Learning Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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1 | Raman Thukral, Mohit Goswami, Sharayu Jagtap, Sandeep Goyal, Shalabh Gupta |
A Multi-Octave Frequency Range SerDes with a DLL Free Receiver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | S. Devi, Gourav Tilwankar, Rajesh Zele |
Automated Design of Analog Circuits using Machine Learning Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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1 | Soma Barman Mandal, Moumita Acharya, Samik Basu 0003, Amlan Chakrabarti |
FPGA Implementation of Different Stochastic Biochemical Reactions Involved in a Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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1 | K. Lakshmi BhanuPrakash Reddy, K. B. Dheeraj Kumar, Vikramkumar Pudi |
Design of Energy-Efficient TSPC based D Flip-flop for CNTFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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1 | Nirmal Kumar Boran, Kenrick Pinto, Bernard Menezes |
On Disabling Prefetcher to Amplify Cache Side Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Mahesh Mahadurkar, Nalesh Sivanandan, S. Kala |
Hardware Acceleration of SpMV Multiplier for Deep Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Ganesh Mulay, Himanshu N. Patel, Manish Kumar, Kiral Ghodadra |
FPGA based High Frequency Clock Phase Difference Measurement and Correction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Ashish Sura, Vikas Nehra |
Performance Comparison of Single Level STT and SOT MRAM Cells for Cache Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | |
25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021 ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![IEEE, 978-1-6654-1992-5 The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Diksha Shekhawat, Apoorva Jangir, Jai Gopal Pandey |
A Hardware Generator for Posit Arithmetic and its FPGA Prototyping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Tresa Joseph, T. S. Bindiya |
High Speed and Power Efficient Multiplexer based Matrix Vector Multiplication for LSTM Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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1 | Sahibia Kaur Vohra, Sherin A. Thomas, Mahendra Sakare, Devarshi Mrinal Das |
Analytical Modelling of a CMOS Inter Spike Interval Decoder for Resistive Crossbar based Brain Inspired Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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1 | Yuvam Bhateja, Joshua Roy Palathinkal, Tamajeet Mandal, Pronay Roy, Dipankar Saha |
Modeling of Thermal Properties of Semiconducting Monolayer MoSe2 and WSe2. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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1 | Kaushal Kumari Neeraj, Nihar Ranjan Mohapatra |
Behavior of LDMOS transistors at cryogenic temperature - An experiment based analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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1 | David Selvakumar, J. Mervin, Shashikala Gunderao Pattanshetty, Vivian Desalphine |
Formal Verification and Analysis of a Pseudo Random Number Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Soumya Tapse, Srivatsava Jandhyala, Adithya Reddy Banti |
An All-CMOS Supply, Temperature and Process Invariant Hybrid Current Reference For Power Efficient IoT Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Sayeed Ahmad, Naushad Alam, Mohd. Hasan |
Radiation Hardened Area-Efficient 10T SRAM Cell for Space Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | S. Sharon Dev, S. M. Krishna, S. S. Archana, Rose George Kunthara, K. Neethu, Rekha K. James |
Dual Stage Encoding Technique to Minimize Cross Coupling across NoC Links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Venkata Reddy Kolagatla, Vivian Desalphine, David Selvakumar |
Area-Time Scalable High Radix Montgomery Modular Multiplier for Large Modulus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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1 | Ayazulla Khan Patan, Dimitrios Stathis 0001, Pudi Dhilleswararao, Yu Yang, Srinivas Boppu, Ahmed Hemani |
Design and Implementation of Optimized Register File for Streaming Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Soumya Sambit Rath, Debiprasad Priyabrata Acharya |
A Low Power Analog-to-Information Converter for Wireless Receivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, July 23-25, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-9369-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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1 | Kolluri Rajesh, Anand Tirkey, Anirban Sarkar 0005, Sumanta Pyne |
Reinforcement Learning based Droplet Routing Algorithm for Digital Microfluidic Biochips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, July 23-25, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-9369-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Nilanjana Das, Joy Halder, Baisakhi Das, Biplab K. Sikdar |
Exploring Hard to Detect Sequential Hardware Trojans. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, July 23-25, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-9369-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Sisir Kumar Jena, Santosh Biswas, Jatindra Kumar Deka |
Approximate Testing of Digital VLSI Circuits using Error Significance based Fault Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, July 23-25, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-9369-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Jyotiranjan Swain, Rajesh Kolluri, Sumanta Pyne |
A Proactive Wash droplet routing for Digital Microfluidics Biochip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, July 23-25, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-9369-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Shabbir Darbar, J. Mervin, David Selvakumar |
Side Channel Leakage Assessment Strategy On Attack Resistant AES Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, July 23-25, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-9369-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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1 | Sahan Panguluru, Jai Gopal Pandey |
A Highly Stable and Robust 7T SRAM Cell using Memristor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, July 23-25, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-9369-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Jayanta Paul, Rajat Subhra Bhowmick, Riom Sen, Dwaipayan Ray, Suman S. Manjhi, Soumya Sen, Biplab K. Sikdar |
Evaluation of Face Recognition Schemes for Low-computation IoT System Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, July 23-25, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-9369-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Nirmal Kumar Boran, Dinesh Kumar Yadav, Rishabh Iyer |
Classification based scheduling in Heterogeneous ISA Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, July 23-25, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-9369-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Ajish Zacharias, Gisha C. G., Bijoy Antony Jose |
Chaotic Ring Oscillator Based True Random Number Generator Implementations in FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, July 23-25, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-9369-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Vaibhav Verma, Fiza Akhtar, Anuj Grover |
Comparative Analysis and Implementation of Single-ended Sense Amplifier Schemes using 65nm LSTP CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, July 23-25, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-9369-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Mandakini Kadam, Saroja V. Siddamal, Shripadraj Annigeri |
Design and Implementation of chaotic nondeterministic random seed-based Hybrid True Random Number Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, July 23-25, 2020, pp. 1-5, 2020, IEEE, 978-1-7281-9369-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Arvind Thumatti K. R., Marcel Brand, Christian Heidorn, Srinivas Boppu, Frank Hannig, Jürgen Teich |
Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, July 23-25, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-9369-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Sumit Kumar, Nagesh Ch |
Design of a Two-Step Low-Power and High-Speed CMOS Flash ADC Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, July 23-25, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-9369-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Dinesh Rotake, Anand D. Darji, Jitendra Singh |
Ultrasensitive Multi-Arm-Microcantilever-Based Piezoresistive Sensor for BioMEMS Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, July 23-25, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-9369-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Akshay Birari, Piyush Birla, Kuruvilla Varghese, Bharadwaj S. Amrutur |
A RISC-V ISA Compatible Processor IP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, July 23-25, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-9369-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Amartya Dutta, Riya Majumder, Debasis Dhal, Rajat Kumar Pal |
A Novel Droplet Routing Algorithm with Behavioral Performances in Hexagonal Electrode based DMFB. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, July 23-25, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-9369-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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