|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 700 occurrences of 376 keywords
|
|
|
Results
Found 2246 publication records. Showing 2246 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
38 | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj |
3D configuration caching for 2D FPGAs. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
field programmable gate array (fpga), reconfigurable computing, 3d integration, configuration caching |
38 | Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro López 0001, José Duato |
An hybrid eDRAM/SRAM macrocell to implement first-level data caches. |
MICRO |
2009 |
DBLP DOI BibTeX RDF |
retention time, static and dynamic memory cells, leakage current |
38 | Ping Zhou, Bo Zhao 0007, Jun Yang 0002, Youtao Zhang |
A durable and energy efficient main memory using phase change memory technology. |
ISCA |
2009 |
DBLP DOI BibTeX RDF |
low power, phase change memory, endurance |
38 | Y. Hosogaya, Toshio Endo, Satoshi Matsuoka |
Performance evaluation of parallel applications on next generation memory architecture with power-aware paging method. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Yu-Tsao Hsing, Chun-Chieh Huang, Jen-Chieh Yeh, Cheng-Wen Wu |
SDRAM Delay Fault Modeling and Performance Testing. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Wenjing Zhang, Graham A. Jullien, Vassil S. Dimitrov |
A Programmable Base MDLNS MAC with Self-Generated Look-Up Table. |
IWSOC |
2004 |
DBLP DOI BibTeX RDF |
|
38 | Alexander Thomasian |
Data Allocation and Scheduling in Disks and Disk Arrays. |
MASCOTS Tutorials |
2003 |
DBLP DOI BibTeX RDF |
|
38 | Philip Machanick, Zunaid Patel |
L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy. |
Asia-Pacific Computer Systems Architecture Conference |
2003 |
DBLP DOI BibTeX RDF |
|
38 | Ganesan Umanesan, Eiji Fujiwara |
A Class of Random Multiple Bits in a Byte Error Correcting (S t/b EC)Codes for Semiconductor Memory Systems. |
PRDC |
2002 |
DBLP DOI BibTeX RDF |
|
38 | Wei-Chung Cheng, Massoud Pedram |
Low power techniques for address encoding and memory allocation. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
|
38 | Nien-Tsu Wang, Nam Ling |
A Novel Dual-Path Architecture for HDTV Video Decoding. |
Data Compression Conference |
1999 |
DBLP DOI BibTeX RDF |
|
38 | Yasunao Katayama, Eric J. Stuckey, Sumio Morioka, Zhao Wu |
Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention. |
DFT |
1999 |
DBLP DOI BibTeX RDF |
|
38 | Richard Fromm, Stylianos Perissakis, Neal Cardwell, Christoforos E. Kozyrakis, Bruce McGaughy, David A. Patterson 0001, Thomas E. Anderson, Katherine A. Yelick |
The Energy Efficiency of IRAM Architectures. |
ISCA |
1997 |
DBLP DOI BibTeX RDF |
|
38 | Maurizio Skerlj, Paolo Ienne |
Error Protected Data Bus Inversion Using Standard DRAM Components. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
bus inversion, reliability, low power, memory, ECC, DRAM, error protection |
38 | Riichiro Takemura, Kiyoo Itoh 0001, Tomonori Sekiguchi |
A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-VT sense amplifiers. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
FD-SOI, dynamic-VT sense amplifier, low-voltage RAM, twin-cell DRAM |
38 | Michael I. Fuller, James P. Mabry, John A. Hossack, Travis N. Blalock |
40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
CMOS, DRAM, ultrasound, FIFO, embedded memory |
38 | Victor Delaluz, Anand Sivasubramaniam, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin |
Scheduler-based DRAM energy management. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
scheduler, operating systems, energy management, DRAM, energy estimation |
38 | Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama |
DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage. |
ISMVL |
2000 |
DBLP DOI BibTeX RDF |
logic-in-memory, communication bottleneck, threshold operation, functional pass gate, DRAM, multiple-valued logic |
38 | Norbert Wehn, Søren Hein |
Embedded DRAM Architectural Trade-Offs. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
embedded logic, embedded DRAM |
38 | Jaewon Park, Jae Hoon Lee, Sang-Kil Park, Ki Chul Chun, Kyomin Sohn, Sungho Kang 0001 |
An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
|
35 | Bo Zhao 0007, Yu Du, Youtao Zhang, Jun Yang 0002 |
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor. |
MICRO |
2009 |
DBLP DOI BibTeX RDF |
3D die stacking, NUCA, process variation, DRAM |
35 | Kiyoo Itoh 0001 |
Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet |
35 | Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mossé, Rami G. Melhem |
Near-Memory Caching for Improved Energy Consumption. |
IEEE Trans. Computers |
2007 |
DBLP DOI BibTeX RDF |
Memory power management, Cached DRAM, Power Management, Energy-aware systems, Memory design |
35 | Betty Prince |
Nanotechnology and emerging memories. |
SBCCI |
2007 |
DBLP DOI BibTeX RDF |
FeRAM, ferroelectric, floating body, nanocrystal, nitride storage, scaling issues, single electron memories, memory, variability, scaling, SRAM, MEMs, DRAM, flash, MRAM, phase change, non-volatile, molecular memory |
35 | Jui-Hua Li, Nam Ling |
An efficient video decoder design for MPEG-2 MP@ML. |
ASAP |
1997 |
DBLP DOI BibTeX RDF |
video decoder design, MPEG-2 MP@ML, video decoder architecture, function-specific processing blocks, variable-length decoder, inverse 2-D discrete cosine transform, motion compensation unit, bus-monitoring model, bus arbitration schemes, DRAM accesses, motion compensation, buffer sizes |
32 | Menghao Su, Xiang Gao, Yunji Chen, Qi Liu, Longbing Zhang |
Efficiency-Aware QoS DRAM Scheduler. |
NAS |
2009 |
DBLP DOI BibTeX RDF |
|
32 | Yan Li 0030, Helmut Schneider, Florian Schnabel 0002, Roland Thewes, Doris Schmitt-Landsiedel |
Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Amit Hadke, Tony Benavides, S. J. Ben Yoo, Rajeevan Amirtharajah, Venkatesh Akella |
OCDIMM: Scaling the DRAM Memory Wall Using WDM Based Optical Interconnects. |
Hot Interconnects |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Jorge García-Vidal, Maribel March, Llorenç Cerdà, Jesús Corbal, Mateo Valero |
A DRAM/SRAM Memory Scheme for Fast Packet Buffers. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
high-performance memory systems, Router architecture, storage schemes, packet buffers |
32 | Changwoo Byun, Seog Park, Sejong Oh |
OS-DRAM: A Delegation Administration Model in a Decentralized Enterprise Environment. |
WAIM |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Ad J. van de Goor |
An Industrial Evaluation of DRAM Tests. |
IEEE Des. Test Comput. |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Young-Don Bae, Hoi-Jun Yoo |
A low-power graphics LSI integrating 29Mb embedded DRAM for mobile multimedia applications. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Bruce L. Jacob |
A Case for Studying DRAM Issues at the System Level. |
IEEE Micro |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott |
An Investigation into Crosstalk Noise in DRAM Structures. |
MTDT |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Doris Keitel-Schulz, Norbert Wehn |
Embedded DRAM Development: Technology, Physical Design, and Application Issues. |
IEEE Des. Test Comput. |
2001 |
DBLP DOI BibTeX RDF |
|
32 | Mill-Jer Wang, R.-L. Jiang, J.-W. Hsia, Chih-Hu Wang, Jwu E. Chen |
Guardband Determination for the Detection of Off-State and Junction Leakages in DRAM Testing. |
Asian Test Symposium |
2001 |
DBLP DOI BibTeX RDF |
|
32 | Junji Ogawa, Mark Horowitz |
A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro. |
Intelligent Memory Systems |
2000 |
DBLP DOI BibTeX RDF |
|
32 | Jörg Hilgenstock, Klaus Herrmann 0002, Peter Pirsch |
Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM. |
Great Lakes Symposium on VLSI |
1999 |
DBLP DOI BibTeX RDF |
|
32 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
Incorporating DRAM access modes into high-level synthesis. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
32 | Norman Margolus |
An FPGA architecture for DRAM-based systolic computations. |
FCCM |
1997 |
DBLP DOI BibTeX RDF |
|
29 | Engin Ipek, Jeremy Condit, Edmund B. Nightingale, Doug Burger, Thomas Moscibroda |
Dynamically replicated memory: building reliable systems from nanoscale resistive memories. |
ASPLOS |
2010 |
DBLP DOI BibTeX RDF |
write endurance, phase-change memory |
29 | Doe Hyun Yoon, Mattan Erez |
Virtualized and flexible ECC for main memory. |
ASPLOS |
2010 |
DBLP DOI BibTeX RDF |
fault tolerance, reliability, error correction, memory systems |
29 | Dmitry G. Korzun, Andrei V. Gurtov |
A local equilibrium model for P2P resource ranking. |
SIGMETRICS Perform. Evaluation Rev. |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Sipat Triukose, Zhihua Wen, Michael Rabinovich |
Content delivery networks: how big is big enough? |
SIGMETRICS Perform. Evaluation Rev. |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Alma Riska, Erik Riedel |
Evaluation of disk-level workloads at different time scales. |
SIGMETRICS Perform. Evaluation Rev. |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Wangyuan Zhang, Tao Li 0006 |
Characterizing and mitigating the impact of process variations on phase change based memory systems. |
MICRO |
2009 |
DBLP DOI BibTeX RDF |
process variation, memory system, phase change memory |
29 | Hui Zeng, Matt T. Yourst, Kanad Ghose, Dmitry V. Ponomarev |
MPTLsim: a simulator for X86 multicore processors. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
simulator, microprocessor, coherent cache |
29 | Sundar Iyer, Ramana Rao Kompella, Nick McKeown |
Designing packet buffers for router linecards. |
IEEE/ACM Trans. Netw. |
2008 |
DBLP DOI BibTeX RDF |
hit-rate, line-card, cache, memory hierarchy, router, switches, packet buffer |
29 | Major Bhadauria, Sally A. McKee |
Optimizing thread throughput for multithreaded workloads on memory constrained CMPs. |
Conf. Computing Frontiers |
2008 |
DBLP DOI BibTeX RDF |
performance, efficiency, power, memory bandwidth |
29 | Marius Grannæs, Magnus Jahre, Lasse Natvig |
Low-cost open-page prefetch scheduling in chip multiprocessors. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Taewhan Kim, Jungeun Kim |
Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory-Access Optimization. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Raju Rangaswami, Zoran Dimitrijevic, Edward Y. Chang, Klaus E. Schauser |
Building MEMS-based storage systems for streaming media. |
ACM Trans. Storage |
2007 |
DBLP DOI BibTeX RDF |
Storage architecture, multidisk storage, streaming media, I/O scheduling, MEMS-based storage |
29 | Angel Dominguez, Nghi Nguyen, Rajeev Barua |
Recursive function data allocation to scratch-pad memory. |
CASES |
2007 |
DBLP DOI BibTeX RDF |
profile dependance, embedded systems, compiler, memory allocation, recursive functions, scratch-pad memory |
29 | Tomas Henriksson, Pieter van der Wolf, Axel Jantsch, Alistair C. Bruce |
Network Calculus Applied to Verification of Memory Access Performance in SoCs. |
ESTIMedia |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Bryan Black, Murali Annavaram, Ned Brekelbaum, John DeVale, Lei Jiang, Gabriel H. Loh, Don McCaule, Patrick Morrow, Donald W. Nelson, Daniel Pantuso, Paul Reed, Jeff Rupley, Sadasivan Shankar, John Paul Shen, Clair Webb |
Die Stacking (3D) Microarchitecture. |
MICRO |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Taeho Kgil, Trevor N. Mudge |
FlashCache: a NAND flash memory file cache for low power web servers. |
CASES |
2006 |
DBLP DOI BibTeX RDF |
full-system, server platforms, simulation, embedded system, low power, flash memory, web server, application-specific architectures |
29 | Kun-Bin Lee, Tzu-Chieh Lin, Chein-Wei Jen |
An Efficient Quality-Aware Memory Controller for Multimedia Platform SoC. |
IEEE Trans. Circuits Syst. Video Technol. |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino |
Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Rotenberg |
Tapping ZettaRAMTM for Low-Power Memory Systems. |
HPCA |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Ju Yeob Kim, Sung Je Hong, Jong Kim 0001 |
Parallely testable design for detection of neighborhood pattern sensitive faults in high density DRAMs. |
ISCAS (6) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Rafal Karakiewicz, Roman Genov |
Minimal activity mixed-signal VLSI architecture for real-time linear transforms in video. |
ISCAS (5) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Jungeun Kim, Taewhan Kim |
Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
scheduling, binding, memory access |
29 | Thomas L. Sterling |
Towards Memory Oriented Scalable Computer Architecture and High Efficiency Petaflops Computing. |
NPC |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Graham Kirsch |
Active Memory: Micron's Yukon. |
IPDPS |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Jonathan Mangnall, Steven F. Quigley |
System Level Simulation of a SIMD Active Memory Enhanced PC (Or, Why We Don't Want 100% Bandwidth Utilisation. |
IPDPS |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Hui Zhang, Pinaki Mazumder, Li Ding 0002, Kyounghoon Yang |
Performance modeling of resonant tunneling based RAMs. |
ISCAS (4) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Koji Inoue, Koji Kai, Kazuaki J. Murakami |
Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems. |
Intelligent Memory Systems |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Hak-soo Yu, Songjun Lee, Jacob A. Abraham |
An Adder Using Charge Sharing and its Application in DRAMs. |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Erik G. Hallnor, Steven K. Reinhardt |
A fully associative software-managed cache design. |
ISCA |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Chung-Yu Wu, Yu-Yee Liow |
A new dynamic ternary sense amplifier for 1.5-bit/cell multi-level low-voltage CMOS DRAMs. |
ISCAS (1) |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Heath A. James, Kenneth A. Hawick |
Remote Application Scheduling on Metacomputing Systems. |
HPDC |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Philip Machanick, Pierre Salverda, Lance Pompe |
Hardware-Software Trade-Offs in a Direct Rambus Implementation of the RAMpage Memory Hierarchy. |
ASPLOS |
1998 |
DBLP DOI BibTeX RDF |
|
29 | Thomas Alexander, Gershon Kedem |
Distributed Prefetch-buffer/Cache Design for High-Performance Memory Systems. |
HPCA |
1996 |
DBLP DOI BibTeX RDF |
Prefetch-buffer, cache, prediction, memory |
29 | Leonidas I. Kontothanassis, Rabin A. Sugumar, Greg Faanes, James E. Smith 0001, Michael L. Scott |
Cache performance in vector supercomputers. |
SC |
1994 |
DBLP DOI BibTeX RDF |
|
29 | Hongzhong Zheng, Zhichun Zhu |
Power and Performance Trade-Offs in Contemporary DRAM System Designs for Multicore Processors. |
IEEE Trans. Computers |
2010 |
DBLP DOI BibTeX RDF |
DRAM systems, performance, power, Multicore processors |
29 | Fei Wu 0005, Xiang Chen, Jiguang Wan |
Cache Blocks: An Efficient Scheme for Solid State Drives without DRAM Cache. |
NAS |
2010 |
DBLP DOI BibTeX RDF |
Dirty Data, Random write, Power concumption, Comsumer electronics, SRAM, DRAM, Cache Blocks |
29 | Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King |
PPT: joint performance/power/thermal management of DRAM memory for multi-core systems. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
page allocation, scheduling, power, temperature, DRAM memory |
29 | Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev |
Optimizing Test Length for Soft Faults in DRAM Devices. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
DRAM testing, test length optimization, circuit design, memory layout, delay time, soft faults |
29 | Yong-Ha Park, Jeonghoon Kook, Hoi-Jun Yoo |
Embedded DRAM (eDRAM) Power-Energy Estimation for System-on-a-Chip (SoC) Applications. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
power estimation, embedded DRAM |
29 | Ashley Saulsbury, Su-Jaen Huang, Fredrik Dahlgren |
Efficient management of memory hierarchies in embedded DRAM systems. |
International Conference on Supercomputing |
1999 |
DBLP DOI BibTeX RDF |
cache, latency, memory hierarchy, processor, DRAM, COMA |
26 | Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu 0024, Dinesh Somasekhar, Shih-Lien Lu |
Reducing cache power with low-cost, multi-bit error-correcting codes. |
ISCA |
2010 |
DBLP DOI BibTeX RDF |
ecc, edram, idle power, idle states, multi-bit ecc, refresh power, vccmin, dram |
26 | Banit Agrawal, Timothy Sherwood |
High-bandwidth network memory system through virtual pipelines. |
IEEE/ACM Trans. Netw. |
2009 |
DBLP DOI BibTeX RDF |
VPNM, bank conflicts, mean time to stall, packet reassembly, virtual pipeline, network, memory, DRAM, universal hashing, memory controller, MTS, packet buffering |
26 | Wenlong Li, Eric Q. Li, Aamer Jaleel, Jiulong Shan, Yurong Chen 0001, Qigang Wang, Ravi R. Iyer 0001, Ramesh Illikkal, Yimin Zhang 0002, Dong Liu, Michael Liao, Wei Wei, Jinhua Du |
Understanding the Memory Performance of Data-Mining Workloads on Small, Medium, and Large-Scale CMPs Using Hardware-Software Co-simulation. |
ISPASS |
2007 |
DBLP DOI BibTeX RDF |
DRAM caches, small-scale CMP, medium-scale CMP, large-scale CMP, hardware-software co-simulation, terabyte-level workloads, multithreaded data mining applications, cache design, memory performance, multicore systems, memory system performance |
26 | Zhen Fang 0002, Lixin Zhang 0002, John B. Carter, Ali Ibrahim, Michael A. Parker |
Active memory operations. |
ICS |
2007 |
DBLP DOI BibTeX RDF |
distributed shared memory, cache coherence, stream processing, DRAM, memory performance, thread synchronization |
26 | Ibrahim Hur, Calvin Lin |
Adaptive History-Based Memory Schedulers for Modern Processors. |
IEEE Micro |
2006 |
DBLP DOI BibTeX RDF |
Memory schedulers, IBM Power5, processors, DRAM, memory bandwidth |
26 | Koichi Sato, Brian L. Evans, J. K. Aggarwal |
Designing an Embedded Video Processing Camera Using a 16-bit Microprocessor for a Surveillance System. |
J. VLSI Signal Process. |
2006 |
DBLP DOI BibTeX RDF |
temporal spatio-velocity transform, embedded system, interaction, tracking, video, recognition, microprocessor, surveillance, DRAM, velocity, Ptolemy |
26 | Zaid Al-Ars, Ad J. van de Goor |
Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs. |
IEEE Trans. Computers |
2003 |
DBLP DOI BibTeX RDF |
dynamic faulty behavior, functional fault models, defect simulation, spot defects, Embedded DRAM, fault primitives |
26 | Brian R. Gaeke, Parry Husbands, Xiaoye S. Li, Leonid Oliker, Katherine A. Yelick, Rupak Biswas |
Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines. |
IPDPS |
2002 |
DBLP DOI BibTeX RDF |
memory intensive benchmarks, data parallelism, vector processor, Processor-in-Memory, embedded DRAM |
26 | Kiyoo Itoh 0001 |
Low-voltage memories for power-aware systems. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
DRAM and SRAM cells, gain cells, gate-source/substrate-source back-biasing, memory-rich architectures, multi-Vr, non-volatile RAMs, on-chip voltage converters, peripheral circuits, subthreshold current, testing |
26 | Jörg E. Vollrath, Ulf Lederer, Thomas Hladschik |
Compressed Bit Fail Maps for Memory Fail Pattern Classification. |
J. Electron. Test. |
2001 |
DBLP DOI BibTeX RDF |
bit fail map, compressed bit fail map, catch ram, memory, DRAM |
26 | Preeti Ranjan Panda, Francky Catthoor, Nikil D. Dutt, Koen Danckaert, Erik Brockmeyer, Chidamber Kulkarni, Arnout Vandecappelle, Per Gunnar Kjeldsberg |
Data and memory optimization techniques for embedded systems. |
ACM Trans. Design Autom. Electr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
data optimization, memory architecture customization, memory power dissipation, high-level synthesis, survey, SRAM, allocation, data cache, DRAM, register file, architecture exploration, code transformation, address generation, size estimation |
26 | Mark Brehob, Richard J. Enbody |
The Potential of Carbon-Based Memory Systems. |
MTDT |
1999 |
DBLP DOI BibTeX RDF |
nanotube, buckyball, nanomemory, carbon, memory, nanotechnology, DRAM, RAM |
26 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
Exploiting off-chip memory access modes in high-level synthesis. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
High Level Synthesis, DRAM, Memory Synthesis |
25 | Yuxuan Qin, Chuxiong Lin, Weifeng He, Yanan Sun 0003, Zhigang Mao, Mingoo Seok |
CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Ataberk Olgun, Hasan Hassan, Abdullah Giray Yaglikçi, Yahya Can Tugrul, Lois Orosa 0001, Haocong Luo, Minesh Patel, Oguz Ergin, Onur Mutlu |
DRAM Bender: An Extensible and Versatile FPGA-Based Infrastructure to Easily Test State-of-the-Art DRAM Chips. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Ranyang Zhou, Sabbir Ahmed, Arman Roohi, Adnan Siraj Rakin, Shaahin Angizi |
DRAM-Locker: A General-Purpose DRAM Protection Mechanism against Adversarial DNN Weight Attacks. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Hasan Hassan |
Improving DRAM Performance, Reliability, and Security by Rigorously Understanding Intrinsic DRAM Operation. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Jung-Won Han, S. H. Park, M. Y. Jeong, K. S. Lee, K. N. Kim, H. J. Kim, J. C. Shin, S. M. Park, S. H. Shin, S. W. Park, J. H. Lee, S. H. Kim, B. C. Kim, M. H. Jung, I. Y. Yoon, H. Kim, S. U. Jang, K. J. Park, Y. K. Kim, I. G. Kim, J. H. Oh, S. Y. Han, B. S. Kim, B. J. Kuh, J. M. Park |
Ongoing Evolution of DRAM Scaling via Third Dimension -Vertically Stacked DRAM -. |
VLSI Technology and Circuits |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Mayank Kabra, Prashanth H. C., Kedar Deshpande, Madhav Rao |
HIE-DRAM: High Performance Efficient In-DRAM Computing Architecture for SIMD. |
ISQED |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Wenjing Jin 0001, Wonsuk Jang, Haneul Park, Jongsung Lee 0001, Soosung Kim 0001, Jae W. Lee |
DRAM Translation Layer: Software-Transparent DRAM Power Savings for Disaggregated Memory. |
ISCA |
2023 |
DBLP DOI BibTeX RDF |
|
Displaying result #101 - #200 of 2246 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3][ 4][ 5][ 6][ 7][ 8][ 9][ 10][ 11][ >>] |
|