Search results for "MOS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
31	Mos Kaveh	The joys of leading an academic department.	IEEE Signal Process. Mag.	2004	DBLP DOI BibTeX RDF
31	Ada Diaconescu, Adrian Mos, John Murphy 0001	Automatic Performance Management in Component Based Software Systems.	ICAC	2004	DBLP DOI BibTeX RDF
31	Adrian Mos	A framework for performance management of component based distributed applications.	OOPSLA Companion	2002	DBLP DOI BibTeX RDF
31	Adrian Mos	A framework for performance management of component based distributed applications.	OOPSLA Companion	2002	DBLP DOI BibTeX RDF
31	Adrian Mos, John Murphy 0001	A framework for performance monitoring, modelling and prediction of component oriented distributed systems.	Workshop on Software and Performance	2002	DBLP DOI BibTeX RDF
31	Adrian Mos, John Murphy 0001	Performance Management in Component-Oriented Systems Using a Model Driven ArchitectureTM Approach.	EDOC	2002	DBLP DOI BibTeX RDF
31	Evert C. Mos, J. J. L. Hoppenbrouwers, Martin T. Hill, M. W. Blum, Johannes Joseph H. B. Schleipen, Huug de Waardt	Optical neuron by use of a laser diode with injection seeding and external optical feedback.	IEEE Trans. Neural Networks Learn. Syst.	2000	DBLP DOI BibTeX RDF
31	Daniel Goryn, Mos Kaveh	Direction finding networks based on the approximate maximum likelihood and covariance fit formulations.	ICASSP	1991	DBLP DOI BibTeX RDF
31	Daniel Goryn, Mos Kaveh	Neural networks for narrowband and wideband direction finding.	ICASSP	1988	DBLP DOI BibTeX RDF
31	Hong Wang, Mos Kaveh	Sensitivity and performance analysis of coherent signal-subspace processing for multiple wideband sources.	ICASSP	1985	DBLP DOI BibTeX RDF
30	Dimitar P. Dimitrov	Deep-Submicron MOS Transistor Matching: A Case Study.	DDECS	2008	DBLP DOI BibTeX RDF
30	Daniel Fernández, Jordi Madrenas, Dominik Kapusta, Piotr Michalik	Exponential-enhanced characteristic of MOS transistors and its application to log-domain circuits.	ISCAS	2008	DBLP DOI BibTeX RDF
30	Chutham Sawigun, Jirayuth Mahattanakul	A Compact High Current Efficiency Low-Voltage MOS Transconductor with Nearly Constant Input Voltage Range.	ISCAS	2007	DBLP DOI BibTeX RDF
30	Takashi Sato, Takumi Uezono, Shiho Hagiwara, Kenichi Okada, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu	A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation.	ISQED	2007	DBLP DOI BibTeX RDF
30	Michael Ott, Jason Abt, Udit Sharma, Edward Keyes, Trevor J. Hall, Henry Schriemer	Quantitative Capacitance Measurements of MOS Structures using a Scanning Probe Microscope.	CCECE	2006	DBLP DOI BibTeX RDF
30	Masanori Hariyama, Michitaka Kameyama	A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment.	APCCAS	2006	DBLP DOI BibTeX RDF
30	Changming Ma, Chun Zhang, Zhihua Wang 0001	Power Analysis for the MOS AC/DC Rectifier of Passive RFID Transponders.	APCCAS	2006	DBLP DOI BibTeX RDF
30	Chua-Chin Wang, Tzung-Je Lee, Chih-Chen Li, Ron Hu	An All-MOS High Linearity Voltage-to-Frequency Converter Chip with 520 KHz/V Sensitivity.	APCCAS	2006	DBLP DOI BibTeX RDF
30	Pedram Sameni, Chris Siu, Shahriar Mirabbasi, Hormoz Djahanshahi, Marwa Hamour, Krzysztof Iniewski, Jatinder Chana	Modeling of MOS varactors and characterizing the tuning curve of a 5-6 GHz LC VCO.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
30	Keng Hoong Wee, Ji-Jon Sit, Rahul Sarpeshkar	Biasing techniques for subthreshold MOS resistive grids.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
30	Yuan Yao, Yin Shi, Foster F. Dai	A novel low-power input-independent MOS AC/DC charge pump.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
30	Somnath Sengupta	Analytical expression of HD3 due to non-linear MOS switch in MOSFET-C sample and hold circuits.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
30	Mohammad Taherzadeh-Sani, Ali Abbasian, Behnam Amelifard, Ali Afzali-Kusha	Modeling of MOS transistors based on genetic algorithm and simulated annealing.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
30	Yuanzhong (Paul) Zhou, Duane Connerney, Ronald Carroll, Timwah Luk	Modeling MOS Snapback for Circuit-Level ESD Simulation Using BSIM3 and VBIC Models.	ISQED	2005	DBLP DOI BibTeX RDF
30	Dong-Shong Liang, Kwang-Jow Gan, Long-Xian Su, Chi-Pin Chen, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang	Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits.	IWSOC	2005	DBLP DOI BibTeX RDF
30	Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra	Analysis of MOS cross-coupled LC-tank oscillators using short-channel device equations.	ASP-DAC	2004	DBLP DOI BibTeX RDF
30	Hamilton Klimach, Alfredo Arnaud, Márcio C. Schneider, Carlos Galup-Montoro	Characterization of MOS transistor current mismatch.	SBCCI	2004	DBLP DOI BibTeX RDF	matching, analog design, MOSFET, mismatch, compact models
30	Jing-Hong Conan Zhan, Jon S. Duster, Kevin T. Kornegay	A comparative study of MOS VCOs for low voltage high performance operation.	ISLPED	2004	DBLP DOI BibTeX RDF	FOM, low power, low voltage, VCO, phase noise, RF design
30	Baohua Wang, Pinaki Mazumder	On optimality of adiabatic switching in MOS energy-recovery circuit.	ISLPED	2004	DBLP DOI BibTeX RDF	adiabatic circuit, power clock optimization, variational calculus
30	Baohua Wang, Pinaki Mazumder	On optimality of adiabatic switching in MOS energy-recovery circuit.	ISLPED	2004	DBLP DOI BibTeX RDF	adiabatic circuit, power clock optimization, variational calculus
30	Francisco Serra-Graells, Xavier Redondo	Exact design of all-MOS log filters.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
30	Antonio J. López-Martín, Alfonso Carlosena, Jaime Ramírez-Angulo	A novel design technique for very low voltage MOS translinear circuits.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
30	Aránzazu Otín, Santiago Celma, Concepción Aldea	Modeling of accumulation MOS capacitors for high performance analog circuits.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
30	Jofre Pallares, Justo Sabadell, Francisco Serra-Graells	Modeling all-MOS log filters and its application to Sigma-Delta modulators.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
30	Victor Varshavsky, Vyacheslav Marakhovsky	A Neuron-MOS Threshold Element with Switching Capacitors.	Fuzzy Days	2001	DBLP DOI BibTeX RDF
30	Thomas Tille, Jens Sauerbrey, Doris Schmitt-Landsiedel	A low-voltage MOSFET-only Sigma-Delta modulator for speech band applications using depletion-mode MOS-capacitors in combined series and parallel compensation.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
30	Saeid Nooshabadi	Modelling of effects of temperature profile in the MOS transistor characteristics.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
30	Takao Myono, E. Nishibe, S. Kikuchi, K. Iwatsu, Tatsuya Suzuki, Y. Sasaki, K. Itoh, Haruo Kobayashi 0001	Modeling and parameter extraction technique for high-voltage MOS device.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
30	Jaume Segura 0001, Carol de Benito, Antonio Rubio 0001, Charles F. Hawkins	A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	fault modeling, physical defects, gate oxide short
30	Yung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang	ILLIADS: a fast timing and reliability simulator for digital MOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
30	Yung-Ho Shih, Sung-Mo Kang	Analytic transient solution of general MOS circuit primitives.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
30	F. Joel Ferguson	Detection of multiple faults in MOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
30	Karem A. Sakallah, Yao-Tsung Yen, Steve S. Greenberg	A first-order charge conserving MOS capacitance model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
30	Antun Domic	Layout Synthesis of MOS Digital Cells.	DAC	1990	DBLP DOI BibTeX RDF
30	John Horan, Colin Lyden, Alan Mathewson, Ciaran G. Cahill, W. A. Lane	Analysis of distributed resistance effects in MOS transistors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
30	M. Sytrzycki	Modeling of gate oxide shorts in MOS transistors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
30	Hung Chi Lai, Saburo Muroga	Design of MOS networks in single-rail input logic for incompletely specified functions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
30	M. T. Smith	A Hardware Switch Level Simulator for Large MOS Circuits.	DAC	1987	DBLP DOI BibTeX RDF
30	Daniel Weise	Functional Verification of MOS Circuits.	DAC	1987	DBLP DOI BibTeX RDF
29	R. K. Sharma, Nikhil Raj	MOS Modelling and Simulation of Human Glottis.	ICSAP	2010	DBLP DOI BibTeX RDF	Alveolar pressure, MOS resistor, voice source, vocal fold
29	Ghislaine Thuau, Gabriele Saucier	Optimized Layout of MOS Cells.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	optimised MOS cell layout, optimized topological arrangements, minimized Boolean function, well-structured network, transistor merging procedure, nonseries-parallel network, logic design, circuit layout CAD, minimisation of switching nets, logical optimization, field effect integrated circuits
29	Shinji Nakamura, Kai-Yu Chu	A Single Chip Parallel Multiplier by MOS Technology.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	single chip parallel multiplier, MOS technology, five-counter cell, logic design level, full adder cell design, logic design, integrated logic circuits, multiplying circuits, design optimization, field effect integrated circuits
29	Hans-Joachim Wunderlich, Wolfgang Rosenstiel	On fault modeling for dynamic MOS circuits.	DAC	1986	DBLP DOI BibTeX RDF	dynamic MOS, fault modeling, random testing, test pattern generation
29	Yuval Tamir, Carlo H. Séquin	Design and Application of Self-Testing Comparators Implemented with MOS PLA's.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	two-rail code checker, duplication and matching, faults in VLSI circuits, MOS PLA fault model, self-testing comparator, programmable logic array, Concurrent error detection
29	Kuang-Wei Chiang, Zvonko G. Vranesic	Comments on "Fault Diagnosis of MOS Combinational Networks".	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	MOS logic circuits, test generation, Fault detection
29	Randal E. Bryant	A Switch-Level Model and Simulator for MOS Digital Systems.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	MOS logic simulation, VLSI, switch-level model
29	Yacoub M. El-Ziq, Stephen Y. H. Su	Fault Diagnosis of MOS Combinational Networks.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	computer-aided testing, diagnosable networks, fault testing, MOS (metal oxide semiconductor), fault diagnosis, test generation, design for testability, fault detection, Automatic testing, fault location, fault isolation, computer algorithms, statistical results
29	Isao Shirakawa, Noboru Okuda, Takashi Harada, Sadahiro Tani, Hiroshi Ozaki	A Layout System for the Random Logic Portion of an MOS LSI Chip.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	random logic, minimization of Boolean exeression, MOS ratioless circuit one-dimensional gate array problem, computer-aided design (CAD), layout, large-scale integration (LSI), Complex gate
29	Hussein T. Mouftah, I. B. Jordan	Design of Ternary COS/MOS Memory and Sequential Circuits.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	COS/MOS integrated circuits, fundamental ternary circuits, programmable divide-by-N counters, ternary counters, ternary flip-flops, ternary logic implementation, ternary memory cells, ternary sequential logic, multiple-valued logic
29	Tso-Kai Liu	Synthesis of Feed-Forward MOS Networks with Cells of Similar-Complexities.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	MOS complex cell, negative function, optimal feed-forward network, Boolean expression, cell complexity, input vector
29	Tso-Kai Liu	Synthesis Algorithm for 2-level MOS Networks.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	MOS complex cell, negative function, optimal 2-level network, true vector, Boolean expression
27	Zili Qi, Xinhui Hu, Wangjin Zhou, Sheng Li 0010, Hao Wu, Jian Lu, Xinkang Xu	LE-SSL-MOS: Self-Supervised Learning MOS Prediction with Listener Enhancement.	ASRU	2023	DBLP DOI BibTeX RDF
27	Hamed Aminzadeh	g m/I D functions of MOS devices" >Systematic circuit design and analysis using generalised g m/I D functions of MOS devices.	IET Circuits Devices Syst.	2020	DBLP DOI BibTeX RDF
27	Hamed Aminzadeh, Mohammad Mahdi Valinezhad	0.7-V supply, 21-nW All-MOS voltage reference using a MOS-Only current-driven reference core in digital CMOS.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
27	Varvara Bezhenova, Alicja Malgorzata Michalowska-Forsyth	Aspect ratio of radiation-hardened MOS transistors - Modelling of the equivalent channel dimensions of integrated MOS transistors in radiation-hardened enclosed layout.	Elektrotech. Informationstechnik	2018	DBLP DOI BibTeX RDF
27	Tobias Hoßfeld, Poul E. Heegaard, Martín Varela 0001, Sebastian Möller 0001	QoE beyond the MOS: an in-depth look at QoE via better metrics and their relation to MOS.	Qual. User Exp.	2016	DBLP DOI BibTeX RDF
27	Wladek Grabinski, Fernanda Irrera, Marco Balucani, Paolo Nenzi	Editorial of the Special Issue of Microelectronics Journal on the IEEE International MOS-AK/GSA Workshop on Compact Modeling 2010 (MOS-AK/GSA Rome 2010).	Microelectron. J.	2013	DBLP DOI BibTeX RDF
27	Yeda Regina Venturini	MOS - Ontological Security Model for access control policy negotiation in multi-domains (MOS - Modelo Ontológico de Segurança para negociação de política de controle de acesso em multidomínios).		2006	RDF
27	Menghua Wang, Bryan A. Franz	Comparing the ocean color measurements between MOS and SeaWiFS: a vicarious intercalibration approach for MOS.	IEEE Trans. Geosci. Remote. Sens.	2000	DBLP DOI BibTeX RDF
27	Wonho Yang, Robert E. Yantorno	Improvement of MBSD by scaling noise masking threshold and correlation analysis with MOS difference instead of MOS.	ICASSP	1999	DBLP DOI BibTeX RDF
27	Masayuki Mizuno, Masakazu Yamashina, Koichiro Furuta, Hiroyuki Igura, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Hachiro Yamada	A GHz MOS adaptive pipeline technique using MOS current-mode logic.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
27	L. N. M. Edward	Comment on "Voltage-controlled linear resistor by two MOS transistors and its application to active RC filter MOS integration".	Proc. IEEE	1986	DBLP DOI BibTeX RDF
25	ChenMing Hu	BSIM - making the first international standard MOSFET model.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	BSIM, MOS, compact modeling
25	Andrea Bacioccola, Claudio Cicconetti, Giovanni Stea	User-level performance evaluation of VoIP using ns-2.	VALUETOOLS	2007	DBLP DOI BibTeX RDF	simulation, QoS, VoIP, ns-2, MOS, e-model
25	Do Young Kim, Jong Won Park	An Embedded Variable Bit-Rate Audio Coder for Ubiquitous Speech Communications.	ICUCT	2006	DBLP DOI BibTeX RDF	Embedded Coder, G.729EV, PESQ-WB, Scalable Audio Coder, Ubiquitous Audio, MOS
25	Farhad Alibeygi Parsan, Ahmad Ayatollahi, Adib Abrishamifar	Investigating the linearity of MOSFET-only switched-capacitor DeltaSigma modulators under low-voltage condition.	DDECS	2009	DBLP DOI BibTeX RDF
25	Cosmin Radu Popa	A New FGMOST Euclidean Distance Computational Circuit Based on Algebraic Mean of the Input Potentials.	ICANN (1)	2009	DBLP DOI BibTeX RDF	Computational circuits, FGMOST, VLSI design
25	Dubravko Culibrk, Dragan Kukolj, Petar Vasiljevic, Maja Pokric, Vladimir Zlokolica	Feature Selection for Neural-Network Based No-Reference Video Quality Assessment.	ICANN (2)	2009	DBLP DOI BibTeX RDF	Video quality assessment, no-reference approach, neural-networks, multi-layer perceptron, perceptual quality
25	Manas Somaiya, Christopher M. Jermaine, Sanjay Ranka	Learning correlations using the mixture-of-subsets model.	ACM Trans. Knowl. Discov. Data	2008	DBLP DOI BibTeX RDF	EM algorithm, Mixture modeling, high-dimensional data
25	Akihiro Hirosaki, Masatomo Miura, Atsushi Matsumoto, Takahiro Hanyu	Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices.	ISMVL	2008	DBLP DOI BibTeX RDF	differential-pair circuit, radix-2 signed-digit adder, reliability
25	Joon-Myung Kang, Hong-Taek Ju, Mi-Jung Choi, James Won-Ki Hong	OMA DM Based Remote RF Signal Monitoring of Mobile Devices for QoS Improvement.	MMNS	2007	DBLP DOI BibTeX RDF	Mobile Device Management, RF Signal Monitoring, OMA DM, OMA DM DiagMon, QoS
25	Lijing Ding, Ayman Radwan, Mohamed Samy El-Hennawey, Rafik A. Goubran	Performance Study of Objective Voice Quality Measures in VoIP.	ISCC	2007	DBLP DOI BibTeX RDF
25	Youichi Kurokawa, Yutaka Ishibashi, Toshio Asano	Group Synchronization Control in a Remote Haptic Drawing System.	ICME	2007	DBLP DOI BibTeX RDF
25	Joon-Myung Kang, Hong-Taek Ju, Mi-Jung Choi, James Won-Ki Hong	OMA DM Based Remote Software Debugging of Mobile Devices.	APNOMS	2007	DBLP DOI BibTeX RDF	Mobile Device Diagn-ostics, OMA DM, OMA DM DiagMon, Software Debugging, Device Management
25	René Serral-Gracià, Loránd Jakab, Jordi Domingo-Pascual	Measurement Based Call Quality Reporting.	LCN	2007	DBLP DOI BibTeX RDF
25	Abhijit Karmakar, Arun Kumar 0007, R. K. Patney	A Multiresolution Model of Auditory Excitation Pattern and Its Application to Objective Evaluation of Perceived Speech Quality.	IEEE Trans. Speech Audio Process.	2006	DBLP DOI BibTeX RDF
25	Micah G. O'Halloran, Rahul Sarpeshkar	An analog storage cell with 5e-/sec leakage.	ISCAS	2006	DBLP DOI BibTeX RDF
25	Saurabh Singh, K. Radhakrishna Rao	Low Voltage Analogue Multiplier.	APCCAS	2006	DBLP DOI BibTeX RDF
25	Alexis De Vos, Yvan Van Rentergem	Power Consumption in Reversible Logic Addressed by a Ramp Voltage.	PATMOS	2005	DBLP DOI BibTeX RDF
25	Gilson I. Wirth, Michele G. Vieira, Egas Henes Neto, Fernanda Gusmão de Lima Kastensmidt	Single event transients in combinatorial circuits.	SBCCI	2005	DBLP DOI BibTeX RDF	soft errors, integrated circuits, single event transients
25	Yasushi Sugama, Takahiro Yoshida, Takayuki Hamamoto, Seiichiro Hangai, Choong Seng Boon, Sadaatsu Kato	A Comparison of Subjective Picture Quality with Objective Measure Using Subjective Spatial Frequency.	ICME	2005	DBLP DOI BibTeX RDF
25	Hiroo Masuda, Shin-ichi Ohkawa, Masakazu Aoki	Approach for physical design in sub-100 nm era.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
25	Hung-Ch Lee, Kuo-Tai Chang, Ke-Horng Chen, Wen Tsao Chen	Power Saving of a Dynamic Width Controller for a Monolithic Current-Mode CMOS DC-DC Converter.	IWSOC	2005	DBLP DOI BibTeX RDF
25	Sung Il Han, Young Hee Choi, Hyeon Kyeong Seong, Heung-Soo Kim	A Study on the Design of Flash Analog to Quaternary Converter Using DLC Comparator.	ISMVL	2003	DBLP DOI BibTeX RDF
25	Chandramouli Gopalakrishnan, Srinivas Katkoori	Behavioral synthesis of datapaths with low leakage power.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
25	Samir Mohamed, Francisco Cervantes-Pérez, Hossam Afifi	Audio Quality Assessment in Packet Networks: An "Inter-Subjectivel" Neural Network Model.	ICOIN	2001	DBLP DOI BibTeX RDF	Objective and Subjective Quality Assessment, Communication Quality and Reliability, Voice over IP and Neural Networks, Multimedia Communication, Real-time transmission
25	Toshiya Kondo, Toshio Nishiyama, Hiroshi Kato	Business process management in customer contact services.	NOMS	1998	DBLP DOI BibTeX RDF
25	Nevine Nassif, Madhav P. Desai, Dale H. Hall	Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor.	DAC	1998	DBLP DOI BibTeX RDF	reconstruction, emulation, visibility, functional simulation
25	Meng-Lin Yu, Bryan D. Ackland	VLSI timing simulation with selective dynamic regionization.	ICCAD	1994	DBLP DOI BibTeX RDF
25	Lawrence P. Huang, Randal E. Bryant	Intractability in linear switch-level simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF