Search results for "SDRAM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Vladimir V. Stankovic, Nebojsa Z. Milenkovic	Synchronization algorithm for predictors for SDRAM memories.	J. Supercomput.	2015	DBLP DOI BibTeX RDF
21	Martin Versen, W. Ernst, G. Singh, Prince Gulati	Test setup for reliability studies of DDR2 SDRAM.	Microelectron. Reliab.	2015	DBLP DOI BibTeX RDF
21	Simon Lindenlauf, Hans Höfken, Marko Schuba	Cold Boot Attacks on DDR2 and DDR3 SDRAM.	ARES	2015	DBLP DOI BibTeX RDF
21	Won-Joo Yun, Indal Song, Hanki Jeoung, Hundai Choi, Seok-Ho Lee, Jun-Bae Kim, Chi-Wook Kim, Jung-Hwan Choi, Seong-Jin Jang, Joo-Sun Choi	17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs.	ISSCC	2015	DBLP DOI BibTeX RDF
21	Rajat Chauhan, Prajkta Vyavahare, Siva Kothamasu	Fail-safe I/O to control RESET# pin of DDR3 SDRAM and achieve ultra-low system power.	ISQED	2015	DBLP DOI BibTeX RDF
21	Hao-Yu Yang, Shih-Hua Kuo, Tzu-Hsuan Huang, Chi-Hung Chen, Chris Lin, Mango Chia-Tso Chao	Random pattern generation for post-silicon validation of DDR3 SDRAM.	VTS	2015	DBLP DOI BibTeX RDF
21	Preeti Ranjan Panda, Vishal Patel, Praxal Shah, Namita Sharma 0001, Vaidyanathan Srinivasan, Dipankar Sarma	Power Optimization Techniques for DDR3 SDRAM.	VLSID	2015	DBLP DOI BibTeX RDF
21	Vladimir V. Stankovic, Nebojsa Z. Milenkovic, Oliver M. Vojinovic	Implementation of the Complete Predictor for DDR3 SDRAM.	IEICE Trans. Inf. Syst.	2014	DBLP DOI BibTeX RDF
21	Hongming Chen 0002, Song Ma, Liu Wang, Hao Zhang, Kenyi Pan, Yuhua Cheng	A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller.	Sci. China Inf. Sci.	2014	DBLP DOI BibTeX RDF
21	Tae-Young Oh, Hoeju Chung, Young-Chul Cho, Jang-Woo Ryu, Kiwon Lee, Changyoung Lee, Jin-Il Lee, Hyoung-Joo Kim 0002, Min-Soo Jang, Gong-Heum Han, Kihan Kim, Daesik Moon, Seung-Jun Bae, Joon-Young Park, Kyung-Soo Ha, Jaewoong Lee, Su-Yeon Doo, Jung-Bum Shin, Chang-Ho Shin, Kiseok Oh, Doo-Hee Hwang, Taeseong Jang, Chulsung Park, Kwang-Il Park, Jung-Bae Lee, Joo-Sun Choi	25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.	ISSCC	2014	DBLP DOI BibTeX RDF
21	Reum Oh, Byunghyun Lee, Sang-Woong Shin, Wonil Bae, Hundai Choi, Indal Song, Yun-Sang Lee, Jung-Hwan Choi, Chi-Wook Kim, Seong-Jin Jang, Joo-Sun Choi	Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs.	VLSIC	2014	DBLP DOI BibTeX RDF
21	Chanho Lee	Arbitration and shuffling algorithm for processing multiple commands in SDRAM controller.	ICCE	2014	DBLP DOI BibTeX RDF
21	Kyomin Sohn, Taesik Na, Indal Song, Yong Shim, Wonil Bae, Sanghee Kang, Dongsu Lee, Hangyun Jung, Seok-Hun Hyun, Hanki Jeoung, Ki Won Lee, Jun-Seok Park, Jongeun Lee, Byunghyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung, Byungchul Kim, Jung-Hwan Choi, Seong-Jin Jang, Chi-Wook Kim, Jung-Bae Lee, Joo-Sun Choi	A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
21	Stefan Langemeyer, Peter Pirsch, Holger Blume	Using SDRAM Memories for High-Performance Accesses to Two-Dimensional Matrices Without Transpose.	Int. J. Parallel Program.	2013	DBLP DOI BibTeX RDF
21	Edgar Lakis, Martin Schoeberl	An SDRAM controller for real-time systems.	ISORC	2013	DBLP DOI BibTeX RDF
21	Hardik Shah, Alois C. Knoll, Benny Akesson	Bounding SDRAM interference: detailed analysis vs. latency-rate analysis.	DATE	2013	DBLP DOI BibTeX RDF
21	Sven Goossens, Jasper Kuijsten, Benny Akesson, Kees Goossens	A reconfigurable real-time SDRAM controller for mixed time-criticality systems.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
21	Seung Mo Jung, Jong Hyun Seok, Ho Jin Yoo, Do Hyung Kim 0002, You Keun Han, Woo-Seop Kim, Joo-Sun Choi, Jun Dong Cho	Noise immunity improvement in the RESET signal of DDR3 SDRAM memory module.	SoCC	2013	DBLP DOI BibTeX RDF
21	Gary A. Van Huben, Kirk D. Lamb, R. Brett Tremaine, B. E. Aleman, S. M. Rubow, S. H. Rider, Warren E. Maule, Michael E. Wazlowski	Server-class DDR3 SDRAM memory buffer chip.	IBM J. Res. Dev.	2012	DBLP DOI BibTeX RDF
21	Samuel Bayliss, George A. Constantinides	Analytical synthesis of bandwidth-efficient SDRAM address generators.	Microprocess. Microsystems	2012	DBLP DOI BibTeX RDF
21	Hardik Shah, Andreas Raabe, Alois C. Knoll	Dynamic Priority Queue: An SDRAM Arbiter With Bounded Access Latencies for Tight WCET Calculation	CoRR	2012	DBLP BibTeX RDF
21	Samuel Bayliss, George A. Constantinides	Optimizing SDRAM bandwidth for custom FPGA loop accelerators.	FPGA	2012	DBLP DOI BibTeX RDF
21	Hardik Shah, Andreas Raabe, Alois C. Knoll	Bounding WCET of applications using SDRAM with Priority Based Budget Scheduling in MPSoCs.	DATE	2012	DBLP DOI BibTeX RDF
21	Sven Goossens, Tim Kouters, Benny Akesson, Kees Goossens	Memory-map selection for firm real-time SDRAM controllers.	DATE	2012	DBLP DOI BibTeX RDF
21	Jim D. Garside, Stephen B. Furber, Steve Temple, David M. Clark, Luis A. Plana	An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery.	ASYNC	2012	DBLP DOI BibTeX RDF
21	Suk-Soo Pyo, Jun-Sung Kim, Jung-Han Kim, Hyun-Taek Jung, Taejoong Song, Cheol-Ha Lee, Gyun-Hong Kim, Young-Keun Lee, Kee Sup Kim	A 0.65V embedded SDRAM with smart boosting and power management in a 45nm CMOS technology.	CICC	2012	DBLP DOI BibTeX RDF
21	Yong-Cheol Bae, Joon-Young Park, Sang Jae Rhee, Seung Bum Ko, Yonggwon Jeong, Kwang-Sook Noh, Young Hoon Son, Jaeyoun Youn, Yonggyu Chu, Hyunyoon Cho, Mijo Kim, Daesik Yim, Hyo-Chang Kim, Sang-Hoon Jung, Hye-In Choi, Sungmin Yim, Jung-Bae Lee, Joo-Sun Choi, Kyungseok Oh	A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme.	ISSCC	2012	DBLP DOI BibTeX RDF
21	Kibong Koo, Sunghwa Ok, Yonggu Kang, Seungbong Kim, Choungki Song, Hyeyoung Lee, Hyungsoo Kim, Yongmi Kim, Jeonghun Lee, Seunghan Oak, Yosep Lee, Jungyu Lee 0002, Joongho Lee, Hyungyu Lee, Jaemin Jang, Jongho Jung, Byeongchan Choi, Yong-Ju Kim, Youngdo Hur, Yunsaing Kim, Byong-Tae Chung, Yongtak Kim	A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture.	ISSCC	2012	DBLP DOI BibTeX RDF
21	Kyu-Nam Lim, Woong-Ju Jang, Hyung-Sik Won, Kang-Yeol Lee, Hyungsoo Kim, Dong-Whee Kim, Mi-Hyun Cho, Seung-Lo Kim, Jong-Ho Kang, Keun-Woo Park, Byung-Tae Jeong	A 1.2V 23nm 6F2 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture.	ISSCC	2012	DBLP DOI BibTeX RDF
21	Kyomin Sohn, Taesik Na, Indal Song, Yong Shim, Wonil Bae, Sanghee Kang, Dongsu Lee, Hangyun Jung, Hanki Jeoung, Ki Won Lee, Junsuk Park, Jongeun Lee, Byunghyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung, Jang Seok Choi, Byung-Sick Moon, Jung-Hwan Choi, Byungchul Kim, Seong-Jin Jang, Joo-Sun Choi, Kyungseok Oh	A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme.	ISSCC	2012	DBLP DOI BibTeX RDF
21	Karthik Chandrasekar 0001, Benny Akesson, Kees Goossens	Run-time power-down strategies for real-time SDRAM memory controllers.	DAC	2012	DBLP DOI BibTeX RDF
21	Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim 0003, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, Jin-Hyun Kim, Jin-Kook Kim, Young-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae-Young Lee, Chang-Ho Shin, Yun-Seok Yang, Beom-Sig Cho, Sam-Young Bang, Hyang-Ja Yang, Young-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seokwon Hwang, Jeong-Don Lim, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun	A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction.	IEEE J. Solid State Circuits	2011	DBLP DOI BibTeX RDF
21	Wooyoung Jang, David Z. Pan	Application-Aware NoC Design for Efficient SDRAM Access.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
21	Hadley M. Siqueira, Ivan Saraiva Silva, Márcio Eduardo Kreutz, Edgard de Faria Corrêa	DDR SDRAM Memory Controller for Digital TV Decoders.	SBESC	2011	DBLP DOI BibTeX RDF
21	Samuel Bayliss, George A. Constantinides	Application Specific Memory Access, Reuse and Reordering for SDRAM.	ARC	2011	DBLP DOI BibTeX RDF
21	Andrew B. Kahng, Vaishnav Srinivas	Mobile system considerations for SDRAM interface trends.	SLIP	2011	DBLP DOI BibTeX RDF
21	Seung-Jun Bae, Young-Soo Sohn, Tae-Young Oh, Si-Hong Kim, Yun-Seok Yang, Dae-Hyun Kim 0003, Sang-Hyup Kwak, Ho-Seok Seol, Chang-Ho Shin, Min-Sang Park, Gong-Heom Han, Byeong-Cheol Kim, Yong-Ki Cho, Hye-Ran Kim, Su-Yeon Doo, Young-Sik Kim, Dong-Seok Kang, Young-Ryeol Choi, Sam-Young Bang, Sun-Young Park, Yong-Jae Shin, Gil-Shin Moon, Cheol-Goo Park, Woo-Seop Kim, Hyang-Ja Yang, Jeong-Don Lim, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun	A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW.	ISSCC	2011	DBLP DOI BibTeX RDF
21	Khaldon Hassan, Frédéric Pétrot, Riccardo Locatelli, Marcello Coppola	EEEP: an extreme end to end flow control protocol for SDRAM access through networks on chip.	INA-OCMC@HiPEAC	2011	DBLP DOI BibTeX RDF
21	Jong-Chern Lee, Sin-Hyun Jin, Dae-Suk Kim, Young Jun Ku, Chul Kim, Byung-Kwon Park, Hong-Gyeom Kim, Seong-Jun Ahn, Jaejin Lee, Sung-Joo Hong	A low-power small-area open loop digital DLL for 2.2Gb/s/pin 2Gb DDR3 SDRAM.	A-SSCC	2011	DBLP DOI BibTeX RDF
21	Chih-Ming Hsu	PCB design improvement in the circuit between the north bridge and SDRAM through an integrated procedure.	Expert Syst. Appl.	2010	DBLP DOI BibTeX RDF
21	Vladimir V. Stankovic, Nebojsa Z. Milenkovic	DDR3 SDRAM with a Complete Predictor.	IEICE Trans. Inf. Syst.	2010	DBLP DOI BibTeX RDF
21	Wooyoung Jang, David Z. Pan	An SDRAM-Aware Router for Networks-on-Chip.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
21	R. Shashikumar, C. N. Vijay Kumar, M. Nagendrakumar, C. S. Hemanthkumar	Ahb Compatible DDR Sdram Controller Ip Core for Arm Based Soc	CoRR	2010	DBLP BibTeX RDF
21	Khaldon Hassan, Marcello Coppola	Off-Chip SDRAM Access Through Spidergon STNoC.	ISVLSI (Selected papers)	2010	DBLP DOI BibTeX RDF
21	Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim 0003, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, Jin-Hyun Kim, Jin-Kook Kim, Young-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae-Young Lee, Chang-Ho Shin, Yun-Seok Yang, Beom-Sig Cho, Sam-Young Bang, Hyang-Ja Yang, Young-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seokwon Hwang, Jeong-Don Lim, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun	A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction.	ISSCC	2010	DBLP DOI BibTeX RDF
21	Christophe Alias, Alain Darte, Alexandru Plesco	Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS tool.	ASAP	2010	DBLP DOI BibTeX RDF
21	Hongwei Li, Anton Kummert, Sam Schauland, Jörg Velten	3D wave digital filter implementation on a virtex2 FPGA board with external SDRAM.	nDS	2009	DBLP DOI BibTeX RDF
21	Yongsam Moon, Yong-Ho Cho, Hyun-Bae Lee, Byung-Hoon Jeong, Seok-Hun Hyun, Byungchul Kim, In-Chul Jeong, Seong-Young Seo, Junho Shin, Seok-Woo Choi, Ho-Sung Song, Jung-Hwan Choi, Kyehyun Kyung, Young-Hyun Jun, Kinam Kim	1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture.	ISSCC	2009	DBLP DOI BibTeX RDF
21	Guangrong Pan, Da Feng, Qin Wang 0004, Yue Qi, Meiqiang Yu	The Design and Implementation of AMBA Interfaced High-Performance SDRAM Controller for HDTV SoC.	CSIE (3)	2009	DBLP DOI BibTeX RDF
21	Feng Lin, Roman A. Royer, Brian Johnson, Brent Keeth	A Wide-Range Mixed-Mode DLL for a Combination 512 Mb 2.0 Gb/s/pin GDDR3 and 2.5 Gb/s/pin GDDR4 SDRAM.	IEEE J. Solid State Circuits	2008	DBLP DOI BibTeX RDF
21	Jose M. M. Ferreira	An SDRAM test education package that embeds the factory equipment into the e-learning server.	Int. J. Online Eng.	2008	DBLP BibTeX RDF
21	Sang Joon Hwang, Young-Hyun Jun, Man Young Sung	A pre-emphasis output buffer control scheme for a GDDR3 SDRAM interface.	IEICE Electron. Express	2008	DBLP DOI BibTeX RDF
21	KyungHoon Kim, SangSic Yoon, KiChang Kwean, DaeHan Kwon, SunSuk Yang, MunPhil Park, YongKi Kim, ByongTae Chung	A 5.2Gb/p/s GDDR5 SDRAM with CML clock distribution network.	ESSCIRC	2008	DBLP DOI BibTeX RDF
21	Antonin Bougerol, Florent Miller, Nadine Buard	SDRAM Architecture & Single Event Effects Revealed with Laser.	IOLTS	2008	DBLP DOI BibTeX RDF
21	Ki-Won Lee, Joo-Hwan Cho, Byoung-Jin Choi, Geun-Il Lee, Ho-Don Jung, Woo-Young Lee, Ki-Chon Park, Yongsuk Joo, Jaehoon Cha, Young-Jung Choi, Patrick B. Moran, Jin-Hong Ahn	A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL.	IEEE J. Solid State Circuits	2007	DBLP DOI BibTeX RDF
21	Kyu-Hyoun Kim, Hoeju Chung, Woo-Seop Kim, Moon-Sook Park, Young-Chan Jang, Jinyoung Kim, Hwan-Wook Park, Uksong Kang, Paul W. Coteus, Joo-Sun Choi, Changhyun Kim	An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme.	IEEE J. Solid State Circuits	2007	DBLP DOI BibTeX RDF
21	Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura	An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme.	IEEE J. Solid State Circuits	2007	DBLP DOI BibTeX RDF
21	Jose M. M. Ferreira, Ana C. Leão	Remote Access to Expensive SDRAM Test Equipment: Qimonda Opens the Shop-floor to Test Course Students.	Int. J. Online Eng.	2007	DBLP BibTeX RDF
21	Gary Thorpe, Nagi N. Mekhiel	DDR SDRAM Performance: Locality versus Parallelism.	CAINE	2007	DBLP BibTeX RDF
21	Brian Johnson, Brent Keeth, Feng Lin, Hua Zheng	Phase-Tolerant Latency Control for a Combination 512Mb 2.0Gb/s/pin GDDR3 and 2.5Gb/s/pin GDDR4 SDRAM.	ISSCC	2007	DBLP DOI BibTeX RDF
21	Churoo Park, Hoeju Chung, Yun-Sang Lee, Jaekwan Kim 0003, JaeJun Lee, Moo Sung Chae, Dae-Hee Jung, Sung-Ho Choi, Seung-young Seo, Taek-Seon Park, Jun-Ho Shin, Jin-Hyung Cho, Seunghoon Lee, Ki-Whan Song, Kyu-Hyoun Kim, Jung-Bae Lee, Changhyun Kim, Soo-In Cho	A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
21	Simon Albert, Sven Kalms, Christian Weiss, Achim Schramm	Acquisition and evaluation of long DDR2-SDRAM access sequences.	ISPASS	2006	DBLP DOI BibTeX RDF
21	Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura	An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8: 4 Multiplexed Data-Transfer Scheme.	ISSCC	2006	DBLP DOI BibTeX RDF
21	Kyu-Hyoun Kim, Uksong Kang, Hoeju Chung, Dukha Park, Woo-Seop Kim, Young-Chan Jang, Moon-Sook Park, Hoon Lee, Jinyoung Kim, Jung Sunwoo, Hwan-Wook Park, Hyun-Kyung Kim, Su-Jin Chung, Jae-Kwan Kim 0003, Hyung-Seuk Kim, Kee-Won Kwon, Young-Taek Lee, Joo-Sun Choi, Changhyun Kim	An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme.	ISSCC	2006	DBLP DOI BibTeX RDF
21	Dong-Uk Lee, Hyun-Woo Lee, Ki Chang Kwean, Young-Kyoung Choi, Hyong Uk Moon, Seung-Wook Kwack, Shin-Deok Kang, Kwan-Weon Kim, Yong Ju Kim, Young-Jung Choi, Patrick B. Moran, Jin-Hong Ahn, Joong Sik Kih	A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL.	ISSCC	2006	DBLP DOI BibTeX RDF
21	Sang-Bo Lee, Seong-Jin Jang, Jin-Seok Kwak, Sang-Jun Hwang, Young-Hyun Jun, Soo-In Cho, Chil-Gee Lee	A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
21	Hiroki Fujisawa, Masayuki Nakamura, Yasuhiro Takai, Yasuji Koshikawa, Tatsuya Matano, Seiji Narui, Narikazu Usuki, Chiaki Dono, Shinichi Miyatake, Makoto Morino, Koji Arai, Shuichi Kubouchi, Isamu Fujii, Hideyuki Yoko, Takao Adachi	1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
21	Sheng-Chih Shen, Hung-Ming Hsu, Yi-Wei Chang, Kuen-Jong Lee	A high speed BIST architecture for DDR-SDRAM testing.	MTDT	2005	DBLP DOI BibTeX RDF
21	Changsik Yoo, Kye-Hyun Kyung, Kyunam Lim, Hi-Choon Lee, Joon-Wan Chai, Nak-Won Heo, Dong-Jin Lee, Chang-Hyun Kim	A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
21	Takeshi Hamamoto, Kiyohiro Furutani, Takashi Kubo, Satoshi Kawasaki, Hironori Iga, Takashi Kono, Yasuhiro Konishi, Tsutomu Yoshihara	A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
21	Eduardo Picatoste-Olloqui, Francisco Cardells-Tormo, Jordi Sempere-Agulló, Atilà Herms-Berenguer	Implementing High-Speed Double-Data Rate (DDR) SDRAM Controllers on FPGA.	FPL	2004	DBLP DOI BibTeX RDF
21	Chun-Seok Jeong, Changsik Yoo, Jae-Jin Lee, Joongsik Kih	Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM.	ESSCIRC	2004	DBLP DOI BibTeX RDF
21	Tatsuya Matano, Yasuhiro Takai, Tsugio Takahashi, Yuusuke Sakito, Isamu Fujii, Yoshihiro Takaishi, Hiroki Fujisawa, Shuichi Kubouchi, Seiji Narui, Koji Arai, Makoto Morino, Masayuki Nakamura, Shinichi Miyatake, Toshihiro Sekiguchi, Kuniaki Koyama	A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
21	Jung Pill Kim, Woodward Yang, Han-Yuan Tan	A low-power 256-Mb SDRAM with an on-chip thermometer and biased reference line sensing scheme.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
21	Wei Kuang Lai, Wen Jiunn Hsiao	SDRAM: a SD channel-based multicast scheme on ATM networks for multimedia transmissions.	IEEE Trans. Broadcast.	2003	DBLP DOI BibTeX RDF
21	Pol Marchal, José Ignacio Gómez, Davide Bruni, Luca Benini, Luis Piñuel, Francky Catthoor, Henk Corporaal	SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms.	Embedded Software for SoC	2003	DBLP DOI BibTeX RDF
21	Ning-Yaun Ker, Chung-Ho Chen	An effective SDRAM power mode management scheme for performance and energy sensitive embedded systems.	ASP-DAC	2003	DBLP DOI BibTeX RDF
21	Sung-Ho Wang, Jeongpyo Kim, Joonsuk Lee, Hyoung Sik Nam, Young Gon Kim, Jae Hoon Shim, Hyung Ki Ahn, Seok Kang, Bong Hwa Jeong, Jin-Hong Ahn, Beomsup Kim	A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF
21	Yasuhiro Takai, Mamoru Fujita, Kyoichi Nagata, Satoshi Isa, Shigeyuki Nakazawa, Atsunori Hirobe, Hiroaki Ohkubo, Masato Sakao, Shinichi Horiba, Tadashi Fukase, Yoshihiro Takaishi, Makoto Matsuo, Masahiro Komuro, Tetsuya Uchida, Takashi Sakoh, Kanta Saino, Shirou Uchiyama, Yuichi Takada, Junichi Sekine, Nobuko Nakanishi, Takeshi Oikawa, Masahiko Igeta, Hiroyoshi Tanabe, Hidenobu Miyamoto, Takeo Hashimoto, Hiromu Yamaguchi, Kuniaki Koyama, Yasuo Kobayashi, Takashi Okuda	A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
21	Shigehiro Kuge, Tetsuo Kato, Kiyohiro Furutani, Shigeru Kikuda, Katsuyoshi Mitsui, Takeshi Hamamoto, Jun Setogawa, Kei Hamade, Yuichiro Komiya, Satoshi Kawasaki, Takashi Kono, Teruhiko Amano, Takashi Kubo, Masaru Haraguchi, Yoshito Nakaoka, Mihoko Akiyama, Yasuhiro Konishi, Hideyuki Ozaki, Tsutomu Yoshihara	A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
21	Hong-Kai Chang, Youn-Long Lin	Array allocation taking into account SDRAM characteristics.	ASP-DAC	2000	DBLP DOI BibTeX RDF
21	Hansoo Kim, In-Cheol Park	Array address translation for SDRAM-based video processing applications.	VCIP	2000	DBLP BibTeX RDF
21	Brian Davis, Bruce L. Jacob, Trevor N. Mudge	The New DRAM Interfaces: SDRAM, RDRAM and Variants.	ISHPC	2000	DBLP DOI BibTeX RDF
21	Toshiaki Kirihata, Gerhard Mueller, Brian Ji, Gerd Frankowsky, John M. Ross, Hartmud Terletzki, Dmitry G. Netis, Oliver Weinfurtner, David R. Hanson, Gabriel Daniel, Louis Lu-Chen Hsu, Daniel W. Storaska, Armin M. Reith, Marco A. Hug, Kevin P. Guay, Manfred Selz, Peter Poechmueller, Heinz Hoenigschmid, Matthew R. Wordeman	A 390-mm2, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
21	Akira Yamazaki, Tadato Yamagata, Makoto Hatakenaka, Atsushi Miyanishi, Isao Hayashi, Shigeki Tomishima, Atsuo Mangyo, Yoshio Yukinari, Takashi Tatsumi, Masashi Matsumura, Kazutami Arimoto, Michihiro Yamada	A 5.3-GB/s embedded SDRAM core with slight-boost scheme.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
21	Wei Kuang Lai, Wen Jiunn Hsiao	SDRAM: a SD channel-based multicast scheme with round-robin access on ATM networks.	ICC	1999	DBLP DOI BibTeX RDF
21	Stefano Bertazzoni, Gian Carlo Cardarilli, D. Piergentili, Marcello Salmeri, Adelio Salsano, Domenico Di Giovenale, G. C. Grande, P. Marinucci, S. Sperandei, S. Bartalucci, G. Mazzenga, Marco Ricci 0003, V. Bidoli, D. de Francesco, Piergiorgio Picozza, A. Rovelli	Failure Tests on 64 Mb SDRAM in Radiation Environment.	DFT	1999	DBLP DOI BibTeX RDF
21	Takeshi Hamamoto, Masaki Tsukude, Kazutami Arimoto, Yasuhiro Konishi, Takayuki Miyamoto, Hideyuki Ozaki, Michihiro Yamada	400-MHz random column operating SDRAM techniques with self-skew compensation.	IEEE J. Solid State Circuits	1998	DBLP DOI BibTeX RDF
21	Toshiaki Kirihata, Martin Gall, Kohji Hosokawa, Jean-Marc Dortu, Hing Wong, Peter Pfefferl, Brian L. Ji, Oliver Weinfurtner, John K. DeBrosse, Hartmud Terletzki, Manfred Selz, Wayne Ellis, Matthew R. Wordeman, Oliver Kiehl	A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture.	IEEE J. Solid State Circuits	1998	DBLP DOI BibTeX RDF
21	Satoshi Eto, Masato Matsumiya, Masato Takita, Yuki Ishii, Toshikazu Nakamura, Kuninori Kawabata, Hideki Kano, Ayako Kitamoto, Toshimi Ikeda, Toru Koga, Mitsuhiro Higashiho, Yuji Serizawa, Kazuo Itabashi, Osamu Tsuboi, Yuji Yokoyama, Masao Taguchi	A 1-Gb SDRAM with ground-level precharged bit line and nonboosted 2.1-V word line.	IEEE J. Solid State Circuits	1998	DBLP DOI BibTeX RDF
21	Chang-Hyun Kim, Jung-Hwa Lee, J. B. Lee, Beomsup Kim, C. S. Park, Sang-Bo Lee, S. Y. Lee, C. W. Park, J. G. Roh, Hyoung Sik Nam, D. Y. Kim, D. Y. Lee, Tae-Sung Jung, Hongil Yoon, Soo-In Cho	A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system.	IEEE J. Solid State Circuits	1998	DBLP DOI BibTeX RDF
21	Atsushi Hatakeyama, Hirohiko Mochizuki, Tadao Aikawa, Masato Takita, Yuki Ishii, Hironobu Tsuboi, Shin-ya Fujioka, Shusaku Yamaguchi, Makoto Koga, Yuji Serizawa, Koichi Nishimura, Kuninori Kawabata, Yoshinori Okajima, Michiari Kawano, Hideyuki Kojima, Kazuhiro Mizutani, Toru Anezaki, Masatomo Hasegawa, Masao Taguchi	A 256-Mb SDRAM using a register-controlled digital DLL.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
21	Theo J. Powell, Dan Cline, Francis Hii	A 256Meg SDRAM BIST for Disturb Test Application.	ITC	1997	DBLP DOI BibTeX RDF
21	Takanori Saeki, Yuji Nakaoka, Mamoru Fujita, Akihito Tanaka, Kyoichi Nagata, Kenichi Sakakibara, Tatsuya Matano, Yukio Hoshino, Kazutaka Miyano, Satoshi Isa, Shigeyuki Nakazawa, Eiichiro Kakehashi, John Mark Drynan, Masahiro Komuro, Tadashi Fukase, Haruo Iwasaki, Motohiro Takenaka, Junichi Sekine, Masahiko Igeta, Nobuko Nakanishi, Toshiro Itani, Kazuyoshi Yoshida, Hiroshi Yoshino, Syuichi Hashimoto, Tsuyoshi Yoshii, Michihiko ichinose, Tomoo imura, Masato Uziie, Shinichi Kikuchi, Kuniaki Koyama, Yukio Fukuzo, Takashi Okuda	A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
14	Ankush Varma, Eric Debes, Igor Kozintsev, Paul Klein, Bruce L. Jacob	Accurate and fast system-level power modeling: An XScale-based case study.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	embedded systems, SystemC, Power modeling
14	Ehsan Atoofian, Amirali Baniasadi	Exploiting program cyclic behavior to reduce memory latency in embedded processors.	SAC	2008	DBLP DOI BibTeX RDF	high-speed embedded processors, row buffer, memory
14	Ibrahim Hur, Calvin Lin	A comprehensive approach to DRAM power management.	HPCA	2008	DBLP DOI BibTeX RDF
14	Jan de Cuveland, Felix Rettig, Venelin Angelov, Volker Lindenstruth	An FPGA-based high-speed, low-latency trigger processor for high-energy physics.	FPL	2008	DBLP DOI BibTeX RDF
14	Benny Akesson, Liesbeth Steffens, Eelke Strooisma, Kees Goossens	Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration.	RTCSA	2008	DBLP DOI BibTeX RDF
14	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	VESPA: portable, scalable, and flexible FPGA-based vector processors.	CASES	2008	DBLP DOI BibTeX RDF	SPREE, VESPA, VIRAM, FPGA, custom, SIMD, vector, ASIP, microarchitecture, application specific, soft processor