Search results for "VHDL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
36	Stephan Thesing	Modeling a system controller for timing analysis.	EMSOFT	2006	DBLP DOI BibTeX RDF	aiT, verification, static analysis, VHDL, timing analysis, WCET, worst-case execution time, avionics, peripherals
36	Kang Chul Kim, Chang-Gyoon Lim, Jae Hung Yoo, Seok Bung Han	Simulation Cost Reduction Strategies for Behavioral Model Verification in Bayesian Based Stopping Rule.	EUC	2006	DBLP DOI BibTeX RDF	behavioral VHDL model, semi-random variable, Verification, stopping rule, branch coverage
36	Richard Schroeppel, Cheryl L. Beaver, Rita Gonzales, Russell Miller 0001, Timothy Draelos	A Low-Power Design for an Elliptic Curve Digital Signature Chip.	CHES	2002	DBLP DOI BibTeX RDF	Optimal El Gamal, Characteristic 2, Field Towers, Trinomial Basis, Qsolve, Almost-Inverse Algorithm, Point Halving, Signed Sliding Window, GF(289), GF(2178), Low Power, Digital Signature, VHDL, Hardware, Elliptic Curve, ECDSA, Quadratic Equation
36	William Fornaciari, Fabio Salice, Umberto Bondi, Edi Magini	Development cost and size estimation starting from high-level specifications.	CODES	2001	DBLP DOI BibTeX RDF	project size estimation, VHDL, concurrent engineering, process management, design reuse
36	Serafín Olcoz, Ana Castellvi, Maria Garcia, Jose Angel Gomez	Static Analysis Tools for Soft-Core Reviews and Audits.	DATE	1998	DBLP DOI BibTeX RDF	Soft-Cores, management, analysis, VHDL
36	Phillip Baraona, Perry Alexander	Representing abstract architectures with axiomatic specifications and activation conditions.	ECBS	1997	DBLP DOI BibTeX RDF	abstract architectures representation, activation conditions, VSPEC, Larch interface language, axiomatic style, formal specification, VHDL, formal semantics, formal analysis, axiomatic specifications
35	Mariagrazia Graziano, Massimo Ruo Roch	An Automotive CD-Player Electro-Mechanics Fault Simulation Using VHDL-AMS.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Automotive electro-mechanical test, Fault simulation, VHDL-AMS
35	Sang-Gu Lee, Michio Miyazaki, Jin-Il Kim	Design of Very High-Speed Integer Fuzzy Controller Without Multiplications by Using VHDL.	KES (1)	2007	DBLP DOI BibTeX RDF	Integer operation, VHDL, Fuzzy control, Defuzzification, COG
35	Donald B. Shaw, Dhamin Al-Khalili, Côme Rozon	IC Bridge Fault Modeling for IP Blocks Using Neural Network-Based VHDL Saboteurs.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	neural networks, VHDL, fault models, fault simulation, CMOS ICs, Bridge defects, IP blocks
35	Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes 0001, Everton Carara	From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study.	SBCCI	2003	DBLP DOI BibTeX RDF	transaction level, VHDL, SystemC, System modeling, register transfer level
35	Régis Leveugle, K. Hadjiat	Multi-Level Fault Injection Experiments Based on VHDL Descriptions: A Case Study.	IOLTW	2002	DBLP DOI BibTeX RDF	VHDL, fault injection, VLSI design, dependability analysis
35	Syed Mahfuzul Aziz, C. N. Basheer, Joarder Kamruzzaman	A Synthesisable VHDL Model for an Easily Testable Generalised Multiplier.	DELTA	2002	DBLP DOI BibTeX RDF	Modified Booth, Generic, Synthesis, VHDL, Multiplier, C-Testable
35	Joaquin Gracia, Juan Carlos Baraza, Daniel Gil, Pedro J. Gil	Comparison and Application of Different VHDL-Based Fault Injection Techniques.	DFT	2001	DBLP DOI BibTeX RDF	VHDL-Based Fault Injection, Fault Tolerant Validation
35	Régis Leveugle, R. Cercueil	High Level Modifications of VHDL Descriptions for On-Line Test or Fault Tolerance.	DFT	2001	DBLP DOI BibTeX RDF	circuit architectures, fault tolerance, VHDL, on-line testing
35	Jinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, Xianlong Hong	FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking.	ASP-DAC	1999	DBLP DOI BibTeX RDF	Finite State Machine, VHDL, Symbolic Model Checking
35	Daniel Gil, Juan Carlos Baraza, J. V. Busquets, Pedro J. Gil	Fault Injection into VHDL Models: Analysis of the Error Syndrome of a Microcomputer System.	EUROMICRO	1998	DBLP DOI BibTeX RDF	VHDL simulation, Error syndrome, Propagation latency, Fault injection, Transient faults, Experimental validation
35	Sien-An Ong, Kari Tiensyrjä, Lech Józwiak	Interactive codesign for real-time embedded control systems: task graph generation from SA/VHDL models.	EUROMICRO	1997	DBLP DOI BibTeX RDF	interactive codesign, real-time embedded control systems, task graph generation, InCo, textual functional specification method, linear control structures, static behavioral analysis, graphical functional specification method, high level synthesis, finite-state machines, VHDL, modular design, hierarchical decomposition, hardware software partitioning, cost-efficient
35	Matthias Bauer 0003, Wolfgang Ecker	Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach.	DAC	1997	DBLP DOI BibTeX RDF	VHDL
35	Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell	Automated verification of temporal properties specified as state machines in VHDL.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	automated verification methodology, correctness specifications, Viper microprocessor, Mealy FSM, compatible states, formal specification, formal verification, high level synthesis, finite state machines, VHDL, sequential circuits, state machines, hardware description languages, microprocessor chips, synchronous sequential circuit, temporal properties, liveness properties
34	Gunther Lehmann, Bernhard Wunder, Klaus D. Müller-Glaser	Basic concepts for an HDL reverse engineering tool-set.	ICCAD	1996	DBLP DOI BibTeX RDF	VHDL Verilog Hardware Description Reuse Reverse Engineering Hypertext CASE Visualization Productivity Design Process Analysis Control Flow ADA Graphical Symbol, VHDL
34	Preeti Ranjan Panda, Nikil D. Dutt	1995 high level synthesis design repository.	ISSS	1995	DBLP DOI BibTeX RDF	1995 high level synthesis design repository, VHDL language, behavioral finite state machines, behavioral level, computational complexity, high level synthesis, finite state machines, VHDL, microprocessors, hardware description languages, microprocessor chips, floating point units
34	Frank Vahid	Procedure exlining: a transformation for improved system and behavioral synthesis.	ISSS	1995	DBLP DOI BibTeX RDF	VHDL transformation tool, distinct computation, procedure exlining, procedure inlining, redundant sequences, statements, formal specification, distributed processing, VHDL, hardware description languages, remote procedure calls, behavioral synthesis, behavioral specification, system synthesis, procedure calls, synthesis tools
30	Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali	Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models.	DFT	2003	DBLP DOI BibTeX RDF
30	Shahrzad Mirkhani, Meisam Lavasani, Zainalabedin Navabi	Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
30	Marisa Luisa López-Vallejo, Carlos Angel Iglesias, Juan Carlos López 0001	A Knowledge-based System for Hardware-Software Partitioning.	DATE	1998	DBLP DOI BibTeX RDF
30	Steven P. Smith, Ramón D. Acosta	A Value System for Switch-Level Modeling.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
30	Moe Shahdad	Software and system design: VHSIC Hardware Description Language overview.	ACM Annual Conference	1984	DBLP DOI BibTeX RDF
29	Robert Meagher, Modukuri Sushmitha, Maher E. Rizkalla, Paul Salama, Mohamed El-Sharkawy 0001	VHDL Design for Real Time Motion Estimation Video Applications.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	simulation, Real time, Motion estimation, Hardware, Video compression
29	Barry Schulz, Chirag Parikh, Christian Trefftz	Opportunities for parallelism when implementing algorithms in VHDL - a case study - Shift-Or.	EIT	2009	DBLP DOI BibTeX RDF
29	Stephen Wood, David H. Akehurst, O. Uzenkov, W. Gareth J. Howells, Klaus D. McDonald-Maier	A Model-Driven Development Approach to Mapping UML State Diagrams to Synthesizable VHDL.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
29	Flavius Gruian, Mark Westmijze	VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture.	SAC	2008	DBLP DOI BibTeX RDF	embedded systems, java processor, Bluespec
29	Felipe Machado, Teresa Riesgo, Yago Torroja	A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits.	PATMOS	2006	DBLP DOI BibTeX RDF
29	Nagarajan Ranganathan, Ravi Namballa, Narender Hanchate	CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL.	ISVLSI	2006	DBLP DOI BibTeX RDF
29	Ales Smrcka, Vojtech Rehák, Tomás Vojnar, David Safránek, Petr Matousek, Z. Rehák	Verifying VHDL Designs with Multiple Clocks in SMV.	FMICS/PDMC	2006	DBLP DOI BibTeX RDF
29	Ginés Doménech-Asensi, José-Alejandro López Alcantud, Ramón Ruiz Merino	Description and Simulation of Bio-inspired Systems Using VHDL-AMS.	IWINAC (2)	2005	DBLP DOI BibTeX RDF
29	Terkel K. Tolstrup, Flemming Nielson, Hanne Riis Nielson	Information Flow Analysis for VHDL.	PaCT	2005	DBLP DOI BibTeX RDF
29	Avinash G. Keskar, Kishor Kadbe, Nikhil Damle, Pooja Deshpande	Finely Tuned Cascaded Fuzzy Controllers with VHDL - A Case Study for Linerization of V-I Characteristics of a Convertor.	KES (2)	2005	DBLP DOI BibTeX RDF
29	David A. Gwaltney, Kenneth Dutton	A VHDL Core for Intrinsic Evolution of Discrete Time Filters with Signal Feedback.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
29	Robert Bogdan Staszewski, Roman Staszewski, Poras T. Balsara	VHDL Simulation and Modeling of an All-Digital RF Transmitter.	IWSOC	2005	DBLP DOI BibTeX RDF
29	Anneliese Amschler Andrews, Andrew O'Fallon, Tom Chen 0001	RUBASTEM: A Method for Testing VHDL Behavioral Models.	HASE	2004	DBLP DOI BibTeX RDF
29	Kimmo U. Järvinen, Matti Tommiska, Jorma Skyttä	A VHDL Generator for Elliptic Curve Cryptography.	FPL	2004	DBLP DOI BibTeX RDF
29	Massimo Bombana, Francesco Bruschi	SystemC-VHDL Co-Simulation and Synthesis in the HW Domain.	DATE	2003	DBLP DOI BibTeX RDF
29	Eric W. Johnson	Extensive Introduction to VHDL and PLDs in the Sophomore Year.	MSE	2003	DBLP DOI BibTeX RDF
29	S. R. Seward, Parag K. Lala	Fault Injection for Verifying Testability at the VHDL Level.	ITC	2003	DBLP DOI BibTeX RDF
29	Fazrena A. Hamid, Tom J. Kazmierski	Synthesis and optimization of analog VLSI filters from VHDL-AMS parse trees.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
29	Ashraf Salem	Semi-formal verification of VHDL-AMS descriptions.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
29	Jochen Mades, Diana Estévez Schwarz, Manfred Glesner	A discrete algorithm for the regularization of hierarchical VHDL-AMS models.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
29	Gunter Krampl, Marco Rona, Hermann Tauber	Test Setup Simulation - A High-Performance VHDL-Based Virtual Test Solution Meeting Industrial Requirements.	ITC	2002	DBLP DOI BibTeX RDF	Mixed-Signal and Analog Test, Test Cost Reduction Techniques
29	Hamed Farshbaf, Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi	Fault Simulation for VHDL Based Test Bench and BIST Evaluation.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
29	Karim S. Karim, Peyman Servati, N. Mohan, Arokia Nathan, John A. Rowlands	VHDL-AMS modeling and simulation of a passive pixel sensor in a-Si: H technology for medical imaging.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
29	Franz Wotawa	Using Multiple Models for Debugging VHDL Designs.	IEA/AIE	2001	DBLP DOI BibTeX RDF
29	Cristiana Bolchini, R. Montandon, Fabio Salice, Donatella Sciuto	Design of VHDL-based totally self-checking finite-state machine and data-path descriptions.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
29	Eduardo J. Peralías, Antonio J. Acosta 0001, Adoración Rueda, José L. Huertas	A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters.	DATE	2000	DBLP DOI BibTeX RDF
29	B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	Speeding-Up Fault Injection Campaigns in VHDL Models.	SAFECOMP	2000	DBLP DOI BibTeX RDF
29	K. C. Chang 0001	Comment on "Event suppression by optimizing VHDL programs".	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
29	Siddika Berna Örs, Ahmet Dervisoglu	Modeling Bit Multiplication Blocks for DSP Applications Using VHDL.	EUROMICRO	1999	DBLP DOI BibTeX RDF
29	Walter Lange, Wolfgang Rosenstiel	VHDL Description and High-Level Synthesis of an ATM Layer Circuit.	EUROMICRO	1999	DBLP DOI BibTeX RDF
29	Ralf Reetz, Klaus Schneider 0001, Thomas Kropf	Formal Specification in VHDL for Hardware Verification.	DATE	1998	DBLP DOI BibTeX RDF
29	Wolfram Putzke-Röming, Martin Radetzki, Wolfgang Nebel	A Flexible Message Passing Mechanism for Objective VHDL.	DATE	1998	DBLP DOI BibTeX RDF	object-oriented hardware modelling, communication, message passing
29	Felix Nicoli	Denotational Semantics of a Behavioral Subset of VHDL.	DATE	1998	DBLP DOI BibTeX RDF
29	George Economakos, George K. Papakonstantinou	Exploiting the Use of VHDL Specifications in the AGENDA High-Level Synthesis Environment.	EUROMICRO	1998	DBLP DOI BibTeX RDF
29	David Déharbe, Subash Shankar, Edmund M. Clarke	Model Checking VHDL with CV.	FMCAD	1998	DBLP DOI BibTeX RDF
29	Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto	Implicit test generation for behavioral VHDL models.	ITC	1998	DBLP DOI BibTeX RDF
29	Michael Münch, Norbert Wehn, Manfred Glesner	An efficient ILP-based scheduling algorithm for control-dominated VHDL descriptions.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	scheduling, timing constraints, integer linear programming (ILP)
29	Peter A. Walker, Sumit Ghosh	VHDL extensions for complex transmission line simulation.	ED&TC	1997	DBLP DOI BibTeX RDF
29	Kwang-Il Park, Jun Sung Kim, Heung Bum Kim, Jong Hyuk Choi, Kyu Ho Park	The Acceleration of VHDL Simulation by Classifying Events.	Annual Simulation Symposium	1997	DBLP DOI BibTeX RDF
29	James R. Armstrong, Geoff Frank, F. Gail Gray	Efficient approaches to testing VHDL DSP models.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
29	Naren Narasimhan, Ranga Vemuri, Jay Roy	Synchronous Controller Models for Synthesis from Communicating VHDL Processes.	VLSI Design	1996	DBLP DOI BibTeX RDF
29	Kuochen Wang, Sy-Yen Kuo	Computer-aided modeling and evaluation of reconfigurable VLSI processor arrays with VHDL.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
29	Vijay Nagasamy, Neerav Berry, Carlos Dangelo	Specification, Planning, and Synthesis in a VHDL Design Environment.	IEEE Des. Test Comput.	1992	DBLP DOI BibTeX RDF
29	Vijay Pitchumani, Pankaj Mayor, Nimish Radia	A VHDL Fault Diagnosis Tool Using Functional Fault Models.	IEEE Des. Test Comput.	1992	DBLP DOI BibTeX RDF
29	Raul Camposano, Larry F. Saunders, Raja M. Tabet	VHDL as Input for High-Level Synthesis.	IEEE Des. Test Comput.	1991	DBLP DOI BibTeX RDF
29	Joanne DeGroat	Transparent Logic Modeling in VHDL.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
29	C. O. Newton, M. G. Hill	Comparison of implementations of real arithmetic in ELLA and VHDL.	EURO-DAC	1990	DBLP DOI BibTeX RDF
29	Rodney Farrow, Alec G. Stanculescu	A VHDL Compiler Based on Attribute Grammar Methodology.	PLDI	1989	DBLP DOI BibTeX RDF
29	Jayaram Bhasker	Implementation of an optimizing compiler for VHDL.	ACM SIGPLAN Notices	1988	DBLP DOI BibTeX RDF
29	Kwanghyun Kim, Joseph G. Tront, Dong Sam Ha	Automatic Insertion of BIST Hardware Using VHDL.	DAC	1988	DBLP BibTeX RDF
29	Larry F. Saunders	The IBM VHDL Design System.	DAC	1987	DBLP DOI BibTeX RDF
29	David Navarro, D. Ramat, Fabien Mieyeville, Ian O'Connor, Frédéric Gaffiot, Laurent Carrel	VHDL & VHDL-AMS Modelling and Simulation of a CMOS Imager IP.	FDL	2005	DBLP BibTeX RDF
29	Michael Schlegel, Göran Herrmann, Dietmar Müller 0001	Erweiterte Kostenmodellierung mit VHDL/VHDL-AMS.	MBMV	2004	DBLP BibTeX RDF
29	Christophe Paoli	Validation de descriptions VHDL fondée sur des techniques issues du domaine du test de logiciels. (Validation of VHDL descriptions based on software testing techniques).		2001	RDF
29	Martin Radetzki, Wolfram Putzke-Röming, Wolfgang Nebel	Übersetzung von Objektorientiertem VHDL nach Standard VHDL.	MBMV	1998	DBLP BibTeX RDF
29	Adel Changuel	Prototypage rapide d'architectures mixtes logiciels/matériels à partir de modèles mixtes C-VHDL. (Rapid prototyping of mixed hw/sw architectures from mixed c/vhdl models).		1996	RDF
29	Valentina Salapura, Volker Hamann	Implementing fuzzy control systems using VHDL and statecharts.	EURO-DAC	1996	DBLP DOI BibTeX RDF
29	Maher Rahmouni, Ahmed Amine Jerraya, Polen Kission, Antonio Carneiro de Mesquita Filho, Aloysio Pedroza, Luci Pirmez	Analysis of different protocol description styles in VHDL for high-level synthesis.	EURO-DAC	1996	DBLP DOI BibTeX RDF
29	Gunther Lehmann, Klaus D. Müller-Glaser, Bernhard Wunder	A VHDL reuse workbench.	EURO-DAC	1996	DBLP DOI BibTeX RDF
29	Claus Schneider, Wolfgang Ecker	Stepwise refinement of behavioral VHDL specifications by separation of synchronization and functionality.	EURO-DAC	1996	DBLP DOI BibTeX RDF
29	Michael Gschwind, Dietmar Maurer	An extendable MIPS-I processor kernel in VHDL for hardware/software co-design.	EURO-DAC	1996	DBLP DOI BibTeX RDF
29	Franz J. Rammig	Beyond VHDL: textual formalisms, visual techniques, or both?	EURO-DAC	1996	DBLP DOI BibTeX RDF
29	Francesco Curatelli, Marco Chirico, Leonardo Mangeruca	Specification and management of timing constraints in behavioral VHDL.	EURO-DAC	1996	DBLP DOI BibTeX RDF
29	Ekambaram Balaji, Prabhu Krishnamurthy	Modeling ASIC memories in VHDL.	EURO-DAC	1996	DBLP DOI BibTeX RDF
29	Enrico Macii, Massimo Poncino, Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto	BDD-based testability estimation of VHDL designs.	EURO-DAC	1996	DBLP DOI BibTeX RDF
29	Peter T. Breuer, Carlos Delgado Kloos, Natividad Martínez Madrid, Luis Sánchez, Andrés Marín	A refinement calculus for VHDL.	EURO-DAC	1996	DBLP DOI BibTeX RDF
29	Paolo Prinetto, Alfredo Benso, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Arturo M. Amendola, Leonardo Impagliazzo, P. Marmo	Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experiment.	EURO-DAC	1996	DBLP DOI BibTeX RDF
29	C.-J. Richard Shi	Entity overloading for mixed-signal abstraction in VHDL.	EURO-DAC	1996	DBLP DOI BibTeX RDF
29	Wendell C. Baker, A. Richard Newton	The maximal VHDL subset with a cycle-level abstraction.	EURO-DAC	1996	DBLP DOI BibTeX RDF
29	Teresa Riesgo, Javier Uceda	A fault model for VHDL descriptions at the register transfer level.	EURO-DAC	1996	DBLP DOI BibTeX RDF
29	Krzysztof Bilinski, Erik L. Dagless, Jaroslaw Mirkowski	Synchronous parallel controller synthesis from behavioural multiple-process VHDL description.	EURO-DAC	1996	DBLP DOI BibTeX RDF
29	Kevin O'Brien, Serge Maginot, Anne Robert	Towards maximising the use of structural VHDL for synthesis.	EURO-DAC	1996	DBLP DOI BibTeX RDF
29	Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli	Hardware/software partitioning of VHDL system specifications.	EURO-DAC	1996	DBLP DOI BibTeX RDF