Search results for "adder"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
43	Ashis Kumer Biswas, Md. Mahmudul Hasan, Moshaddek Hasan, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu	A Novel Approach to Design BCD Adder and Carry Skip BCD Adder.	VLSI Design	2008	DBLP DOI BibTeX RDF
43	Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury	Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder.	VLSI Design	2005	DBLP DOI BibTeX RDF
43	John P. Fishburn	A Depth-Decreasing Heuristic for Combinational Logic: Or How To Convert a Ripple-Carry Adder Into A Carry-Lookahead Adder Or Anything in-between.	DAC	1990	DBLP DOI BibTeX RDF
41	Liang-Kai Wang, Michael J. Schulte, John D. Thompson, Nandini Jairam	Hardware Designs for Decimal Floating-Point Addition and Related Operations.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
41	Ajay Kumar Verma, Philip Brisk, Paolo Ienne	Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design.	DATE	2008	DBLP DOI BibTeX RDF
41	Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas	Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format.	ISVLSI	2007	DBLP DOI BibTeX RDF
41	Jiajia Chen 0002, Chip-Hong Chang, A. Prasad Vinod 0001	Design of High-speed, Low-power FIR Filters with Fine-grained Cost Metrics.	APCCAS	2006	DBLP DOI BibTeX RDF
41	Shaoqiang Bi, Warren J. Gross, Wei Wang 0003, Asim J. Al-Khalili, M. N. S. Swamy	An Area-Reduced Scheme for Modulo 2n-1 Addition/Subtraction.	IWSOC	2005	DBLP DOI BibTeX RDF
41	Ramin Rafati, A. Z. Charaki, G. R. Chaji, Seid Mehdi Fakhraie, Kenneth Carless Smith	Comparison of a 17 b multiplier in Dual-rail domino and in Dual-rail D3L (D4L) logic styles.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
41	Gin Yee, Carl Sechen	Clock-delayed domino for dynamic circuit design.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
41	José Fernández Ramos, Alfonso Gago Bohórquez	Two Operand Binary Adders with Threshold Logic.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	neural networks, logic design, computer arithmetic, Threshold logic, threshold gate, binary adders
40	Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet	Ultra-Low Voltage Subthreshold Binary Adder Architectures for IoT Applications: Ripple Carry Adder or Kogge Stone Adder.	NORCAS	2019	DBLP DOI BibTeX RDF
38	Toshinori Sato, Shingo Watanabe	Instruction Scheduling for Variation-Originated Variable Latencies.	ISQED	2008	DBLP DOI BibTeX RDF	variable latency adder, long latency adder, instruction criticality, microprocessors, parameter variations
38	Wen-Chang Yeh, Chein-Wei Jen	Generalized Earliest-First Fast Addition Algorithm.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Carry-propagation adder, final adder, conditional-sum, carry-lookahead
38	Mallika De, Bhabani P. Sinha	Testing of a parallel ternary multiplier using I2L logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	integrated injection logic, parallel ternary multiplier, I/sup 2/L logic, multivalued I/sup 2/L circuits, input balanced ternary full adder, precarry generator, multivalued current inputs, multivalued current outputs, generated test sets, skew fault, fault diagnosis, logic testing, design for testability, logic design, digital arithmetic, fault location, stuck-at fault, generalized model, adders, adder, multiplying circuits, multivalued logic circuits, test sets, parallel multiplier
38	P. Balasubramanian 0001, David A. Edwards, Charlie Brej	Self-timed full adder designs based on hybrid input encoding.	DDECS	2009	DBLP DOI BibTeX RDF
38	Vahid Moalemi, Ali Afzali-Kusha	Subthreshold 1-Bit Full Adder Cells in sub-100 nm Technologies.	ISVLSI	2007	DBLP DOI BibTeX RDF
38	Amir Agah, Seid Mehdi Fakhraie, Azita Emami-Neyestanak	Tertiary-Tree 12-GHz 32-bit Adder in 65nm Technology.	ISCAS	2007	DBLP DOI BibTeX RDF
38	John Moskal, Erdal Oruklu, Jafar Saniie	Design and Synthesis of a Carry-Free Signed-Digit Decimal Adder.	ISCAS	2007	DBLP DOI BibTeX RDF
38	Massimo Alioto, Gaetano Palumbo	High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology.	ISCAS	2007	DBLP DOI BibTeX RDF
38	Guy Even	On Teaching Fast Adder Designs: Revisiting Ladner & Fischer.	Essays in Memory of Shimon Even	2006	DBLP DOI BibTeX RDF
38	V. S. Kanchana Bhaaskaran, S. Salivahanan, D. S. Emmanuel	Semi-Custom Design of Adiabatic Adder Circuits.	VLSI Design	2006	DBLP DOI BibTeX RDF
38	Sheng Sun, Yi Han, Xinyu Guo, Kian Haur Chong, Larry McMurchie, Carl Sechen	409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS.	ISVLSI	2005	DBLP DOI BibTeX RDF
38	Yajuan He, Chip-Hong Chang, Jiangmin Gu	An area efficient 64-bit square root carry-select adder for low power applications.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
38	Ilham Hassoune, Amaury Nève, Jean-Didier Legat, Denis Flandre	Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell.	PATMOS	2004	DBLP DOI BibTeX RDF
38	Peter Celinski, Sorin Cotofana, Derek Abbott	A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder.	IWANN (2)	2003	DBLP DOI BibTeX RDF
38	Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy 0001	Low Power Adder with Adaptive Supply Voltage.	ICCD	2003	DBLP DOI BibTeX RDF
38	Mingyan Zhang, Jiangmin Gu, Chip-Hong Chang	A novel hybrid pass logic with static CMOS output drive full-adder cell.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
38	Mohammed Sayed, Wael M. Badawy	Performance analysis of single-bit full adder cells using 0.18, 0.25, and 0.35 µm CMOS technologies.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
38	Daniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel	A New Self-Checking Code-Disjoint Carry-Skip Adder.	IOLTW	2002	DBLP DOI BibTeX RDF
38	Javier D. Bruguera, Tomás Lang	Multilevel Reverse-Carry Adder.	ICCD	2000	DBLP DOI BibTeX RDF
38	Robin R.-B. Sheen, S. Wang, Oscal T.-C. Chen, Ruey-Liang Ma	Power consumption of a 2's complement adder minimized by effective dynamic data ranges.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
38	James Jacob, P. Srinivas Sivakumar, Vishwani D. Agrawal	Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs.	VLSI Design	1997	DBLP DOI BibTeX RDF
36	Mateus Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001	Design of a radix-2m hybrid array multiplier using carry save adder format.	SBCCI	2005	DBLP DOI BibTeX RDF	hybrid multiplier, low power, carry save adder
36	Yiran Chen 0001, Hai Li 0001, Kaushik Roy 0001, Cheng-Kok Koh	Cascaded carry-select adder (C2SA): a new structure for low-power CSA design.	ISLPED	2005	DBLP DOI BibTeX RDF	low-power, carry-select adder
36	Mário C. B. Osorio, Carlos A. Sampaio, André Inácio Reis, Renato P. Ribas	Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logic.	SBCCI	2004	DBLP DOI BibTeX RDF	ECDL, CMOS, adder, digital circuits
36	Kuo-Hsing Cheng, Shun-Wen Cheng, Chan-Wei Huang	64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design.	IWSOC	2004	DBLP DOI BibTeX RDF	conditional carry, hybrid dual-threshold voltage, CMOS, VLSI design, Adder
36	Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder	Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices.	ISMVL	2000	DBLP DOI BibTeX RDF	signed-digit adder, negative differential-resistance devices, NDR devices, multiple-valued logic, resonant-tunneling diodes, redundant number systems, RTDs
36	Naofumi Takagi, Takashi Horiyama	A High-Speed Reduced-Size Adder Under Left-to-Right Input Arrival.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	on-the-fly conversion, adder, Arithmetic circuit, divider
36	D. V. Poornaiah, P. V. Ananda Mohan	A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications.	VLSI Design	1996	DBLP DOI BibTeX RDF	concurrent dual multiplier-dual adder architecture, video coding applications, high-throughput image coding, carry-save 4:2 compressors, computational complexity, VLSI, VLSI, data compression, video coding, adders, computation time, multiplying circuits, digital signal processing chips
32	Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo	Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition.	DSD	2007	DBLP DOI BibTeX RDF
32	Himanshu Thapliyal, A. Prasad Vinod 0001	Designing Efficient Online Testable Reversible Adders With New Reversible Gate.	ISCAS	2007	DBLP DOI BibTeX RDF
32	Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano	Localization of Faults in Radix-n Signed Digit Adders.	IOLTS	2006	DBLP DOI BibTeX RDF
32	Peter-Michael Seidel, Guy Even	Delay-Optimized Implementation of IEEE Floating-Point Addition.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	IEEE rounding, dual path algorithm, optimized gate sizing, buffer insertion, delay optimization, logical effort, Floating-point addition
32	William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang 0006, Marek A. Perkowski	Quantum logic synthesis by symbolic reachability analysis.	DAC	2004	DBLP DOI BibTeX RDF	model checking, formal verification, quantum computing, satisfiability, reversible logic
32	Oscal T.-C. Chen, Sandy Wang, Yi-Wen Wu	Minimization of switching activities of partial products for designing low-power multipliers.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
32	Bibhudatta Sahoo 0002, Keshab K. Parhi	A Low Power Correlator for CDMA Wireless Systems.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	low-power, correlator, CDMA, incrementer
32	Whitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander Jr.	Quadruple Time Redundancy Adders.	DFT	2003	DBLP DOI BibTeX RDF
32	Hoang Q. Dao, Vojin G. Oklobdzija	Performance Comparison of VLSI Adders Using Logical Effort.	PATMOS	2002	DBLP DOI BibTeX RDF
32	Peter-Michael Seidel, Guy Even	On the Design of Fast IEEE Floating-Point Adders.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
32	Bibhudatta Sahoo 0002, Martin Kuhlmann, Keshab K. Parhi	A low-power correlator.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
32	Bernd Becker 0001, Rolf Drechsler, Sudhakar M. Reddy	(Quasi-) Linear Path Delay Fault Tests for Adders.	VLSI Design	1997	DBLP DOI BibTeX RDF
32	Bernd Becker 0001	Efficient Testing of Optimal Time Adders (Extended Abstract).	MFCS	1986	DBLP DOI BibTeX RDF
31	Robert T. Grisamore, Earl E. Swartzlander Jr.	Negative Save Sign Extension for Multi-term Adders and Multipliers.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	adder trees, multi-term adders, two’s complement arithmetic, sign extension, multipliers
31	Mohammad D. Mottaghi, Ali Afzali-Kusha, Zainalabedin Navabi	ByZFAD: a low switching activity architecture for shift-and-add multipliers.	SBCCI	2006	DBLP DOI BibTeX RDF	adder bypass, byZFAD, hot-block ring counter, shiftand-add multiplier, low-power, switching activity
31	Bong-Il Park, In-Cheol Park, Chong-Min Kyung	A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders.	ICCD	1999	DBLP DOI BibTeX RDF	Booth algorithm, Carry-Save Adder and Wallace Tree, Multiplier
30	Stamatis Vassiliadis, James Phillips, Bart Blaner	Interlock Collapsing ALU's.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	interlocked fixed point arithmetic logic unit, unsigned binary, binary logical operations, single instruction execution, machine cycle, architectural compatibility, parallel processing, digital arithmetic, adders, CMOS integrated circuits, CMOS technology, carry-save adder, carry-lookahead adder, two's complement
30	Bernd Becker 0001	Efficient Testing of Optimal Time Adders.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	optimal time adders, conditional sum adder, VLSI, logic testing, adders, integrated logic circuits, VLSI chip, carry look-ahead adder
30	Antonis M. Paschalis, Dimitris Nikolos, Constantine Halatsis	Efficient Modular Design of TSC Checkers for M-out-of-2M Codes.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	half-adder, VLSI MOS implementation, logic design, trees, codes, codes, adders, modular design, totally self-checking checkers, full-adder
29	Alireza Namazi, Seyed Ghassem Miremadi, Alireza Ejlali	A High Speed and Low Cost Error Correction Technique for the Carry Select Adder.	ARES	2009	DBLP DOI BibTeX RDF
29	Jie Shao, Ning Ye, Xiao-Yan Zhang	An IEEE Compliant Floating-Point Adder with the Deeply Pipelining Paradigm on FPGAs.	CSSE (4)	2008	DBLP DOI BibTeX RDF
29	Eduardo Mesquita, Helen Franck, Luciano Volcan Agostini, José Luís Güntzel	RIC Fast Adder and its Set Tolerant Implementation in FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
29	Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, Rajesh Ananthraman	Robust Energy-Efficient Adder Topologies.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
29	Jon Alfredsson, Snorre Aunet, Bengt Oelmann	Small Fan-in Floating-Gate Circuits with Application to an Improved Adder Structure.	VLSI Design	2007	DBLP DOI BibTeX RDF
29	Keivan Navi, Omid Kavehei, Mahnoush Rouholamini, Amir Sahafi, Shima Mehrabi	A Novel CMOS Full Adder.	VLSI Design	2007	DBLP DOI BibTeX RDF
29	Massimo Alioto, Gaetano Palumbo	Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
29	Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi 0001	Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic.	ISMVL	2006	DBLP DOI BibTeX RDF
29	Henning Gundersen, Yngvar Berg	A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices.	ISMVL	2006	DBLP DOI BibTeX RDF
29	Douglas L. Maskell, Jussipekka Leiwo, Jagdish Chandra Patra	The design of multiplierless FIR filters with a minimum adder step and reduced hardware complexity.	ISCAS	2006	DBLP DOI BibTeX RDF
29	Ali Malik, Seok-Bum Ko	A Study on the Floating-Point Adder in FPGAS.	CCECE	2006	DBLP DOI BibTeX RDF
29	Neil Burgess	Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
29	Neil Burgess	New Models of Prefix Adder Topologies.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	prefix addition, absolute difference, VLSI, delay model, idempotency
29	Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo	Fast Low-Power 64-Bit Modular Hybrid Adder.	PATMOS	2005	DBLP DOI BibTeX RDF
29	Xinyu Guo, Carl Sechen	High Speed Redundant Adder and Divider in Output Prediction Logic.	ISVLSI	2005	DBLP DOI BibTeX RDF
29	Arjun K. Pai, Khaled Benkrid, Danny Crookes	Embedded Reconfigurable DCT Architectures Using Adder-Based Distributed Arithmetic.	CAMP	2005	DBLP DOI BibTeX RDF
29	Chi Huang, Xinyu Wu, Jinmei Lai, Chengshou Sun, Gang Li	A design of high speed double precision floating point adder using macro modules.	ASP-DAC	2005	DBLP DOI BibTeX RDF
29	Song Peng, Rajit Manohar	Fault Tolerant Asynchronous Adder through Dynamic Self-reconfiguration.	ICCD	2005	DBLP DOI BibTeX RDF
29	Toshiro Akino, Kei Matsuura, Akiyoshi Yasunaga	A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverter.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
29	John D. Thompson, Nandini Karra, Michael J. Schulte	A 64-bit Decimal Floating-Point Adder.	ISVLSI	2004	DBLP DOI BibTeX RDF
29	Aamir A. Farooqui, Vojin G. Oklobdzija, Sadiq M. Sait	Area-time optimal adder with relative placement generator.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
29	Amaury Nève, Denis Flandre, Helmut Schettler, Thomas Ludwig 0004, Gerhard Hellner	Design of a branch-based 64-bit carry-select adder in 0.18 µm partially depleted SOI CMOS.	ISLPED	2002	DBLP DOI BibTeX RDF	SOI technology, logic design styles, circuit Design
29	Andrew Beaumont-Smith, Cheng-Chew Lim	Parallel Prefix Adder Design.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
29	Henrik Eriksson, Per Larsson-Edefors, Atila Alvandpour	A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
29	Oscar Gustafsson, Henrik Ohlsson, Lars Wanhammar	Minimum-adder integer multipliers using carry-save adders.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
29	Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan	Code-Disjoint Carry-Dependent Sum Adder with Partial Look-Ahead.	IOLTW	2001	DBLP DOI BibTeX RDF
29	Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra	Novel Fault-Tolerant Adder Design for FPGA-Based Systems.	IOLTW	2001	DBLP DOI BibTeX RDF
29	Sheng Sun, Larry McMurchie, Carl Sechen	A High-Performance 64-bit Adder Implemented in Output Prediction Logic.	ARVLSI	2001	DBLP DOI BibTeX RDF
29	Asger Munk Nielsen, David W. Matula, Chung Nan Lyu, Guy Even	An IEEE Compliant Floating-Point Adder that Conforms with the Pipelined Packet-Forwarding Paradigm.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	IEEE floating-point rounding, Floating-point arithmetic, redundant number representations, floating-point addition
29	Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo	VLSI Implementation of a Low-Power High-Speed Self-Timed Adder.	PATMOS	2000	DBLP DOI BibTeX RDF
29	Ahmed M. Shams, Magdy A. Bayoumi	Performance evaluation of 1-bit CMOS adder cells.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
29	Philippe Royannez, Amara Amara	A 1.0ns 64-bits GaAs Adder using Quad tree algorithm.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
29	Vojin G. Oklobdzija, David Villeger	Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
29	Stefan Gerber 0002, Michael Gössel	Detection of Permanent Hardware Faults of a Floating Point Adder by Pseudoduplication.	EDCC	1994	DBLP DOI BibTeX RDF
28	Hung-Yu Wang, Chun-Wei Chiu, Hung-Yuan Tseng, Hsieh-Wei Lee	Design of Low Adder Cost FIR Digital Filters Using Graph Representation.	ICGEC	2011	DBLP DOI BibTeX RDF	Adder cost, Digital filter, Graph representation
28	Gang Chen 0004, Feng Liu 0029	Proofs of Correctness and Properties of Integer Adder Circuits.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	adder circuits, Formal method, computer arithmetic
28	Lihui Ni, Zhijin Guan, Wenying Zhu	A General Method of Constructing the Reversible Full-Adder.	IITSI	2010	DBLP DOI BibTeX RDF	reversible full-adder, reversible gates, gate count, garbage outputs
28	Ching-Hwa Cheng, Chiou-Kou Tung, Shao-Hui Shieh, Yu-Cherng Hung	Design High-Performance and Low-Power Adder Cores with Full-Swing Nodes for Embedded Systems.	IIH-MSP	2009	DBLP DOI BibTeX RDF	Embedded System, Low Power, Adder
28	Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka	A fast hybrid carry-lookahead/carry-select adder design.	ACM Great Lakes Symposium on VLSI	2001	DBLP DOI BibTeX RDF	CMOS, domino logic, carry lookahead adder
28	Ranjeet Ranade, Sanjay Bhandari, A. N. Chandorkar	VLSI Implementation of Artificial Neural Network Based Digital Multiplier and Adder.	VLSI Design	1996	DBLP DOI BibTeX RDF	Digital Multiplier and Adder, VLSI Implementation of Neural Networks, Artificial Neural Networks (ANN)
28	John J. Shedletsky	Comment on the Sequential and Indeterminate Behavior of an End-Around-Carry Adder.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	End-around-carry (EAC) adder, negative zero, one's complement arithmetic