Search results for "Carry"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
20	Antonio Blotti, Maurizio Castellucci, Roberto Saletti	Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library.	PATMOS	2002	DBLP DOI BibTeX RDF
20	Amaury Nève, Denis Flandre, Helmut Schettler, Thomas Ludwig 0004, Gerhard Hellner	Design of a branch-based 64-bit carry-select adder in 0.18 µm partially depleted SOI CMOS.	ISLPED	2002	DBLP DOI BibTeX RDF	SOI technology, logic design styles, circuit Design
20	Peter Celinski, Said F. Al-Sarawi, Derek Abbott, José Francisco López	Low depth carry lookahead addition using charge recycling threshold logic.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
20	Daniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel	A New Self-Checking Code-Disjoint Carry-Skip Adder.	IOLTW	2002	DBLP DOI BibTeX RDF
20	Youngtae Kim, Taewhan Kim	Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders.	ASP-DAC	2001	DBLP DOI BibTeX RDF
20	Vitalij Ocheretnij, Egor S. Sogomonyan, Michael Gössel	A New Code-Disjoint Sum-Bit Duplicated Carry Look-Ahead Adder for Parity Codes.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
20	Xiaoling Sun, Jian Xu, Pieter M. Trouborst	Testing Carry Logic Modules of SRAM-based FPGAs.	MTDT	2001	DBLP DOI BibTeX RDF
20	Chua-Chin Wang, Po-Ming Lee, Rong-Chin Lee, Chenn-Jung Huang	A 1.25 GHz 32-bit tree-structured carry lookahead adder.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
20	Xiaoling Sun, Jian Xu, Pieter M. Trouborst	Testing Xilinx XC4000 Configurable Logic Blocks with Carry Logic Modules.	DFT	2001	DBLP DOI BibTeX RDF	configurable logic blocks, fault diagnosis, BIST, FPGA testing
20	Athanasios Kakarountas, Kyriakos Papadomanolakis, Vasileios Kokkinos, Constantinos E. Goutis	Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance.	PATMOS	2000	DBLP DOI BibTeX RDF
20	Hyuk-Jun Lee, Michael J. Flynn	Coarse-grained carry architecture for FPGA (poster abstract).	FPGA	2000	DBLP DOI BibTeX RDF
20	Andreas Herrfeld, Siegbert Hentschke	Ternary Multiplication Circuits Using 4-Input Adder Cells and Carry Look-Ahead.	ISMVL	1999	DBLP DOI BibTeX RDF	MVL, ternary adder, ternary multiplication, VLSI, multiple valued-logic
20	Kei-Yong Khoo, Chao-Liang Chen, Alan N. Willson Jr.	A CMOS pipelined carry-save array using true single-phase single-transistor-latch clocking.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
20	Sae Hwan Kim, Shiu-Kai Chin	Formal Verification of Tree-Structured Carry-Lookahead Adders.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
20	Franck Multon, Jean-Luc Nougaret, Gérard Hégron, Luc Millet, Bruno Arnaldi	A Software System to Carry-out Virtual Experiments on Human Motion.	CA	1999	DBLP DOI BibTeX RDF
20	Taewhan Kim, William Jao, Steven W. K. Tjiang	Circuit optimization using carry-save-adder cells.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
20	Taewhan Kim, William Jao, Steven W. K. Tjiang	Arithmetic Optimization Using Carry-Save-Adders.	DAC	1998	DBLP DOI BibTeX RDF	transceiver, spread spectrum communication, RF CMOS, digital radio, ISM frequency band
20	Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald, Wen-Chung Cho	Delay-Insensitive Carry-Lookahead Adders.	VLSI Design	1997	DBLP DOI BibTeX RDF
20	Palash Sarkar 0001, Bimal K. Roy, Pabitra Pal Choudhury	VLSI Implementation of Modulo Multiplication Using Carry Free Addition.	VLSI Design	1997	DBLP DOI BibTeX RDF
20	Chin-Long Wey	Built-in self-test (BIST) design of high-speed carry-free dividers.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
20	Daniel Etiemble, Keivan Navi	Algorithms and multi-valued circuits for the multioperand addition in the binary stored-carry number system.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
19	Mark Goresky, Andrew Klapper	Some Results on the Arithmetic Correlation of Sequences.	SETA	2008	DBLP DOI BibTeX RDF	correlation, sequences, pseudo-randomness, feedback with carry shift register
19	Yanqing Cui, Jan Chipchase, Fumiko Ichikawa	A Cross Culture Study on Phone Carrying and Physical Personalization.	HCI (10)	2007	DBLP DOI BibTeX RDF	Mobile Essentials, Carry-ing, Personalization, Mobile Phone, User Experience, Culture
19	Ajay Kumar Verma, Paolo Ienne	Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands.	ASP-DAC	2007	DBLP DOI BibTeX RDF	multiplier-like circuits, XOR-dominated circuits, datapath design, netlist optimization, carry-save form, column compressors, XOR operations, logic synthesizers, algebraic factoring, computer arithmetic, logic synthesis, digital design, parallel multipliers
19	Hong Xu 0008, Wen-Feng Qi 0001	On the Distinctness of Decimations of Generalized l-Sequences.	SETA	2006	DBLP DOI BibTeX RDF	Feedback-with-carry shift registers (FCSRs), l-sequences, generalized l-sequences, integer residue ring, primitive sequences, 2-adic numbers
19	Bonseok Koo, Dongwook Lee, Gwonho Ryu, Taejoo Chang, Sangjin Lee 0002	High-Speed RSA Crypto-processor with Radix-4 Modular Multiplication and Chinese Remainder Theorem.	ICISC	2006	DBLP DOI BibTeX RDF	Booth’s algorithm, RSA, Chinese Remainder Theorem, Montgomery multiplication, Carry Save Adder
19	Birgit Graf, Matthias Hans, Rolf Dieter Schraft	Care-O-bot II-Development of a Next Generation Robotic Home Assistant.	Auton. Robots	2004	DBLP DOI BibTeX RDF	Robotic Home Assistant, Walking Aid, Path Modification, Fetch and Carry Tasks, User Interface, Path Planning, Service Robot, Object Manipulation, Task Planning
19	Viktor Bunimov, Manfred Schimmler	Efficient Parallel Multiplication Algorithm for Large Integres.	Euro-Par	2003	DBLP DOI BibTeX RDF	large number arithmetic, redundant numbers, Computer arithmetic, integer multiplication, carry save addition, parallel multiplication
19	Jongsun Park 0001, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy 0001	High performance and low power FIR filter design based on sharing multiplication.	ISLPED	2002	DBLP DOI BibTeX RDF	FIR filter design, computation sharing, conditional capture flip-flop, high performance and low power carry select adder
19	Junhyung Um, Taewhan Kim	Layout-aware synthesis of arithmetic circuits.	DAC	2002	DBLP DOI BibTeX RDF	layout, high performance, carry-save-adder
19	Juan A. Montiel-Nelson, Saeid Nooshabadi, V. de Armas, Roberto Sarmiento, Antonio Núñez	High Speed GaAs Subsystem Design using Feed Through Logic.	DATE	1999	DBLP DOI BibTeX RDF	GaAs fast arithmetic circuits, GaAs design methodologies, GaAs subsystem design, GaAs ripple-carry adders, GaAs magnitude comparators
19	Eugen Ettelt, Ralf Furtwängler, Uwe D. Hanebeck, Günther Schmidt	Design Issues of a Semi-Autonomous Robotic Assistant for the Health Care Environment.	J. Intell. Robotic Syst.	1998	DBLP DOI BibTeX RDF	mobile service robot, fetch-and-carry task, augmented virtual workspace, health care, mobile manipulation, human-robot interface, robotic assistant
19	Steven M. Nowick, Kenneth Y. Yun, Ayoob E. Dooply, Peter A. Beerel	Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders.	ASYNC	1997	DBLP DOI BibTeX RDF	completion detection, Brent-Kung, Carry-Bypass, asynchronous, adders, hazards, high-performance design
19	S. Ramanathan, V. Visvanathan	A systolic architecture for LMS adaptive filtering with minimal adaptation delay.	VLSI Design	1996	DBLP DOI BibTeX RDF	LMS adaptive filtering, minimal adaptation delay, convergence behaviour, function preserving transformations, SFG representation, carry-save arithmetic, systolic folded pipelined architecture, VLSI, delays, systolic arrays, pipeline processing, adaptive filters, digital filters, digital signal processing chips, convergence of numerical methods, systolic architecture, signal flow graphs, signal flow graph, least mean squares methods, LMS algorithm
19	D. V. Poornaiah, P. V. Ananda Mohan	A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications.	VLSI Design	1996	DBLP DOI BibTeX RDF	concurrent dual multiplier-dual adder architecture, video coding applications, high-throughput image coding, carry-save 4:2 compressors, computational complexity, VLSI, VLSI, data compression, video coding, adders, computation time, multiplying circuits, digital signal processing chips
19	Song Cui, Neil Burgess, Michael J. Liebelt, Kamran Eshraghian	A GaAs IEEE Floating Point Standard Single Precision Multiplier.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	floating point multiplier, rounding algorithm, modified carry save array, GaAs technology
19	Andrew Klapper, Mark Goresky	Large Periods Nearly de Bruijn FCSR Sequences.	EUROCRYPT	1995	DBLP DOI BibTeX RDF	deBruijn property, Binary sequences, feedback with carry shift registers, 2-adic numbers
19	Yuji Ohi, Takafumi Aoki, Tatsuo Higuchi 0001	Redundant Complex Number Systems.	ISMVL	1995	DBLP DOI BibTeX RDF	redundant complex number systems, complex number representations, high-speed arithmetic circuits, positional number system, binary-tree multiple-operand addition, arithmetic algorithms, redundant number systems, carry-free addition
19	Menghui Zheng, Alexander Albicki	Low power and high speed multiplication design through mixed number representations.	ICCD	1995	DBLP DOI BibTeX RDF	high speed multiplication, mixed number representations, low power multiplication, reduced switching, Sign-Magnitude, Redundant Binary adder, Booth decoder, Carry-Propagation-Free, digital arithmetic, VLSI architecture, redundant number systems, Partial Products
19	Hiromichi Yamada, Takashi Hotta, Takahiro Nishiyama, Fumio Murabayashi, Tatsumi Yamauchi, Hideo Sawamoto	A 13.3ns double-precision floating-point ALU and multiplier.	ICCD	1995	DBLP DOI BibTeX RDF	double-precision floating-point ALU, floating-point multiplier, carry select addition, prerounding techniques, noise tolerant precharge circuit, two-cycle latency, 13.3 ns, 0.3 micron, 2.5 V, 150 MHz, normalization, floating point arithmetic, CMOS integrated circuits, multiplying circuits, CMOS technology, arithmetic logic unit
19	Alain Guyot, Luis A. Montalvo, A. Houelle, Habib Mehrez, Nicolas Vaucher	Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers.	VLSI Design	1995	DBLP DOI BibTeX RDF	layout synthesis, radix-2 dividers, pseudo-radix-4 dividers, redundant number notation, carry-propagation-free addition/subtraction, VLSI, logic CAD, circuit layout CAD, CMOS logic circuits, VLSI implementation, integrated circuit layout, redundant number systems, dividing circuits, digit-recurrence division
19	W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi	A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging.	VLSI Design	1995	DBLP DOI BibTeX RDF	CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron
19	Sabyasachi Das, Sunil P. Khatri	A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
19	Jun-Hong Chen, Haw-Shiuan Wu, Ming-Der Shieh, Wen-Ching Lin	A New Montgomery Modular Multiplication Algorithm and its VLSI Design for RSA Cryptosystem.	ISCAS	2007	DBLP DOI BibTeX RDF
19	Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo	Fast Low-Power 64-Bit Modular Hybrid Adder.	PATMOS	2005	DBLP DOI BibTeX RDF
19	Rumi Zhang, Wei Wang 0003, Konrad Walus, Graham A. Jullien	Performance comparison of quantum-dot cellular automata adders.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
19	Abhishek Singh, Santosh Pande	Compiler optimizations for Java aglets in distributed data intensive applications.	SAC	2002	DBLP DOI BibTeX RDF	Java
19	Kamal Rajagopalan, Peter R. Sutton	A flexible multiplication unit for an FPGA logic block.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
19	Mahmoud A. Manzoul	A quaternary complex number CCD adder (abstract only).	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF
15	R. Nishanth, C. Helen Sulochana	A novel lightweight CNN-based error-reduced carry prediction approximate full adder design for multimedia applications.	Neural Comput. Appl.	2024	DBLP DOI BibTeX RDF
15	Jingxuan Yang, Xiaoqin Wang, Yiying Jiang	CANET: Quantized Neural Network Inference With 8-bit Carry-Aware Accumulator.	IEEE Access	2024	DBLP DOI BibTeX RDF
15	Melika Amiri, Massoud Dousti, Majid Mohammadi	Design and implementation of carry-save adder using quantum-dot cellular automata.	J. Supercomput.	2024	DBLP DOI BibTeX RDF
15	Maxime Remaud	Quantum Ripple-Carry Adders and Comparator.	CoRR	2024	DBLP DOI BibTeX RDF
15	Suparna Kundu, Siddhartha Chowdhury, Sayandeep Saha, Angshuman Karmakar, Debdeep Mukhopadhyay, Ingrid Verbauwhede	Carry Your Fault: A Fault Propagation Attack on Side-Channel Protected LWE-based KEM.	CoRR	2024	DBLP DOI BibTeX RDF
15	Suparna Kundu, Siddhartha Chowdhury, Sayandeep Saha, Angshuman Karmakar, Debdeep Mukhopadhyay, Ingrid Verbauwhede	Carry Your Fault: A Fault Propagation Attack on Side-Channel Protected LWE-based KEM.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2024	DBLP DOI BibTeX RDF
15	Wushuang Wang, Fei Xue, Toshiki Mitsui, Zhiyuan Shang, Maiko Shigeno	Carry-over Effect Values Minimization under Circle Method and Binary Factorization Based on Jaya Algorithm.	CCEAI	2024	DBLP DOI BibTeX RDF
15	Ayan Palchaudhuri, Anindya Sundar Dhar	FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation.	VLSID	2024	DBLP DOI BibTeX RDF
15	Satoki Tsuichihara, Masayuki Yamada, Kaito Hara, Gustavo Alfonso Garcia Ricardez, Akishige Yuguchi, Jun Takamatsu, Takahiro Wada, Yasutake Takahashi, Tsukasa Ogasawara	Holding Strategy Using Torso to Enable Humanoid Robots to Carry Heavier Objects.	SII	2024	DBLP DOI BibTeX RDF
15	Lilach Alon, Maja Krtalic	"Words Are not just Words; They Carry Experiences Within Them": Navigating Personal Information Management in Multilingual Contexts.	iConference (1)	2024	DBLP DOI BibTeX RDF
15	S. Senthilkumar, V. Samuthira Pandi, T. Sripriya, N. Pragadish	Design of recustomize finite impulse response filter using truncation based scalable rounding approximate multiplier and error reduced carry prediction approximate adder for image processing application.	Concurr. Comput. Pract. Exp.	2023	DBLP DOI BibTeX RDF
15	Perumal Mahendran, M. S. Kavitha, R. Radhika, C. Kotteeswaran	Design of all pass make over based capricious digital filter using eminent speed dual carry select adder and truncation and rounding approximate multiplier for image processing application.	Concurr. Comput. Pract. Exp.	2023	DBLP DOI BibTeX RDF
15	Afshin Khaksari, Omid Akbari, Behzad Ebrahimi	BEAD: Bounded error approximate adder with carry and sum speculations.	Integr.	2023	DBLP DOI BibTeX RDF
15	Jeyakumar Ponraj, R. Jeyabharath, P. Veena, Tharumar Srihari	High-performance multiply-accumulate unit by integrating binary carry select adder and counter-based modular wallace tree multiplier for embedding system.	Integr.	2023	DBLP DOI BibTeX RDF
15	Ke Cui, Jintao Yu, Jiaxuan Zou, Xiangyu Li 0005	A High-Resolution TDC Design Based on Multistep Fine Time Measurement by Utilizing Delay-Adjustable Looped Carry Chains on FPGAs.	IEEE Trans. Instrum. Meas.	2023	DBLP DOI BibTeX RDF
15	Umberto Garlando, Qi Wang, Oleksandr V. Dobrovolskiy, Andrii V. Chumak, Fabrizio Riente	Numerical Model for 32-Bit Magnonic Ripple Carry Adder.	IEEE Trans. Emerg. Top. Comput.	2023	DBLP DOI BibTeX RDF
15	Chua-Chin Wang, Oliver Lexter July A. Jose, Wen-Shou Yang, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tzung-Je Lee	A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
15	K. Saritha Raj, P. Rajesh Kumar, M. Satyanarayana	Capricious Digital Filter Design and Implementation Using Baugh-Wooley Multiplier and Error Reduced Carry Prediction Approximate Adder for ECG Noise Removal Application.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
15	Huigyu Yang, Syed M. Raza, Moonseong Kim, Hyunseung Choo	Deep Mobile Path Prediction With Shift-and-Join and Carry-Ahead.	IEEE Trans. Cogn. Commun. Netw.	2023	DBLP DOI BibTeX RDF
15	Sivasamy Ramasamy, David Banjerdpongchai, PooGyeon Park	Chaos Control of a Delayed Tri-Trophic Food Chain Model with Fear and Its Carry over Effects.	Symmetry	2023	DBLP DOI BibTeX RDF
15	Nima Amirafshar, Ahmad Sadigh Baroughi, Hadi Shahriar Shahhoseini, Nima TaheriNejad	Carry Disregard Approximate Multipliers.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
15	B. Jeevan, K. Bikshalu, E. Hari Krishna, Kosaraju Sivani	Design of 2-1 Multiplexer based high-speed, Two-Stage 90 nm Carry Select Adder for fast arithmetic units.	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
15	Muhammad Awais, Ali Zahir, Syed Ayaz Ali Shah, Pedro Reviriego, Anees Ullah, Nasim Ullah, Adam Khan, Hazrat Ali	Toward Optimal Softcore Carry-aware Approximate Multipliers on Xilinx FPGAs.	ACM Trans. Embed. Comput. Syst.	2023	DBLP DOI BibTeX RDF
15	K. Gavaskar, D. Malathi, G. Ravivarma, P. S. Priyatharshan, S. Rajeshwari, B. Sanjay	Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors.	Wirel. Pers. Commun.	2023	DBLP DOI BibTeX RDF
15	Wenbo Guo 0009	High-Speed (7, 2) Compressor Using A Fast Carry-Generation Logic based on Sorting Network.	CoRR	2023	DBLP DOI BibTeX RDF
15	Siyi Wang, Anubhab Baksi, Anupam Chattopadhyay	A Higher Radix Architecture for Quantum Carry-lookahead Adder.	CoRR	2023	DBLP DOI BibTeX RDF
15	Goeric Huybrechts, Srikanth Ronanki, Xilai Li, Hadis Nosrati, Sravan Bodapati, Katrin Kirchhoff	DCTX-Conformer: Dynamic context carry-over for low latency unified streaming and non-streaming Conformer.	CoRR	2023	DBLP DOI BibTeX RDF
15	Rajarshi Roy Chowdhury, Azam Che-Idris, Pg Emeroylariffion Abas	Internet of Things: Digital Footprints Carry A Device Identity.	CoRR	2023	DBLP DOI BibTeX RDF
15	Ryosuke Korekata, Motonari Kambara, Yu Yoshida, Shintaro Ishikawa, Yosuke Kawasaki, Masaki Takahashi, Komei Sugiura	Switching Head-Tail Funnel UNITER for Dual Referring Expression Comprehension with Fetch-and-Carry Tasks.	CoRR	2023	DBLP DOI BibTeX RDF
15	Motonari Kambara, Komei Sugiura	Fully Automated Task Management for Generation, Execution, and Evaluation: A Framework for Fetch-and-Carry Tasks with Natural Language Instructions in Continuous Space.	CoRR	2023	DBLP DOI BibTeX RDF
15	Seyed-Sajad Ahmadpour, Nima Jafari Navimipour, Mohammad Mosleh, Ali Newaz Bahar, Senay Yalçin	A nano-scale n-bit ripple carry adder using an optimized XOR gate and quantum-dots technology with diminished cells and power dissipation.	Nano Commun. Networks	2023	DBLP DOI BibTeX RDF
15	Maja Krtalic, Kingsley T. Ihejirika	The things we carry: migrants' personal collection management and use.	J. Documentation	2023	DBLP DOI BibTeX RDF
15	Yaacov Belenky, Ira Dushar, Valery Teper, Vadim Bugaenko, Oleg Karavaev, Leonid Azriel, Yury Kreimer	Carry-based Differential Power Analysis (CDPA) and its Application to Attacking HMAC-SHA-2.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2023	DBLP DOI BibTeX RDF
15	Suparna Kundu, Siddhartha Chowdhury, Sayandeep Saha, Angshuman Karmakar, Debdeep Mukhopadhyay, Ingrid Verbauwhede	Carry Your Fault: A Fault Propagation Attack on Side-Channel Protected LWE-based KEM.	IACR Cryptol. ePrint Arch.	2023	DBLP BibTeX RDF
15	Corey Hannum, Rui Li 0021, Weitian Wang	A Trust-Assist Framework for Human-Robot Co-Carry Tasks.	Robotics	2023	DBLP DOI BibTeX RDF
15	Ryosuke Korekata, Motonari Kambara, Yu Yoshida, Shintaro Ishikawa, Yosuke Kawasaki, Masaki Takahashi, Komei Sugiura	Switching Head-Tail Funnel UNITER for Dual Referring Expression Comprehension with Fetch-and-Carry Tasks.	IROS	2023	DBLP DOI BibTeX RDF
15	Chun Zheng, Xiafu Pan	Design of Intelligent Security Inspection System for Airport Passengers' Carry on Luggage Based on Machine Learning.	ICMTEL (1)	2023	DBLP DOI BibTeX RDF
15	Sen Hou, Yue Cao	On Searching Dynamic Feedback with Carry Shift Registers Having Sparse Switches.	ICCT	2023	DBLP DOI BibTeX RDF
15	Xuan Wang, Jia Liu, Xi Yu, Xingyu Chen, Yujie Yu, Zhihong Zhao	People Counting with Carry-on RFID Tags.	IWQoS	2023	DBLP DOI BibTeX RDF
15	Riley Jackson, Maxwell Phillips, Firas Hassan, Ahmed Ammar	High Precision Carry-Look-Ahead Logic for Negation, Absolute Value, and Two's Complement.	ICECS	2023	DBLP DOI BibTeX RDF
15	Baofeng Qi, Shaojiang Sun, Yihui Tong, Jie Zhang, Zhehe Wang, Xianchao Wang	Algorithm-based Study on Transformation Combination for Carry-free Modified Signed Digit(MSD) Addition.	CSCloud/EdgeCom	2023	DBLP DOI BibTeX RDF
15	Kshitij Sharma, Michail N. Giannakos	Carry-Forward Effect: Early scaffolding learning processes.	LDT	2023	DBLP DOI BibTeX RDF
15	Marek Nowakowski, Guido S. Berger, João Braun, João Mendes, Luciano Bonzatto Junior, José Lima 0001	Advance Reconnaissance of UGV Path Planning Using Unmanned Aerial Vehicle to Carry Our Mission in Unknown Environment.	ROBOT (2)	2023	DBLP DOI BibTeX RDF
15	Bhaskar Gaur, Edgard Muñoz-Coreas, Himanshu Thapliyal	A Logarithmic Depth Quantum Carry-Lookahead Modulo (2n - 1) Adder.	ACM Great Lakes Symposium on VLSI	2023	DBLP DOI BibTeX RDF
15	Mengfan Xu, Yuejun Zhang, Huihong Zhang, Liang Wen, Tengfei Yuan, Pengjun Wang, Zhiyi Li	Full-custom Design of Improved Carry Adder Circuit for CLBs.	ASICON	2023	DBLP DOI BibTeX RDF
15	Poh Yuin Lyn, Nor Azlin Ghazali, Mohamed Fauzi Packeer Mohamed, Muhammad Firdaus Akbar	Design of Low-Power and Area-Efficient Square Root Carry Select Adder Using Binary to Excess-1 Converter (BEC).	RoViSP	2023	DBLP DOI BibTeX RDF
15	Toshinori Sato, Hiroyuki Hama, Tomoaki Ukezono	Comparative Evaluation between Carry Prediction and Sign Error Correction in Approximate Addition.	ISOCC	2023	DBLP DOI BibTeX RDF
15	Luiz Paulo Carvalho, Rosa Maria Esteves Moreira da Costa, Flávia Maria Santoro, Jonice Oliveira	How to carry out a Brazilian research in computing considering ethical or moral aspects?	SBSI	2023	DBLP DOI BibTeX RDF
15	Jiwen Yang, Congwei Liao, Kun Wang, Junjun An, Shuai Shen, Shengdong Zhang	A-Si TFT Integrated Gate Driver Workable at -40°C Using Bootstrapped Carry Signal.	IEEE Access	2022	DBLP DOI BibTeX RDF
15	Robert B. Kent, Marios S. Pattichis	Use of Carry Chain Logic and Design System Extensions to Construct Significantly Faster and Larger Single-Stage N-Sorters and N-Filters.	IEEE Access	2022	DBLP DOI BibTeX RDF
15	Jia-Yuan Liao, Jun-Wei Hsieh, Ching-Wen Ma	Automatic Meter Reading Based on Bi-Fusion MSP Network and Carry-Out Rechecking.	IEEE Access	2022	DBLP DOI BibTeX RDF