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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 522 occurrences of 327 keywords
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Results
Found 301 publication records. Showing 301 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Tajana Simunic, Giovanni De Micheli, Luca Benini |
Event-Driven Power Management of Portable Systems. |
ISSS |
1999 |
DBLP DOI BibTeX RDF |
|
1 | Nadim Maluf |
Micro-Electromechanical Systems (MEMS): Miniaturization Beyond Microelectronics. |
ISSS |
1999 |
DBLP DOI BibTeX RDF |
|
1 | Gang Qu 0001, Malena R. Mesarina, Miodrag Potkonjak |
System Synthesis of Synchronous Multimedia Applications. |
ISSS |
1999 |
DBLP DOI BibTeX RDF |
|
1 | Shail Aditya, B. Ramakrishna Rau, Vinod Kathail |
Automatic Architectural Synthesis of VLIW and EPIC Processors. |
ISSS |
1999 |
DBLP DOI BibTeX RDF |
|
1 | Yin-Tsung Hwang, Yuan-Hung Wang |
Communication and Interface Synthesis on a Rapid Prototyping Hardware/Software Codesign System. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Takanori Okuma, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar, Hiroto Yasuura |
Instruction Encoding Techniques for Area Minimization of Instruction ROM. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Luc De Coster, Marleen Adé, Rudy Lauwereins, J. A. Peperstraete |
Code Generation for Compiled Bit-True Simulation of DSP Applications. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Rainer Leupers |
HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Frank Vahid, Tony Givargis |
Incorporating Cores into System-Level Specification. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Zhao Wu, Wayne H. Wolf |
Data-Path Synthesis of VLIW Video Signal Processors. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Karam S. Chatha, Ranga Vemuri |
A Tool for Partitioning and Pipelined Scheduling of Hardware-Software Systems. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Francky Catthoor (eds.) |
Proceedings of the 11th International Symposium on System Synthesis, ISSS '98, Hsinchu, Taiwan, December 2-4, 1998. |
ISSS |
1998 |
DBLP BibTeX RDF |
|
1 | Rainer Leupers, Fabian David |
A Uniform Optimization Technique for Offset Assignment Problems. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Ing-Jer Huang, Ping-Huei Xie |
Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Allocation. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Enrica Filippi, Luciano Lavagno, L. Licciardi, Archille Montanaro, Maurizio Paolini, Roberto Passerone, Marco Sgroi, Alberto L. Sangiovanni-Vincentelli |
Intellectual Property Re-use in Embedded System Co-design: An Industrial Case Study. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Peter Voigt Knudsen, Jan Madsen |
Integrating Communication Protocol Selection with Partitioning in Hardware/Software Codesign. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Tony Givargis, Frank Vahid |
Interface Exploration for Reduced Power in Core-Based Systems. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Wonyong Sung, Junedong Kim, Soonhoi Ha |
Memory Efficient Software Synthesis from Dataflow Graph. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Hiroyuki Tomiyama, Akihiko Inoue, Hiroto Yasuura |
Statistical Performance-Driven Module Binding in High-Level Synthesis. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Francky Catthoor, Diederik Verkest, Erik Brockmeyer |
Proposal for Unified System Design Meta Flow in Task-Level and Instruction-Level Design Technology Research for Multi-Media Applications. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Soha Hassoun |
Fine Grain Incremental Rescheduling Via Architectural Retiming. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Chuck Siska |
A Processor Description Language Supporting Retargetable Multi-Pipeline DSP Program Development Tools. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Wei-Kai Cheng, Youn-Long Lin |
Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Doris Keitel-Schulz, Norbert Wehn |
Issues in Embedded DRAM Development and Applications. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Frank Vahid |
A Three-Step Approach to the Functional Partitioning of Large Behavioral Processes. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Oliver Bringmann 0001, Wolfgang Rosenstiel, Dirk Reichardt |
Synchronization Detection for Multi-Process Hierarchical Synthesis. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Cristiana Bolchini, William Fornaciari, Fabio Salice, Donatella Sciuto |
Concurrent Error Detection at Architectural Level. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Allan Rae, Sri Parameswaran |
Application-Specific Heterogeneous Multiprocessor Synthesis Using Differential-Evolution. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Christoph Jäschke, Rainer Laur |
Resource Constrained Modulo Scheduling with Global Resource Sharing. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Apostolos A. Kountouris, Christophe Wolinski |
False Path Analysis Based on a Hierarchical Control Representation. |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
1 | Gernot Koch, Udo Kebschull, Wolfgang Rosenstiel |
Co-Emulation and Debugging of HW/SW-Systems. |
ISSS |
1997 |
DBLP DOI BibTeX RDF |
|
1 | Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess |
Constraint Analysis for DSP Code Generation. |
ISSS |
1997 |
DBLP DOI BibTeX RDF |
|
1 | Peter Slock, Sven Wuytack, Francky Catthoor, Gjalt G. de Jong |
Fast and Extensive System-Level Memory Exploration for ATM Applications. |
ISSS |
1997 |
DBLP DOI BibTeX RDF |
memory exploration, memory optimization, network applications |
1 | Robert Pasko, Patrick Schaumont, Veerle Derudder, Daniela Duracková |
Optimization Method for Broadband Modem FIR Filter Design using Common Subexpression Elimination. |
ISSS |
1997 |
DBLP DOI BibTeX RDF |
|
1 | Chih-Tung Chen, Kayhan Küçükçakar |
A Source-Level Dynamic Analysis Methodology and Tool for High-Level Synthesis. |
ISSS |
1997 |
DBLP DOI BibTeX RDF |
|
1 | Christian Blumenröhr, Dirk Eisenbiegler |
An Efficient Representation for Formal Synthesis. |
ISSS |
1997 |
DBLP DOI BibTeX RDF |
|
1 | Steven Vercauteren, Diederik Verkest, Gjalt G. de Jong, Bill Lin 0001 |
Derivation of Formal Representations from Process-Based Specification and Implementation Models. |
ISSS |
1997 |
DBLP DOI BibTeX RDF |
|
1 | Uwe Eckhardt, Renate Merker |
Optimization of the Background Memory Utilization by Partitioning. |
ISSS |
1997 |
DBLP DOI BibTeX RDF |
|
1 | Catherine H. Gebotys |
An Efficient Model for DSP Code Generation: Performance, Code Size, Estimated Energy. |
ISSS |
1997 |
DBLP DOI BibTeX RDF |
|
1 | Frank Vahid |
Port Calling: A Transformation for Reducing I/O during Multi-Package Functional Partitioning. |
ISSS |
1997 |
DBLP DOI BibTeX RDF |
communication, transformation, hardware/software codesign, system synthesis, Functional partitioning |
1 | Frank Vahid, Francky Catthoor (eds.) |
Proceedings of the 10th International Symposium on System Synthesis, ISSS '97, Antwerp, Belgium, September 17-19, 1997. |
ISSS |
1997 |
DBLP BibTeX RDF |
|
1 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
Architectural Exploration and Optimization of Local Memory in Embedded Systems. |
ISSS |
1997 |
DBLP DOI BibTeX RDF |
|
1 | Anne Mignotte, Olivier Peyran |
Reducing the Complexity of ILP Formulations for Synthesis. |
ISSS |
1997 |
DBLP DOI BibTeX RDF |
|
1 | A. Hein, J. Dalcolmo, P. Le Corre, Rudy Lauwereins, Marleen Adé |
Prototyping of the Receiver Unit for a Broadband Access Network. |
ISSS |
1997 |
DBLP DOI BibTeX RDF |
rapid prototyping tool, resource estimation in distributed systems, data-flow modeling, frame-grabber |
1 | Birger Landwehr, Peter Marwedel |
A New Optimization Technique for Improving Resource Exploitation and Critical Path Minimization. |
ISSS |
1997 |
DBLP DOI BibTeX RDF |
|
1 | Henning Dierks |
Synthesising Controllers from Real-Time Specifications. |
ISSS |
1997 |
DBLP DOI BibTeX RDF |
|
1 | Smita Bakshi, Daniel Gajski |
A Scheduling and Pipelining Algorithm for Hardware/Software Systems. |
ISSS |
1997 |
DBLP DOI BibTeX RDF |
throughput-constrained, scheduling, pipelining, high-performance, Hardware/software codesign |
1 | Krzysztof Kuchcinski |
Embedded System Synthesis by Timing Constraints Solving. |
ISSS |
1997 |
DBLP DOI BibTeX RDF |
Embedded Systems, Synthesis, Constraint Logic Programming |
1 | Ellen Sentovich |
Quick Conservative Causality Analysis. |
ISSS |
1997 |
DBLP DOI BibTeX RDF |
quick conservative causality analysis, causality problem, standard logic synthesis techniques, combinational circuits, combinational circuit, conservative algorithm |
1 | Guido Araujo, Ashok Sudarsanam, Sharad Malik |
Instruction Set Design and Optimizations for Address Computation in DSP Architectures. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Miguel Miranda, Francky Catthoor, Martin Janssen, Hugo De Man |
ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Alan Su 0002, Ta-Yung Liu, Yu-Chin Hsu, Mike Tien-Chien Lee |
Eliminating False Loops Caused by Sharing in Control Path. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
false loops, control path sharing, timing validation, design sign-off phase, data path sharing, control logic sharing, removal algorithm, computation complexity, high level synthesis, high level synthesis, filter, resource sharing, logic minimization |
1 | Hiroyuki Tomiyama, Hiroto Yasuura |
Size-Constrained Code Placement for Cache Miss Rate Reduction. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Alessandro Balboni, William Fornaciari, Massimo Vincenzi, Donatella Sciuto |
The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
virtual instruction set, control-dominated hardware-software system, retargetable code synthesis, real-time systems, embedded systems, software development, performance estimation, embedded computing, software synthesis, real-time constraints, system synthesis, static scheduling |
1 | James E. Beck, Daniel P. Siewiorek |
Modeling Multicomputer Task Allocation as a Vector Packing Problem. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
Vector Packing, Multicomputers, Design Automation |
1 | Vojin Zivojnovic, Stefan Pees, C. Schälger, Markus Willems, Rainer Schoenen, Heinrich Meyr |
DSP Processor/Compiler Co-Design: A Quantitative Approach. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
processor/compiler codesign, benchmarking methodology, DSPstone, fast processor simulation, SuperSim, compiled processor simulation, performance evaluation, embedded systems, digital signal processing, digital signal processing chips, LISA, top-down approach, machine description |
1 | Michael Gasteier, Manfred Glesner |
Bus-Based Communication Synthesis on System-Level. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
Memory Organization for Improved Data Cache Performance in Embedded Processors. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Michael Münch, Manfred Glesner, Norbert Wehn |
An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
control-flow dominated VHDL, time-constrainted scheduling, scheduling, ILP, code transformation, resource-constrained scheduling |
1 | Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel |
Testability Insertion in Behavioral Descriptions. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
synthesis for testability, at-speed testing, testability measures, test point insertion, high-level description |
1 | Sven Wuytack, Francky Catthoor, Gjalt G. de Jong, Bill Lin 0001, Hugo De Man |
Flow Graph Balancing for Minimizing the Required Memory Bandwidth. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Laurent Freund, Michel Israël, Frédéric Rousseau 0001, J. M. Bergé, Michel Auguin, Cécile Belleudy, Guy Gogniat |
A Codesign Experiment in Acoustic Echo Cancellation: GMDFa. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
|
1 | |
Proceedings of the 9th International Symposium on System Synthesis, ISSS '96, San Diego, CA, USA, November 6-8, 1996. |
ISSS |
1996 |
DBLP BibTeX RDF |
|
1 | Petru Eles, Zebo Peng, Krzysztof Kuchcinski, Alex Doboli |
Hardware/Software Partitioning with Iterative Improvement Heuristics. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
optimization, simulated annealing, partitioning, tabu search, Hardware/Software co-design |
1 | Frank Vahid, Thuy Dm Le, Yu-Chin Hsu |
A Comparison of Functional and Structural Partitioning. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Stephen Docy, Inki Hong, Miodrag Potkonjak |
Throughput Optimization in Disk-Based Real-Time Application Specific Systems. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
Massive Storage, Hard Real-Time, System-Level Synthesis |
1 | Stephen A. Blythe, Robert A. Walker 0001 |
Toward a Practical Methodology for Completely Characterizing the Optimal Design Space. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Chunho Lee, Miodrag Potkonjak, Wayne H. Wolf |
System-Level Synthesis of Application Specific Systems using A* Search and Generalized Force-Directed Heuristics. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
Hard Real-Time, Search Techniques, System-Level Synthesis |
1 | Min Xu, Fadi J. Kurdahi |
Layout-Driven RTL Binding Techniques for High-Level Synthesis. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
layout-driven register-transfer-level, binding techniques, chip level implementation, high level synthesis, high-level synthesis, design process |
1 | Johnny Öberg, Anshul Kumar, Ahmed Hemani |
Grammar-Based Hardware Synthesis of Data Communication Protocols. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
Grammar-based Specification, Data Communication Protocols, Design Space Exploration, Hardware Synthesis |
1 | Luca Benini, Patrick Vuillod, Claudionor José Nunes Coelho Jr., Giovanni De Micheli |
Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
low power, High level synthesis, finite state machines, gated clocks |
1 | Gernot Koch, Udo Kebschull, Wolfgang Rosenstiel |
Breakpoints and Breakpoint Detection in Source Level Emulation. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
|
1 | Luiz C. V. dos Santos, Marc J. M. Heijligers, C. A. J. van Eijk, Jos T. J. van Eijndhoven, Jochen A. G. Jess |
A Constructive Method for Exploiting Code Motion. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
conditional resource sharing, scheduling, high-level synthesis, code generation, conditionals, Code motion, search space pruning |
1 | Preeti Ranjan Panda, Nikil D. Dutt |
1995 high level synthesis design repository. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
1995 high level synthesis design repository, VHDL language, behavioral finite state machines, behavioral level, computational complexity, high level synthesis, finite state machines, VHDL, microprocessors, hardware description languages, microprocessor chips, floating point units |
1 | Herman Schmit, Donald E. Thomas |
Array mapping in behavioral synthesis. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
array grouping, array mapping, memory components, memory design space, schedule length, scheduling, data structures, memory architecture, hardware description languages, binding, behavioral synthesis, access times, design representation, hardware synthesis, synthesis tool |
1 | Pai H. Chou, Ross B. Ortega, Gaetano Borriello |
The Chinook hardware/software co-synthesis system. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
Chinook hardware/software co-synthesis system, custom logic, design co-simulation, design time constraints, embedded controller design, error-prone tasks, function migration, interface hardware, interface software, system components integration, real-time systems, software tools, logic design, microprocessors, logic CAD, microcontrollers, computer-aided design tools |
1 | Frank Vahid |
Procedure exlining: a transformation for improved system and behavioral synthesis. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
VHDL transformation tool, distinct computation, procedure exlining, procedure inlining, redundant sequences, statements, formal specification, distributed processing, VHDL, hardware description languages, remote procedure calls, behavioral synthesis, behavioral specification, system synthesis, procedure calls, synthesis tools |
1 | Jay K. Adams, Donald E. Thomas |
Multiple-process behavioral synthesis for mixed hardware-software systems. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
automated iterative improvement technique, concurrency optimization, concurrency tradeoffs, cost/performance ratio, hardware-software tradeoffs, mixed hardware-software systems, multiple-process behavioral synthesis, software engineering, resource allocation, concurrency control, controllers, optimisation, high level synthesis, logic design, multiprocessing systems, microprocessors, ASICs, application specific integrated circuits, ASIC, microprocessor chips, cost-benefit analysis |
1 | Mark Genoe, Paul Vanoostende, Geert van Wauwe |
On the use of VHDL-based behavioral synthesis for telecom ASIC design. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
Alcatel-Bell, RTL-synthesizable description, behavioral synthesis tools, hardware CAD tool, system level design methodology, telecom ASIC design, telecom system hardware design, high level synthesis, VHDL, VHDL, application specific integrated circuits, ASIC, logic synthesis, integrated circuit design, hardware description languages, integrated logic circuits, behavioral synthesis, telecommunication computing, hardware software codesign, design complexities |
1 | Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man |
Synthesis of pipelined DSP accelerators with dynamic scheduling. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
DSP algorithms, FFT butterfly accelerator block, application specific DSP accelerators, highly pipelined data paths, pipelined DSP accelerator synthesis, pipelined bit-parallel hardware, silicon, scheduling, parallel architectures, application specific integrated circuits, dynamic scheduling, pipeline processing, circuit CAD, digital signal processing chips, datapath, controller architecture, network synthesis, run-time schedules |
1 | Pierre G. Paulin, Farhad Mavaddat (eds.) |
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
|
1 | Filip Thoen, Marco Cornero, Gert Goossens, Hugo De Man |
Real-time multi-tasking in software synthesis for information processing systems. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
automatic processor mapping, automatically generated application-specific solution, concurrent process system specification, flexible execution models, hardware resource utilization, information processing systems, internal representation model, mobile satellite communication, personal terminal receiver demodulator, real-time multi-tasking, static information, time utilization, real-time systems, embedded systems, concurrency control, processor scheduling, timing constraints, computer aided software engineering, software synthesis, multiprocessing programs |
1 | Jan Madsen, Bjarne Hald |
An approach to interface synthesis. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
channel optimization, client-side interface description, client/server module synthesis, communication events formalization, existing module reuse, multiple client/server environment, one-sided interface description, server interface description, software reusability, application program interfaces, client-server systems, subroutines, interface synthesis, point-to-point communication |
1 | Frank Vahid, Daniel D. Gajski |
Clustering for improved system-level functional partitioning. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
N-way partitioning, fast heuristics, hardware components, highly-optimizing heuristics, multiple system components, reduced runtimes, system-level functional partitioning, clustering, formal specification, quality, VHDL, software components, merging, logic partitioning |
1 | Guido Araujo, Sharad Malik |
Optimal code generation for embedded memory non-homogeneous register architectures. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
TMS320C25 processor, [1, /spl infin/] model, embedded memory nonhomogeneous register architectures, expression trees, optimal code generation, register transfer graph, scheduling, computational complexity, graph theory, optimisation, computer architecture, register allocation, processor scheduling, storage allocation, microprocessor chips, instruction sets, instruction set architecture, sufficient conditions, instruction selection, structural representation |
1 | Samit Chaudhuri, Stephen A. Blythe, Robert A. Walker 0001 |
An exact methodology for scheduling in a 3D design space. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
2D design space, 3D design space, 3D scheduling problem, Voyager design space exploration system, candidate clock lengths, clock length, globally optimal solution, schedule length, three dimensional scheduling, three-dimensional design space, two dimensional design space, scheduling, optimisation, high level synthesis, search problems, clocks, tight bounds, network synthesis, search space pruning |
1 | Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt, Min Xu |
A comprehensive estimation technique for high-level synthesis. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
HLS benchmarks, RT level components, RTL datapaths, estimation technique, delays, high level synthesis, high-level synthesis, timing, design space exploration, granularity, hardware description languages, data flow graphs, registers, system buses, timing model, buses, behavioral description, layout area |
1 | Rainer Leupers, Peter Marwedel |
Time-constrained code compaction for DSPs. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
code generation techniques, digital signal processing algorithms, encoding restrictions, exact timing behavior, hard real-time constraints, integer programming model, local code compaction, programmable DSP, rigid heuristics, time-constrained code compaction, real-time systems, timing, integer programming, instruction-level parallelism, source coding, automatic programming, digital signal processing chips, side-effects |
1 | Hans Samsom, Frank H. M. Franssen, Francky Catthoor, Hugo De Man |
System level verification of video and image processing specifications. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
formal verification method, front-end telecom, image processing specifications, loop ordering, system level verification, computational complexity, image processing, complexity, formal specification, formal verification, video processing, numerical computing |
1 | Jean-Marc Daveau, Tarek Ben Ismail, Ahmed Amine Jerraya |
Synthesis of system-level communication by an allocation-based approach. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
allocation-based approach, high level primitives, interconnected processes, protocol selection, system-level communication synthesis, protocols, high level synthesis, systems analysis, cost function, interface synthesis, communication control |
1 | Clifford Liem, Pierre G. Paulin, Marco Cornero, Ahmed Amine Jerraya |
Industrial experience using rule-driven retargetable code generation for multimedia applications. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
VideoPhone codec controller, audio telecommunications, dedicated compiler availability, high-fidelity audio, optimization abilities, rule-driven retargetable code generation, video telecommunications, knowledge based systems, computer architecture, multiprocessing systems, multimedia systems, application specific integrated circuits, multimedia applications, application-specific instruction set processors, instruction sets, telecommunication computing, codecs, VLIW processor, VLIW architecture, transformation rules, controller architecture, optimising compilers, industrial experience, videotelephony, target architecture, MPEG audio |
1 | Matthew F. Parkinson, Sri Parameswaran |
Profiling in the ASP codesign environment. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
Automated Synthesis and Partitioning system, Hardware/Software Codesign project, codesign environment, hardware/software codesign methodology, high-level profiling tools, virtual machines, software tools, C, computer architecture, profiling, systems analysis, circuit CAD, workstation, ASP, C code, dedicated hardware, execution profiling |
1 | Jürgen Teich, Lothar Thiele, Edward A. Lee |
Modeling and simulation of heterogeneous real-time systems based on a deterministic discrete event model. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
Ptolemy design system, deterministic discrete event model, heterogeneous real-time systems, mixed asynchronous/synchronous systems, schedule constraints, synchronously clocked systems, timed marked graphs, simulation, modeling, real-time systems, discrete event simulation, timing analysis, finite buffering, self-timed systems |
1 | Markus Schwiegershausen, Peter Pirsch |
A system level design methodology for the optimization of heterogeneous multiprocessors. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
parametrizable processor modules, programmable processors, system level design methodology, optimization, real-time systems, image processing, linear programming, optimisation, integer programming, multiprocessing systems, heterogeneous systems, mixed integer linear programming, CAD tool, image processing algorithms, heterogeneous multiprocessors, mathematical framework |
1 | David J. Kolson, Alexandru Nicolau, Nikil D. Dutt, Ken Kennedy |
Optimal register assignment to loops for embedded code generation. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
data memory access, embedded code generation, heuristic modification, live variables, minimal spill code, optimal register assignment, scientific code, real-time systems, optimisation, storage allocation, loops, program control structures, exponential algorithm |
1 | Ti-Yen Yen, Wayne H. Wolf |
Sensitivity-driven co-synthesis of distributed embedded systems. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
application software architecture, communicating periodic processes, gradient-search algorithm, local sensitivity, priority prediction method, process allocation, real-time distributed embedded systems, sensitivity-driven co-synthesis, software engineering, real-time systems, distributed processing, logic design, ASICs, ASIC, processor scheduling, performance estimates, process scheduling, arbitrary topology, communication links, CPU time, heterogeneous distributed systems |
1 | Joseph Sifakis |
Real-time systems specification and verification. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
|
1 | Enric Musoll, Jordi Cortadella |
Scheduling and resource binding for low power. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
data-path power budget, low-power data-paths, scheduling, low power, high level synthesis, high-level synthesis, power consumption, adders, multipliers, logic circuits, data flow graphs, trading off, network synthesis, functional units, resource binding, resource-binding |
1 | Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita |
Power analysis and low-power scheduling techniques for embedded DSP software. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
circuit state, embedded DSP software, general-purpose commercial microprocessors, instruction-level power model, measurement based power analysis, micro-architectural power model, on-chip Booth multiplier, scheduling, real-time systems, application specific integrated circuits, energy consumption, scheduling algorithm, power analysis, energy minimization, circuit CAD, digital signal processing chips, instruction sets, energy reduction, low-power scheduling, DSP processor |
1 | Paul-Gerhard Plöger, Jörg Wilberg, Michel Langevin, Raul Camposano |
WWW based structuring of codesigns. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
WWW based structuring, design by documentation, hypertext documents, World Wide Web, World Wide Web (WWW), hypermedia, systems analysis, codesigns, Mosaic, information networks, documentation generation, WWW browser |
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