Search results for "RTL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
25	Felipe Machado, Teresa Riesgo, Yago Torroja	Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level.	PATMOS	2008	DBLP DOI BibTeX RDF	activity estimation, CAD, VHDL, BDD, power estimation, RTL, Switching activity, circuit partition, digital circuit design
25	Aaron N. Ng, Igor L. Markov, Rajat Aggarwal, Venky Ramachandran	Solving hard instances of floorplacement.	ISPD	2006	DBLP DOI BibTeX RDF	floorplacement, benchmarks, placement, floorplanning, RTL, circuit layout
25	Steven Swanson, Andrew Putnam, Martha Mercaldi, Ken Michelson, Andrew Petersen 0001, Andrew Schwerin, Mark Oskin, Susan J. Eggers	Area-Performance Trade-offs in Tiled Dataflow Architectures.	ISCA	2006	DBLP DOI BibTeX RDF	WaveScalar, ASIC, RTL, Dataflow computing
25	David Brier, Raj S. Mitra	Use of C/C++ models for architecture exploration and verification of DSPs.	DAC	2006	DBLP DOI BibTeX RDF	simulation, verification, formal, RTL, C/C++
25	Simon Fowler 0002, Andy J. Wellings	Formal development of a real-time kernel.	RTSS	1997	DBLP DOI BibTeX RDF	formal development, simple real time operating system kernel, restricted Ada 95 tasking model, fixed priority real time systems, abstract specification, PVS proof system, computational model, RTL, operating system kernels
25	Jainendra Kumar, Noel R. Strader, Jeff Freeman, Michael Miller	Emulation verification of the Motorola 68060.	ICCD	1995	DBLP DOI BibTeX RDF	emulation verification, Motorola 68060, hardware logic emulation, configurable hardware, circuit verification, pseudo-random verification vectors, software application programs, formal verification, microprocessors, reconfigurable architectures, logic CAD, digital simulation, circuit analysis computing, RTL, hardware description languages, hardware description language, microprocessor chips, HDL, gate-level
24	Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski	C-based design flow: a case study on G.729A for voice over internet protocol (VoIP).	DAC	2008	DBLP DOI BibTeX RDF	C-based design flow, C-to-RTL, G729A, NISC, HLS, VoIP, ASIP
24	Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham	Improved verification of hardware designs through antecedent conditioned slicing.	Int. J. Softw. Tools Technol. Transf.	2007	DBLP DOI BibTeX RDF	LTL property, Antecedent conditioned slicing, Verilog RTL, Model checking, Program slicing, Hardware description languages, Hardware verification
24	Peter Yiannacouras, Jonathan Rose, J. Gregory Steffan	The microarchitecture of FPGA-based soft processors.	CASES	2005	DBLP DOI BibTeX RDF	Nios, RTL generation, SPREE, application specic tradeoff, FPGA, pipeline, exploration, embedded processor, ASIP, microarchitecture, soft processor
24	Jiang Chau Wang, Paulo Sérgio Cardoso, Jose Artur Quilici González, Marius Strum, Ricardo Pires	Datapath BIST Insertion Using Pre-Characterized Area and Testability Data.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	test library, RTL architecture, pre-computed testability, self-test
24	Zaher S. Andraus, Karem A. Sakallah	Automatic abstraction and verification of verilog models.	DAC	2004	DBLP DOI BibTeX RDF	UCLID, logic of counter arithmetic with lambda expressions and uninter-preted functions (CLU), abstraction, register transfer level (RTL), verilog
24	Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee	Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator.	VLSI Design	2000	DBLP DOI BibTeX RDF	Extension field, BIST structure, Cellular Automata (CA), VLSI design and RTL, Finite field, DFT, Fault coverage, LFSR
24	Sujit Dey, Anand Raghunathan, Kenneth D. Wagner	Design for Testability Techniques at the Behavioral and Register-Transfer Levels.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	behavioral synthesis for testability, behavioral synthesis for BIST, high-level test generation, RTL synthesis for testability, design for testability
24	Masaru Takesue	A tampering protocol for reducing the coherence transactions in regular computation.	ISPAN	1997	DBLP DOI BibTeX RDF	tampering protocol, coherence transactions, regular computation, latency of communication, protocols, multiprocessor, cache-coherence protocol, RTL simulator
24	Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo, Wen-Bin Liao	Easily Testable Data Path Allocation Using Input/Output Registers.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	testable data path allocation, behavioral synthesis systems, input/output registers, interconnection allocation, module allocation, higher fault coverage, lower hardware overhead, improved testability, VLSI synthesis, optimization, algorithms, benchmarks, ATPG, DFT, register allocation, circuit optimisation, RTL design
24	Mark Genoe, Paul Vanoostende, Geert van Wauwe	On the use of VHDL-based behavioral synthesis for telecom ASIC design.	ISSS	1995	DBLP DOI BibTeX RDF	Alcatel-Bell, RTL-synthesizable description, behavioral synthesis tools, hardware CAD tool, system level design methodology, telecom ASIC design, telecom system hardware design, high level synthesis, VHDL, VHDL, application specific integrated circuits, ASIC, logic synthesis, integrated circuit design, hardware description languages, integrated logic circuits, behavioral synthesis, telecommunication computing, hardware software codesign, design complexities
24	Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt, Min Xu	A comprehensive estimation technique for high-level synthesis.	ISSS	1995	DBLP DOI BibTeX RDF	HLS benchmarks, RT level components, RTL datapaths, estimation technique, delays, high level synthesis, high-level synthesis, timing, design space exploration, granularity, hardware description languages, data flow graphs, registers, system buses, timing model, buses, behavioral description, layout area
24	Miriam Leeser, John W. O'Leary	Verification of a subtractive radix-2 square root algorithm and implementation.	ICCD	1995	DBLP DOI BibTeX RDF	subtractive radix-2 square root, floating point square root hardware, Intel Pentium, radix-2 square root, MIPS R4400, RTL level, verification, formal verification, theorem proving, theorem proving, floating point arithmetic, optimizing transformations
24	Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang 0003	Intel nehalem processor core made FPGA synthesizable.	FPGA	2010	DBLP DOI BibTeX RDF	intel nehalem, synthesizable core, fpga, emulator
24	Maman Abdurohman, Kuspriyanto, Sarwono Sutikno, Arif Sasongko	Transaction Level Modeling for Early Verification on Embedded System Design.	ACIS-ICIS	2009	DBLP DOI BibTeX RDF
24	Héctor Navarro, Saeid Nooshabadi, Juan A. Montiel-Nelson, Victor Navarro-Botello, Javier Sosa, José C. García 0001	A geometric approach to register transfer level satisfiability.	ISQED	2009	DBLP DOI BibTeX RDF
24	Suresh Raman, Mike Lubyanitsky	Cone Resynthesis ECO Methodology for Multi-Million Gate Designs.	VLSI Design	2009	DBLP DOI BibTeX RDF
24	Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu	Simulation Bounds for Equivalence Verification of Polynomial Datapaths Using Finite Ring Algebra.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
24	Gaurav Singh 0006, Sandeep K. Shukla	Verifying Compiler Based Refinement of BluespecTM.	SPIN	2008	DBLP DOI BibTeX RDF	Bluespec System Verilog (BSV), Formal Verification, Hardware Designs, SPIN Model Checker
24	J. P. Grossman, John K. Salmon, C. Richard Ho, Doug Ierardi, Brian Towles, Brannon Batson, Jochen Spengler, Stanley C. Wang, Rolf Mueller, Michael Theobald, Cliff Young, Joseph Gagliardo, Martin M. Deneroff, Ron O. Dror, David E. Shaw	Hierarchical simulation-based verification of Anton, a special-purpose parallel machine.	ICCD	2008	DBLP DOI BibTeX RDF
24	Banit Agrawal, Timothy Sherwood, Chulho Shin, Simon Yoon	Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation.	VLSI Design	2008	DBLP DOI BibTeX RDF
24	Felice Balarin, Roberto Passerone	Specification, Synthesis, and Simulation of Transactor Processes.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
24	Namrata Shekhar, Sudhakar Kalla, Florian Enescu	Equivalence Verification of Polynomial Datapaths Using Ideal Membership Testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
24	Sivaram Gopalakrishnan, Priyank Kalla	Optimization of polynomial datapaths using finite ring algebra.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	arithmetic datapaths, finite ring algebra, modulo arithmetic, polynomial datapaths, High-level synthesis
24	Hansu Cho, Samar Abdi, Daniel Gajski	Interface synthesis for heterogeneous multi-core systems from transaction level models.	LCTES	2007	DBLP DOI BibTeX RDF	HW-SW co-design, universal bridge, channel, transaction level model, communication synthesis, interface synthesis
24	Hiren D. Patel, Sandeep K. Shukla	Tackling an abstraction gap: co-simulating SystemC DE with bluespec ESL.	DATE	2007	DBLP DOI BibTeX RDF
24	Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William H. Reinhart, Darrel Eric Johnson, Zheng Xu 0004	The FAST methodology for high-speed SoC/computer simulation.	ICCAD	2007	DBLP DOI BibTeX RDF
24	Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke	VCEGAR: Verilog CounterExample Guided Abstraction Refinement.	TACAS	2007	DBLP DOI BibTeX RDF
24	Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara	A DFT Method for Time Expansion Model at Register Transfer Level.	DAC	2007	DBLP DOI BibTeX RDF
24	Nacer-Eddine Zergainoh, Ludovic Tambour, Ahmed Amine Jerraya	Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
24	Stefan Andrei, Wei-Ngan Chin, Albert Mo Kim Cheng, Mihai Lupu	Automatic Debugging of Real-Time Systems Based on Incremental Satisfiability Counting.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	system development tools, automatic debugging, counting SAT problem, Real-time system, formal methods, timing constraint, incremental computation
24	Sébastien Bilavarn, Guy Gogniat, Jean Luc Philippe, Lilian Bossuet	Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
24	Felice Balarin, Roberto Passerone	Functional verification methodology based on formal interface specification and transactor generation.	DATE	2006	DBLP DOI BibTeX RDF
24	Anupam Chattopadhyay, B. Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Automatic ADL-based operand isolation for embedded processors.	DATE	2006	DBLP DOI BibTeX RDF
24	Hristo Nikolov, Todor P. Stefanov, Ed F. Deprettere	Multi-processor system design with ESPAM.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	system-level design, Kahn process networks, heterogeneous MPSoCs
24	Andrés Takach, Bryan Bowyer, Thomas Bollaert	C Based Hardware Design for Wireless Applications.	DATE	2005	DBLP DOI BibTeX RDF
24	Nacer-Eddine Zergainoh, Katalin Popovici, Ahmed Amine Jerraya, Pascal Urard	IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems.	ASP-DAC	2005	DBLP DOI BibTeX RDF
24	Stefan Andrei, Albert Mo Kim Cheng, Wei-Ngan Chin, Mihai Lupu	Systematic Debugging of Real-Time Systems based on Incremental Satisfiability Counting.	IEEE Real-Time and Embedded Technology and Applications Symposium	2005	DBLP DOI BibTeX RDF
24	Mark Litterick, Joachim Geishauser	Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments.	MTV	2004	DBLP DOI BibTeX RDF
24	Stephen Bailey, Erich Marschner, Jayaram Bhasker, Jim Lewis, Peter J. Ashenden	Improving Design and Verification Productivity with VHDL-200x.	DATE	2004	DBLP DOI BibTeX RDF
24	Monica Donno, Enrico Macii, Luca Mazzoni	Power-aware clock tree planning.	ISPD	2004	DBLP DOI BibTeX RDF	clock tree synthesis and routing, physical design and optimization, low-power design, digital design
24	Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham	Towards The Complete Elimination of Gate/Switch Level Simulations.	VLSI Design	2004	DBLP DOI BibTeX RDF
24	Manoj Singh Gaur, Mark Zwolinski	Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique.	VLSI Design	2004	DBLP DOI BibTeX RDF
24	Franco Carbognani, Christopher K. Lennard, C. Norris Ip, Allan Cochrane, Paul Bates	Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard.	DATE	2003	DBLP DOI BibTeX RDF
24	Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes 0001, Everton Carara	From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study.	SBCCI	2003	DBLP DOI BibTeX RDF	transaction level, VHDL, SystemC, System modeling, register transfer level
24	Kwangyong Lee, Jeong-Si Kim, Chaedeok Lim, Heung-Nam Kim	A Development of Remote Tracepoint Debugger for Run-time Monitoring and Debugging of Timing Constraints on Qplus-P RTOS.	WSTFES	2003	DBLP DOI BibTeX RDF
24	Chris Rowen	Reducing SoC Simulation and Development Time.	Computer	2002	DBLP DOI BibTeX RDF
24	Reinaldo A. Bergamaschi	Bridging the domains of high-level and logic synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
24	Indradeep Ghosh, Krishna Sekar, Vamsi Boppana	Design for Verification at the Register Transfer Level.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
24	Ken C. K. Law, Horace Ho-Shing Ip, Fang Wei	An Abstract Layered Model for Hypermedia Document System.	ICMCS, Vol. 2	1999	DBLP DOI BibTeX RDF
24	Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja	Incorporating performance and testability constraints during binding in high-level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
24	Wen-Jong Fang, Allen C.-H. Wu	A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations.	ICCAD	1996	DBLP DOI BibTeX RDF	Multiple-FPGA partitioning, multiple-FPGA synthesis, functional structuring and functional partitioning
24	Abhijit Ghosh, Srinivas Devadas, A. Richard Newton	Sequential test generation and synthesis for testability at the register-transfer and logic levels.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
24	Jung-Hong Kao, Lawrence J. Henschen	A Graph Proof Procedure for Real Time Logic.	SEKE	1992	DBLP DOI BibTeX RDF
23	Tomas Pecenka, Lukás Sekanina, Zdenek Kotásek	Evolution of synthetic RTL benchmark circuits with predefined testability.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	evolvable hardware, testability analysis, Benchmark circuit
23	George Economakos, Sotirios Xydis	A Scheduling Postprocessor to Exploit Morphable RTL Components During High-Level Synthesis.	DSD	2008	DBLP DOI BibTeX RDF
23	Paul Schumacher, Pradip Jha	Fast and accurate resource estimation of RTL-based designs targeting FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
23	Saraju P. Mohanty	ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis.	ISQED	2008	DBLP DOI BibTeX RDF
23	Pejman Lotfi-Kamran, Mehran Massoumi, Mohammad Mirzaei, Zainalabedin Navabi	Enhanced TED: A New Data Structure for RTL Verification.	VLSI Design	2008	DBLP DOI BibTeX RDF
23	David M. Russinoff	A Mathematical Approach to RTL Verification.	CAV	2007	DBLP DOI BibTeX RDF
23	Sasidhar Sunkari, Supratik Chakraborty, Vivekananda M. Vedula, Kailasnath Maneparambil	A Scalable Symbolic Simulator for Verilog RTL.	MTV	2007	DBLP DOI BibTeX RDF
23	Youssef Serrestou, Vincent Beroulle, Chantal Robach	Functional Verification of RTL Designs driven by Mutation Testing metrics.	DSD	2007	DBLP DOI BibTeX RDF
23	Bijan Alizadeh, Masahiro Fujita	Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions.	ATVA	2007	DBLP DOI BibTeX RDF	Formal Verification, System on a Chip (SoC), Communication System, Canonical Representation, Sequential Equivalence Checking
23	Aric D. Blumer, Cameron D. Patterson	Hardware/Software Process Migration and RTL Simulation.	FPL	2007	DBLP DOI BibTeX RDF
23	Jen-Chieh Ou, Daniel G. Saab, Qiang Qiang, Jacob A. Abraham	Reducing verification overhead with RTL slicing.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	verification, test, CAD
23	Hannes Muhr, Roland Höler	Accelerating RTL Simulation by Several Orders of Magnitude Using Clock Suppression.	ICSAMOS	2006	DBLP DOI BibTeX RDF
23	Felipe Machado, Teresa Riesgo, Yago Torroja	A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits.	PATMOS	2006	DBLP DOI BibTeX RDF
23	Domenik Helms, Marko Hoyer, Wolfgang Nebel	Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage.	PATMOS	2006	DBLP DOI BibTeX RDF
23	Jaan Raik, Tanel Nõmmeots, Raimund Ubar	A New Testability Calculation Method to Guide RTL Test Generation.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	test pattern generation, register-transfer level, decision diagrams, testability measures
23	Masahiro Fujita	Extended abstract: a formal design approach from software oriented UML descriptions to hardware oriented RTL.	MEMOCODE	2005	DBLP DOI BibTeX RDF
23	Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng	Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver.	DATE	2005	DBLP DOI BibTeX RDF
23	Jae-Gon Lee, Woo-Seung Yang, Young-Su Kwon, Young-Il Kim, Chong-Min Kyung	Simulation acceleration of transaction-level models for SoC with RTL sub-blocks.	ASP-DAC	2005	DBLP DOI BibTeX RDF	SoC, systemc, transaction-level modeling, TLM, simulation acceleration
23	Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara	A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	strong testability, partially strong testability, complete fault efficiency, design-for-testability, data paths
23	Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr	Optimization Techniques for ADL-Driven RTL Processor Synthesis.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
23	Daniel Große, Rolf Drechsler	CheckSyC: an efficient property checker for RTL SystemC designs.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
23	Nobuyuki Nishiguchi	An advance RTL to GDS2 design methodology for 90 nm and below system LSIs to solve timing closure, signal integrity and design for manufacturing.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
23	Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke	Word level predicate abstraction and refinement for verifying RTL verilog.	DAC	2005	DBLP DOI BibTeX RDF	SAT, predicate abstraction, verilog
23	Alexey Kupriyanov, Frank Hannig, Jürgen Teich	High-Speed Event-Driven RTL Compiled Simulation.	SAMOS	2004	DBLP DOI BibTeX RDF
23	Giuseppe Falconeri, Walid Naifer, Nizar Romdhane	Common Reusable Verification Environment for BCA and RTL Models.	DATE	2004	DBLP DOI BibTeX RDF
23	Pietro Babighian, Luca Benini, Enrico Macii	A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks.	DATE	2004	DBLP DOI BibTeX RDF
23	Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara	Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
23	Arnaud Grasset, Frédéric Rousseau 0001, Ahmed Amine Jerraya	Network Interface Generation for MPSOC: From Communication Service Requirements to RTL Implementation.	IEEE International Workshop on Rapid System Prototyping	2004	DBLP DOI BibTeX RDF
23	Ho Fai Ko, Nicola Nicolici	Functional Illinois Scan Design at RTL.	ICCD	2004	DBLP DOI BibTeX RDF
23	Tun Li, Yang Guo 0003, Sikun Li	An Automatic Circuit Extractor for RTL Verification.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
23	Kartik Mohanram, C. V. Krishna, Nur A. Touba	A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
23	Raik Brinkmann, Rolf Drechsler	RTL-Datapath Verification using Integer Linear Programming.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
23	Alessandro Bogliolo, Roberto Corgnati, Enrico Macii, Massimo Poncino	Parameterized RTL power models for soft macros.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
23	Rajesh Radhakrishnan, Elena Teica, Ranga Vemuri	Verification of Basic Block Schedules Using RTL Transformations.	CHARME	2001	DBLP DOI BibTeX RDF
23	Donald S. Gelosh, Dorothy E. Setliff	Modeling layout tools to derive forward estimates of area and delay at the RTL level.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	estimation techniques, machine learning, estimation, layout, VLSI CAD
23	Crina Anton, Pierluigi Civera, Ionel Colonescu, Enrico Macii, Massimo Poncino, Alessandro Bogliolo	RTL Estimation of Steering Logic Power.	PATMOS	2000	DBLP DOI BibTeX RDF
23	Luca Benini, Alessandro Bogliolo, Enrico Macii, Massimo Poncino, Mihai Surmei	Regression-based RTL power models for controllers.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
23	Ricardo Ferreira, Anne-Marie Trullemans, José C. Costa, José Monteiro 0001	Probabilistic Bottom-Up RTL Power Estimation.	ISQED	2000	DBLP DOI BibTeX RDF	Register Tranfers Level, Power Estimation, Glitches, ZBDD
23	Hiroki Wada, Toshimitsu Masuzawa, Kewal K. Saluja, Hideo Fujiwara	Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency.	VLSI Design	2000	DBLP DOI BibTeX RDF	Complete fault efficiency, Design for testability, Data path, Hierarchical test
23	Jens Horstmannshoff, Heinrich Meyr	Efficient building block based RTL code generation from synchronous data flow graphs.	DAC	2000	DBLP DOI BibTeX RDF
23	Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara	A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF