Search results for "clock"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
39	Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, Vipul Kadodwala	Early clock prototyping for design analysis and quality entitlement.	ISQED	2009	DBLP DOI BibTeX RDF
39	Victor H. Cordero Calle, Sunil P. Khatri	Clock Distribution Scheme using Coplanar Transmission Lines.	DATE	2008	DBLP DOI BibTeX RDF
39	Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown	Clock tree synthesis with data-path sensitivity matching.	ASP-DAC	2008	DBLP DOI BibTeX RDF
39	Yanfeng Wang, Qiang Zhou 0001, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian	Low power clock buffer planning methodology in F-D placement for large scale circuit design.	ASP-DAC	2008	DBLP DOI BibTeX RDF
39	Suman Jana, Sneha Kumar Kasera	On fast and accurate detection of unauthorized wireless access points using clock skews.	MobiCom	2008	DBLP DOI BibTeX RDF	MAC address spoofing, fake access point, IEEE 802.11, fingerprint, timestamp
39	Nainesh Agarwal, Nikitas J. Dimopoulos	DSPstone Benchmark of CoDeL's Automated Clock Gating Platform.	ISVLSI	2007	DBLP DOI BibTeX RDF
39	Mohammad Azim Karami, Ali Afzali-Kusha, Reza Faraji-Dana, Masoud Rostami	Quantitative Comparison of Optical and Electrical H, X, and Y clock Distribution Networks.	ISVLSI	2007	DBLP DOI BibTeX RDF
39	Dawid Trawczynski, Janusz Sosnowski, Janusz Zalewski	The Effect of Large Clock Drifts on Performance of Event and Time Triggered Network Interfaces.	DepCoS-RELCOMEX	2007	DBLP DOI BibTeX RDF
39	Rong Ji, Xianjun Zeng, Liang Chen, Junfeng Zhang	The Implementation and Design of a Low-Power Clock Distribution Microarchitecture.	IEEE NAS	2007	DBLP DOI BibTeX RDF
39	Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man	Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
39	Anand Rajaram, Jiang Hu, Rabi N. Mahapatra	Reducing clock skew variability via crosslinks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
39	Baris Taskin, Ivan S. Kourtev	Delay Insertion Method in Clock Skew Scheduling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
39	Arjun Rajagopal	Clock tree design challenges for robust and low power design.	ISPD	2006	DBLP DOI BibTeX RDF	NBTI, IR drop
39	Thomas Locher, Roger Wattenhofer	Oblivious Gradient Clock Synchronization.	DISC	2006	DBLP DOI BibTeX RDF	Distributed algorithms, synchronization protocols, asynchronous computation
39	Chia-Chun Tsai, Jan-Ou Wu, Chien-Wen Kao, Trong-Yen Lee, Rong-Shue Hsiao	Coupling aware RLC-based clock routings for crosstalk minimization.	ISCAS	2006	DBLP DOI BibTeX RDF
39	Jussi Ängeslevä, Ross Cooper	Last Clock.	IEEE Computer Graphics and Applications	2005	DBLP DOI BibTeX RDF	information visualization, time, interactive art, ambient media
39	Wai-Ching Douglas Lam, Cheng-Kok Koh	Process variation robust clock tree routing.	ASP-DAC	2005	DBLP DOI BibTeX RDF
39	Kuo-Hsing Cheng, Chen-Lung Wu, Yu-Lung Lo, Chia-Wei Su	A phase-detect synchronous mirror delay for clock skew-compensation circuits.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
39	Xinjie Wei, Yici Cai, Xianlong Hong	Zero skew clock routing with tree topology construction using simulated annealing method.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
39	Kambiz Rahimi, Chris Diorio	In-Circuit Self-Tuning of Clock Latencies.	ISQED	2005	DBLP DOI BibTeX RDF
39	Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja	A yield improvement methodology using pre- and post-silicon statistical clock scheduling.	ICCAD	2004	DBLP DOI BibTeX RDF
39	Kamal S. Khouri, Niraj K. Jha	Clock selection for performance optimization of control-flowintensive behaviors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
39	Kamal S. Khouri, Niraj K. Jha	Clock Selection for Performance Optimization of Control-Flow Intensive Behaviors.	VLSI Design	2000	DBLP DOI BibTeX RDF
39	Mustafa Celik, Lawrence T. Pileggi	Metrics and bounds for phase delay and signal attenuation in RC(L)clock trees.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
39	Henrik Lönn	A Fault Tolerant Clock Synchronization Algorithm for Systems with Low-Precision Oscillators.	EDCC	1999	DBLP DOI BibTeX RDF
39	Ashok Vittal, Malgorzata Marek-Sadowska	Low-power buffered clock tree design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
39	Koenraad Audenaert	Clock Trees: Logical Clocks for Programs with Nested Parallelism.	IEEE Trans. Software Eng.	1997	DBLP DOI BibTeX RDF	Lamport clocks, nested fork-join parallelism, event labeling, vector clocks, Logical time
39	Jun Dong Cho, Majid Sarrafzadeh	A buffer distribution algorithm for high-performance clock net optimization.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
39	Shantanu Ganguly, Shervin Hojat	Clock distribution design and verification for PowerPC microprocessors.	ICCAD	1995	DBLP DOI BibTeX RDF	PowerPC
39	Jason Cong, Andrew B. Kahng, Gabriel Robins	Matching-based methods for high-performance clock routing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
38	Baris Taskin, Joseph Demaio, Owen Farell, Michael Hazeltine, Ryan Ketner	Custom topology rotary clock router with tree subnetworks.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Resonant rotary clocking, clock network design, multiphase synchronization, clock skew
38	Gustavo Wilke, Renan Fonseca, Cecilia Mezzomo, Ricardo Reis 0001	A novel scheme to reduce short-circuit power in mesh-based clock architectures.	SBCCI	2008	DBLP DOI BibTeX RDF	clock mesh, power, clock skew, short-circuit
38	Mohamed Nekili, Yvon Savaria, Guy Bois	Design of Clock Distribution Networks in Presence of Process Variations.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	process variations, clock skew, clock distribution
38	Tsung-Han Lin, Keng-hao Chang, Jr-ben Tian, Hao-Hua Chu, Polly Huang	Modeling and simulation comparison of two time synchronization protocols.	PM2HW2N	2008	DBLP DOI BibTeX RDF	performance evaluation, sensor networks, time synchronization
38	Joohee Kim, Conrad H. Ziesler	Fixed-Load Energy Recovery Memory for Low Power.	ISVLSI	2004	DBLP DOI BibTeX RDF
38	Mehmet A. Orgun, Chuchang Liu	Querying Clocked Databases.	FQAS	1998	DBLP DOI BibTeX RDF
38	Rajeev Alur, Costas Courcoubetis, Thomas A. Henzinger	The Observational Power of Clocks.	CONCUR	1994	DBLP DOI BibTeX RDF
38	Gill A. Pratt, John Nguyen	Distributed synchronous clocking.	ARVLSI	1995	DBLP DOI BibTeX RDF	distributed synchronous clocking, hardware clock, synchronous processor, distributed error correction algorithm, global phase alignment, mode lock, k-ary Cartesian meshes, scalability, graph theory, timing, synchronisation, error correction, clocks, phase locked loops, digital systems, clock signals
36	Hochang Jang, Taewhan Kim	Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization.	DAC	2009	DBLP DOI BibTeX RDF	clock synthesis, power/ground noise, buffer insertion
36	Eli Arbel, Cindy Eisner, Oleg Rokhlenko	Resurrecting infeasible clock-gating functions.	DAC	2009	DBLP DOI BibTeX RDF	clustering, low power, approximation, clock gating
36	Edmar Mota-Garcia, Rogelio Hasimoto-Beltrán	Clock offset estimation using collaborative one-way transit time.	SIGMETRICS	2008	DBLP DOI BibTeX RDF	clock offset estimation, one-way transit time
36	Rupak Samanta, Jiang Hu, Peng Li 0001	Discrete buffer and wire sizing for link-based non-tree clock networks.	ISPD	2008	DBLP DOI BibTeX RDF	non-tree, buffer, clock, wire, svm
36	Sultan Al-Hinai, Lynn Margaret Batten, Bernard D. Colbert	Mutually Clock-Controlled Feedback Shift Registers Provide Resistance to Algebraic Attacks.	Inscrypt	2007	DBLP DOI BibTeX RDF	stream cipher, algebraic attacks, clock-control
36	Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	A Gated Clock Scheme for Low Power Testing of Logic Cores.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	test-per-scan, test-per-clock, low power design, low power test
36	Kui Wang, Lian Duan, Xu Cheng	ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew scheduling.	DAC	2006	DBLP DOI BibTeX RDF	back-annotation, skew scheduling, logic synthesis, clock skew
36	Chao-Yang Yeh, Malgorzata Marek-Sadowska	Skew-programmable clock design for FPGA and skew-aware placement.	FPGA	2005	DBLP DOI BibTeX RDF	clock architecture, skew optimization, placement
36	Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee, Wen-Ta Lee	Zero-Skew Driven for RLC Clock Tree Construction in SoC.	ICITA (1)	2005	DBLP DOI BibTeX RDF	RLC delay model, Upward propagation, SoC, Clock tree, Zero skew
36	Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu	Skew scheduling and clock routing for improved tolerance to process variations.	ASP-DAC	2005	DBLP DOI BibTeX RDF	layout embedding, skew scheduling, reliability, process variation, clock routing
36	Kamran Saleh, Mehrdad Najibi, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi	A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	on-chip clock generation, FPGA, GALS
36	Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip J. Restle, Mary Yvonne Lanzerotti	Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	load capacitance, routing, application specific integrated circuit (ASIC), clock, power dissipation
36	Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa	Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	test-per-clock testing, test pattern compression, zero aliasing error, built-in self test, test response compaction
36	Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen	Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time.	ISPD	2003	DBLP DOI BibTeX RDF	?-optimal, incremental refinement, pseudo-polynomial, clock tree, wire-sizing, zero-skew
36	Emil Talpes, Diana Marculescu	A critical analysis of application-adaptive multiple clock processors.	ISLPED	2003	DBLP DOI BibTeX RDF	multi clock processors, dynamic voltage scaling, microarchitecture, simulation framework, globally asynchronous locally synchronous
36	Venkata Syam P. Rapaka, Diana Marculescu	A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores.	ISLPED	2003	DBLP DOI BibTeX RDF	issue window design, mixed-clock circuits, GALS
36	Andreas Weissel, Frank Bellosa	Process cruise control: event-driven clock scaling for dynamic power management.	CASES	2002	DBLP DOI BibTeX RDF	clock scaling, event counters, scheduling, power management
36	Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili	Quadratic deferred-merge embedding algorithm for zero skew clock distribution network.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	VLSI, clock distribution network, zero skew
36	Jaewon Oh, Massoud Pedram	Gated Clock Routing Minimizing the Switched Capacitance.	DATE	1998	DBLP DOI BibTeX RDF	gated clock routing, low power
36	Anurag Agarwal, Vijay K. Garg	Efficient dependency tracking for relevant events in concurrent systems.	Distributed Comput.	2007	DBLP DOI BibTeX RDF	Dependency tracking, Vector clock, Predicate detection
36	Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	A low power VLIW processor generation method by means of extracting non-redundant activation conditions.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	low power, ASIP, clock gating, VLIW processor
36	Anurag Agarwal, Vijay K. Garg	Efficient dependency tracking for relevant events in shared-memory systems.	PODC	2005	DBLP DOI BibTeX RDF	shared-memory, vector clock, predicate detection
36	Srimat T. Chakradhar	Optimum retiming of large sequential circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	optimum retiming, large sequential circuits, unit delay model, optimum clock period, path graph, VLSI, linear programming, delays, timing, integer programming, sequential circuits, logic CAD, integer linear program, flip-flops, circuit CAD, fast algorithm, integrated logic circuits, circuit optimisation, VLSI circuits, linear program relaxation
35	Roland Mandler	A configurable adjunct for real time systems (CARTS).	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	utility programs, configurable adjunct for real time systems, rapid application code generation, generic user interfaces, processor restarts, incremental system integration, incremental system reconfiguration, file-based data, tailored functionality, CARTS postal system, optimal transfer methods, backplane I/O, network I/O, CARTS clock services, high resolution time of day clocks, high resolution mission clock, system wide clock synchronisation, real-time systems, user interfaces, architectures, shared memory, shared memory systems, application program interfaces, clocks, network operating systems, operating system kernels, CARTS, real time distributed systems, input-output programs, system services, intertask communication
35	Bakhtiar Affendi Rosdi, Atsushi Takahashi 0001	Low area pipelined circuits by multi-clock cycle paths and clock scheduling.	ASP-DAC	2006	DBLP DOI BibTeX RDF
34	Rajballav Dash, Rajesh Garg, Sunil P. Khatri, Gwan S. Choi	SEU hardened clock regeneration circuits.	ISQED	2009	DBLP DOI BibTeX RDF
34	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
34	Morteza Saheb Zamani, Maryam Taajobian, Mehdi Saeedi	An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty.	DSD	2008	DBLP DOI BibTeX RDF
34	Marina Biberstein, Yuval Harel, Andre Heilper	Clock Synchronization in Cell BE Traces.	Euro-Par	2008	DBLP DOI BibTeX RDF
34	Aida Todri, Malgorzata Marek-Sadowska	A study of reliability issues in clock distribution networks.	ICCD	2008	DBLP DOI BibTeX RDF
34	Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mossé, Rami G. Melhem	Integrated CPU Cache Power Management in Multiple Clock Domain Processors.	HiPEAC	2008	DBLP DOI BibTeX RDF
34	Zbigniew Jerzak, Robert Fach, Christof Fetzer	Adaptive Internal Clock Synchronization.	SRDS	2008	DBLP DOI BibTeX RDF
34	Saif Ali Butt, Stefan Schmermbeck, Jurij Rosenthal, Alexander Pratsch, Eike Schmidt	System level clock tree synthesis for power optimization.	DATE	2007	DBLP DOI BibTeX RDF
34	Bill Pontikakis, Hung Tien Bui, François R. Boyer, Yvon Savaria	A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs.	ISCAS	2007	DBLP DOI BibTeX RDF
34	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu	Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture.	ISQED	2007	DBLP DOI BibTeX RDF
34	Omer Gurewitz, Israel Cidon, Moshe Sidi	Network classless time protocol based on clock offset optimization.	IEEE/ACM Trans. Netw.	2006	DBLP DOI BibTeX RDF	UTC, classless time protocol (CTP), measurements, network management, estimation, time synchronization, one-way delay
34	Ezra N. Hoch, Danny Dolev, Ariel Daliot	Self-stabilizing Byzantine Digital Clock Synchronization.	SSS	2006	DBLP DOI BibTeX RDF
34	Shalabh Goyal, Abhijit Chatterjee, Mike Atia	Reducing Sampling Clock Jitter to Improve SNR Measurement of A/D Converters in Production Test.	ETS	2006	DBLP DOI BibTeX RDF
34	Yiqun Li, Changsheng Xu, Kongwah Wan, Xin Yan 0001, Xinguo Yu	Reliable Video Clock Time Recognition.	ICPR (4)	2006	DBLP DOI BibTeX RDF
34	Houman Zarrabi, Haydar Saaied, Asim J. Al-Khalili, Yvon Savaria	Zero skew differential clock distribution network.	ISCAS	2006	DBLP DOI BibTeX RDF
34	Xinjie Wei, Yici Cai, Xianlong Hong	Clock Skew Scheduling Under Process Variations.	ISQED	2006	DBLP DOI BibTeX RDF
34	Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man	Digital ground bounce reduction by supply current shaping and clock frequency Modulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
34	Daniel González, Luis Parrilla 0001, Antonio García 0001, Encarnación Castillo, Antonio Lloris-Ruíz	Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers.	PATMOS	2005	DBLP DOI BibTeX RDF
34	Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler	Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors.	HPCA	2005	DBLP DOI BibTeX RDF
34	Jeng-Liang Tsai, Charlie Chung-Ping Chen	Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling.	ASP-DAC	2005	DBLP DOI BibTeX RDF
34	Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra	Fast and Low-Cost Clock Deskew Buffer.	DFT	2004	DBLP DOI BibTeX RDF
34	Kuo-Hsing Cheng, Shu-Yu Jiang, Zong-Shen Chen	BIST for clock jitter measurements.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
34	Omer Gurewitz, Israel Cidon, Moshe Sidi	Network Time Synchronization Using Clock Offset Optimization.	ICNP	2003	DBLP DOI BibTeX RDF
34	Pilar Parra Fernández, Antonio J. Acosta 0001, Manuel Valencia-Barrero	Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1.	PATMOS	2002	DBLP DOI BibTeX RDF
34	Chao Xu, Frank Barber, Kenneth R. Laker, Jan Van der Spiegel	Analysis of clock buffer phase noise.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
34	Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams	Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme.	ITC	2002	DBLP DOI BibTeX RDF
34	Jaewon Oh, Massoud Pedram	Gated clock routing for low-power microprocessor design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
34	Young-Su Kwon, Bong-Il Park, In-Cheol Park, Chong-Min Kyung	A New Single-Clock Flip-Clop for Half-Swing Clocking.	ASP-DAC	1999	DBLP DOI BibTeX RDF
34	Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal	A rated-clock test method for path delay faults.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
34	Les Hall, Mark Clements, Wentai Liu, Griff L. Bilbro	Clock Distribution Using Cooperative Ring Oscillators.	ARVLSI	1997	DBLP DOI BibTeX RDF
34	Qing Zhu, Wayne Wei-Ming Dai	High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
34	Jae Chung, Chung-Kuan Cheng	Skew sensitivity minimization of buffered clock tree.	ICCAD	1994	DBLP DOI BibTeX RDF
34	Ren-Song Tsay	An exact zero-skew clock routing algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
34	Cecilia Metra, Stefano Di Francescantonio, Bruno Riccò, T. M. Mak	Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects.	DFT	2001	DBLP DOI BibTeX RDF	clock faults, testing, microprocessor, Clock distribution network
34	Maheshwar Umasankar, Ahmed El-Amawy	Generalized Algorithms for Systematic Synthesis of Branch-and-Combine Clock Networks for Meshes, Tori, and Hypercubes.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF	skew bound, Branch-and-Combine, feature cycle length, hypercube, mesh, tile, torus, Clock skew, clock network
34	Danny Dolev, Joseph Y. Halpern, Barbara Simons, H. Raymond Strong	Dynamic Fault-Tolerant Clock Synchronization.	J. ACM	1995	DBLP DOI BibTeX RDF	time-of-day clock, fault-tolerance, clock synchronization, Byzantine failures
34	Sherif A. Tawfik, Volkan Kursun	Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew.	ISCAS	2007	DBLP DOI BibTeX RDF