Search results for "flip-flops"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
33	Saihua Lin, Huazhong Yang, Rong Luo	A Novel Low Power Interface Circuit Design Technique for Multiple Voltage Islands Scheme.	ISCAS	2007	DBLP DOI BibTeX RDF
33	Minoru Watanabe, Fuminori Kobayashi	A High-Density Optically Reconfigurable Gate Array Using Dynamic Method.	FPL	2004	DBLP DOI BibTeX RDF
33	Young-Su Kwon, Bong-Il Park, In-Cheol Park, Chong-Min Kyung	A New Single-Clock Flip-Clop for Half-Swing Clocking.	ASP-DAC	1999	DBLP DOI BibTeX RDF
33	John F. McDonald 0001, Bryan S. Goda	Reconfigurable FPGA's in the 1-20 GHz Band with HBT BiCMOS.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
33	Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante	Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection.	DATE	1998	DBLP DOI BibTeX RDF
33	Sachin S. Sapatnekar, Rahul B. Deokar	Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
32	Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija	Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements.	PATMOS	2008	DBLP DOI BibTeX RDF	Clocked storage elements, VLSI, power consumption, flip-flops, voltage scaling, clock gating, power gating, energy optimization, MTCMOS, circuit optimization, circuit tuning, circuit analysis
32	Hans G. Kerkhoff, Mansour Shashaani, Manoj Sachdev	A Low-Speed BIST Framework for High-Performance Circuit Testing.	VTS	2000	DBLP DOI BibTeX RDF	controlled-delay flip-flops, BIST, Delay-fault testing, design for delay testability
32	Haris Lekatsas, Wayne H. Wolf	Code Compression for Embedded Systems.	DAC	1998	DBLP DOI BibTeX RDF	low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian
32	Farzan Fallah, Srinivas Devadas, Kurt Keutzer	Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability.	DAC	1998	DBLP DOI BibTeX RDF	low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian
32	James T. Kao, Siva G. Narendra, Anantha P. Chandrakasan	MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns.	DAC	1998	DBLP DOI BibTeX RDF	low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian
32	Silvina Hanono, Srinivas Devadas	Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator.	DAC	1998	DBLP DOI BibTeX RDF	low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian
32	Clark W. Barrett, David L. Dill, Jeremy R. Levitt	A Decision Procedure for Bit-Vector Arithmetic.	DAC	1998	DBLP DOI BibTeX RDF	low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian
32	Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Masafumi Takahashi, Mototsugu Hamada, Hideho Arakida, Toshihiro Terazawa, Tadahiro Kuroda	Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques.	DAC	1998	DBLP DOI BibTeX RDF	low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian
32	Youpyo Hong, Peter A. Beerel, Luciano Lavagno, Ellen Sentovich	Don't Care-Based BDD Minimization for Embedded Software.	DAC	1998	DBLP DOI BibTeX RDF	low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian
32	Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy 0001, Vivek De	Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits.	DAC	1998	DBLP DOI BibTeX RDF	low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian
32	Bill Lin 0001	Software Synthesis of Process-Based Concurrent Programs.	DAC	1998	DBLP DOI BibTeX RDF	low power, C, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian
32	Robert B. Norwood, Edward J. McCluskey	Synthesis-for-scan and scan chain ordering.	VTS	1996	DBLP DOI BibTeX RDF	synthesis-for-scan procedure, scan chain ordering, testable circuit design, beneficial scan, VLSI, logic testing, integrated circuit testing, design for testability, logic design, sequential circuits, logic synthesis, flip-flops, integrated circuit design, integrated logic circuits, test strategy, boundary scan testing, functional specifications
32	Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal	Parallel concurrent path-delay fault simulation using single-input change patterns.	VLSI Design	1996	DBLP DOI BibTeX RDF	concurrent path-delay fault simulation, single-input change patterns, singly-testable path-delay faults, random values, rising transitions, falling transitions, sixteen-valued algebra, machine word parallelism, ISCAS '85 benchmarks, ISCAS '89 benchmarks, parallel algorithms, fault diagnosis, logic testing, delays, Boolean functions, sequential circuits, logic CAD, circuit analysis computing, flip-flops, Boolean operations
32	Milos D. Ercegovac, Tomás Lang	Sign detection and comparison networks with a small number of transitions.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	comparison networks, signal transitions, iterative implementation, k-bit modules, digital arithmetic, flip-flops, tree network, sign detection
32	Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray	Concurrent timing optimization of latch-based digital systems.	ICCD	1995	DBLP DOI BibTeX RDF	concurrent timing optimization, latch-based digital systems, digital system timing, intentional clock skew, latch-based designed systems, multi-phase clocking, resynchronization, latches insertion, optimisation, timing, logic design, flip-flops, retiming, mixed integer linear program, race conditions, integrated framework, wave pipelining, hazards and race conditions, clock period
32	Kei-Yong Khoo, Alan N. Willson Jr.	Single-transistor transparent-latch clocking.	ARVLSI	1995	DBLP DOI BibTeX RDF	transparent-latch clocking, single-phase clocking scheme, CMOS VLSI designs, single NMOS transistor, allowable width, clock driver, dynamic buffer, architecture-driven voltage scaling, pipelining latches, latch-intensive architectures, filter structures, transposed-form FIR filter, VLSI, flip-flops, clocks, integrated circuit design, digital filters, FIR filters, power dissipation, CMOS digital integrated circuits
32	Carl Ebeling, Brian Lockyear	On the performance of level-clocked circuits.	ARVLSI	1995	DBLP DOI BibTeX RDF	level-clocked circuits, level-sensitive latches, timing, synchronisation, flip-flops, clocks, retiming, clock skew, clock period, pipelined circuits
32	Rajesh Nair, Dong Sam Ha	VISION: an efficient parallel pattern fault simulator for synchronous sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	parallel pattern fault simulator, VLSI, VLSI, fault diagnosis, heuristics, logic testing, integrated circuit testing, sequential circuits, digital simulation, VISION, circuit analysis computing, flip-flops, synchronous sequential circuits, benchmark circuits
32	Joan Carletta, Christos A. Papachristou	Structural constraints for circular self-test paths.	VTS	1995	DBLP DOI BibTeX RDF	circular self-test paths, bit-level correlation, register adjacency, logic testing, built-in self test, built-in self test, integrated circuit testing, sequential circuits, automatic testing, flip-flops, test quality, register transfer level circuits
32	Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Functional clock schedule optimization.	VLSI Design	1995	DBLP DOI BibTeX RDF	clock schedule optimization, time frames, level-sensitive sequential circuits, scheduling, delays, delays, timing, sequential circuits, flip-flops, clocks, circuit optimisation, latches, false paths
32	John P. Fishburn	Clock Skew Optimization.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	synchronous digital system, minimum safety margin, performance, linear programs, optimisation, CMOS, circuit analysis computing, flip-flops, circuit simulation, CMOS integrated circuits, path delays, clock signal
32	Lindsay Kleeman	The Jitter Model for Metastability and Its Application to Redundant Synchronizers.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	jitter model, redundant synchronizers, circuit noise, CMOS D-type flip-flop, bistable device, simulation, circuit analysis computing, flip-flops, SPICE, CMOS integrated circuits, integrated logic circuits, reliability analysis, metastability, timing model, circuit analysis
32	Stephen H. Unger, Chung-Jen Tan	Clocking Schemes for High-Speed Digital Systems.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	clock pulses, edge-triggered flip-flops, edge tolerances, one-phase clocking, delays, timing, Clocking, digital systems, skew, latches, synchronous circuits
32	Hussein T. Mouftah, I. B. Jordan	Design of Ternary COS/MOS Memory and Sequential Circuits.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	COS/MOS integrated circuits, fundamental ternary circuits, programmable divide-by-N counters, ternary counters, ternary flip-flops, ternary logic implementation, ternary memory cells, ternary sequential logic, multiple-valued logic
32	Tich T. Dao, Edward J. McCluskey, Lewis K. Russel	Multivalued Integrated Injection Logic.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	Multilevel I2L, Post logic, quaternary logic, quaternary ROM, quaternary flip-flops, radix-4 arithmetic, threshold I2L, multivalued logic
32	George R. Couranz, Donald F. Wann	Theoretical and Experimental Behavior of Synchronizers Operating in the Metastable Region.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	Asynchronous fundamental mode input changes, binary switching time, flip-flop metastable region, interrupt failure, probabilistic behavior of flip-flops, glitch, asynchronous interactions, synchronizer failures
30	Shota Nakabeppu, Nobuyuki Yamasaki	A Learning-based Control Scheme for MTJ-based Non-volatile Flip-Flops.	IPSJ Trans. Syst. LSI Des. Methodol.	2024	DBLP DOI BibTeX RDF
30	Kimiyoshi Usami, Daiki Yokoyama, Aika Kamei, Hideharu Amano, Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho	Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops to Minimize Store Energy Under Process and Temperature Variations.	IEEE Trans. Very Large Scale Integr. Syst.	2024	DBLP DOI BibTeX RDF
30	Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara	Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing Circuits.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2024	DBLP DOI BibTeX RDF
30	Sekeon Kim, Sehee Lim, Dong Han Ko, Tae Woo Oh, Seong-Ook Jung	Ferroelectric FET Nonvolatile Sense-Amplifier-Based Flip-Flops for Low Voltage Operation.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
30	Yuqiang Cui, Lishuo Deng, Keran Li, Weiwei Shan	FLC-EDC: A Fast Low-Cost Error Detection and Correction Scheme for AVFS System Based on Flip-Flops Resampling in 28-nm CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
30	Soomin Kim, Taewhan Kim	Enhancing Design Qualities Utilizing Multibit Flip-Flops: A Design and Technology Co-Optimization Driven Approach.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
30	Yen-Yu Chen, Hao-Yu Wu, Iris Hui-Ru Jiang, Cheng-Hong Tsai, Chien-Cheng Wu	Slack Redistributed Register Clustering with Mixed-Driving Strength Multi-bit Flip-Flops.	ISPD	2024	DBLP DOI BibTeX RDF
30	Bomin Joo, Bai-Sun Kong	Low-Power High-Speed Sense-Amplifier-Based Flip-Flops With Conditional Bridging.	IEEE Access	2023	DBLP DOI BibTeX RDF
30	Filippo Minnella, Jordi Cortadella, Mario R. Casu, Mihai T. Lazarescu, Luciano Lavagno	Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops.	IEEE Access	2023	DBLP DOI BibTeX RDF
30	Aika Kamei, Hideharu Amano, Takuya Kojima, Daiki Yokoyama, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho	A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
30	Chunkai Fu, Ben Trombley, Hua Xiang 0001, Gi-Joon Nam, Jiang Hu	Machine Learning Techniques for Pre-CTS Identification of Timing Critical Flip-Flops.	ISVLSI	2023	DBLP DOI BibTeX RDF
30	Shotaro Sugitani, Ryuichi Nakajima, Keita Yoshida, Jun Furuta, Kazutoshi Kobayashi	Radiation Hardened Flip-Flops with low Area, Delay and Power Overheads in a 65 nm bulk process.	IRPS	2023	DBLP DOI BibTeX RDF
30	Suwan Kim, Taewhan Kim	Design and Technology Co-Optimization for Useful Skew Scheduling on Multi-Bit Flip-Flops.	ICCAD	2023	DBLP DOI BibTeX RDF
30	Fabian Kreß, Johannes Pfau, Fabian Kempf, Patrick Schmidt, Zhuofan He, Tanja Harbaum, Jürgen Becker 0001	Automated Replacement of State-Holding Flip-Flops to Enable Non-Volatile Checkpointing.	NorCAS	2023	DBLP DOI BibTeX RDF
30	Jaewan Yang, Taewhan Kim	Debanking Techniques on Multi-bit Flip-flops for Reinforcing Useful Clock Skew Scheduling.	SOCC	2023	DBLP DOI BibTeX RDF
30	Jinmyoung Kim, Taewhan Kim	Allocation of Multi-bit Flip-Flops Targeting Low-Power Chips.	ISOCC	2023	DBLP DOI BibTeX RDF
30	Yu-Teng Nien, Chen-Hong Li, Pei-Yin Wu, Yung-Jheng Wang, Kai-Chiang Wu, Mango C.-T. Chao	Test Generation for Defect-Based Faults of Scan Flip-Flops.	VTS	2023	DBLP DOI BibTeX RDF
30	Ziling Wang, Lidan Wang 0001, Shukai Duan	Memristor ratioed logic crossbar-based delay and jump-key flip-flops design.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
30	Anuradha Chathuranga Ranasinghe	Ultra-Low-Voltage Flip-Flops and Near-Threshold Modeling.		2022	DOI RDF
30	Yuki Abe, Kazutoshi Kobayashi, Hiroyuki Ochi	Nonvolatile Flip-Flops Using FiCC for IoT Processors with Intermittent Operations.	MWSCAS	2022	DBLP DOI BibTeX RDF
30	Duong Nghiep Huy, Guowei Chen, Kiichi Niitsu	22nm CMOS pW Standby Power Flip-Flops with/without Security using Dynamic Leakage Suppression Logic.	LASCAS	2022	DBLP DOI BibTeX RDF
30	Meng-Yun Liu, Yu-Cheng Lai, Wai-Kei Mak, Ting-Chi Wang	Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization.	ICCAD	2022	DBLP DOI BibTeX RDF
30	Kimiyoshi Usami, Daiki Yokoyama, Aika Kamei, Hideharu Amano	Optimal switching time to minimize store energy in MTJ-based flip-flops under process and temperature variations.	NorCAS	2022	DBLP DOI BibTeX RDF
30	Chang Cai, Zehao Wu, Jing Zhang, Luchang Ding, Lei Shen, Jun Yu 0010, Yaqing Chi	Implementation of Radiation Hardened Flip-Flops Based on Novel Fishbone Layouts.	ISCAS	2022	DBLP DOI BibTeX RDF
30	Lawrence T. Clark, Alen Duvnjak, Clifford Young-Sciortino, Matthew Cannon, John S. Brunhaver, Sapan Agarwal, Jereme Neuendank, Donald Wilson, Hugh J. Barnaby, Matthew J. Marinella	Self-correcting Flip-flops for Triple Modular Redundant Logic in a 12-nm Technology.	ISCAS	2022	DBLP DOI BibTeX RDF
30	Soomin Kim 0001, Taewhan Kim	Optimizing Timing in Placement Through I/O Signal Flipping on Multi-bit Flip-flops.	ISCAS	2022	DBLP DOI BibTeX RDF
30	Ryuichi Nakajima, Kazuya Ioki, Jun Furuta, Kazutoshi Kobayashi	Radiation Hardened Flip-Flops Minimizing Area, Power, and Delay Overheads with 1/100 Lower α-SER in a 130 nm Bulk Process.	IOLTS	2022	DBLP DOI BibTeX RDF
30	Se Keon Kim, Tae Woo Oh, Sehee Lim, Dong Han Ko, Seong-Ook Jung	High-Performance and Area-Efficient Ferroelectric FET-Based Nonvolatile Flip-Flops.	IEEE Access	2021	DBLP DOI BibTeX RDF
30	Francesco Centurelli, Giuseppe Scotti, Gaetano Palumbo	A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
30	Oliver Schrape, Marko S. Andjelkovic, Anselm Breitenreiter, Steffen Zeidler 0001, Alexey Balashov, Milos Krstic	Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
30	Trapti Sharma, Laxmi Kumre	Design of unbalanced ternary counters using shifting literals based D-Flip-Flops in carbon nanotube technology.	Comput. Electr. Eng.	2021	DBLP DOI BibTeX RDF
30	Gyoung-Hwan Hyun, Taewhan Kim	Allocation of Multibit Retention Flip-Flops for Power Gated Circuits: Algorithm-Design Unified Approach.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2021	DBLP DOI BibTeX RDF
30	Xin Cheng 0001, Bin Li, Haowen Zhu, Yongqiang Zhang 0006, Zhang Zhang	A high-resolution hybrid digital pulse width modulator with dual-edge-triggered flip-flops and hardware compensation.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
30	Takeharu Ikezoe, Takuya Kojima, Hideharu Amano	Recovering Faulty Non-Volatile Flip Flops for Coarse-Grained Reconfigurable Architectures.	IEICE Trans. Electron.	2021	DBLP DOI BibTeX RDF
30	Yoshinori Ono, Kimiyoshi Usami	Energy Efficient Approximate Storing of Image Data for MTJ Based Non-Volatile Flip-Flops and MRAM.	IEICE Trans. Electron.	2021	DBLP DOI BibTeX RDF
30	Mayank Kumar Singh, Puneet Singh, Devarshi Mrinal Das, Mahendra Sakare	A low power 8 × 27-1 PRBS generator using Exclusive-OR gate merged D flip-flops.	MWSCAS	2021	DBLP DOI BibTeX RDF
30	Aika Kamei, Takuya Kojima, Hideharu Amano, Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho	Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops.	MCSoC	2021	DBLP DOI BibTeX RDF
30	Oliver Schrape, Anselm Breitenreiter, Carsten Schulze, Steffen Zeidler 0001, Milos Krstic	Radiation-Hardness-by-Design Latch-based Triple Modular Redundancy Flip-Flops.	LASCAS	2021	DBLP DOI BibTeX RDF
30	Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet	Subthreshold Power PC and Nand Race-Free Flip-Flops in Frequency Divider Applications.	NorCAS	2021	DBLP DOI BibTeX RDF
30	Madhvi Agarwal, Sneh Saurabh	An Efficient Timing Model of Flip-Flops Based on Artificial Neural Network.	MLCAD	2021	DBLP DOI BibTeX RDF
30	Anuradha Chathuranga Ranasinghe, Sabih H. Gerez	Novel Ultra-Low-Voltage Flip-Flops: Near-Vth Modeling and VLSI Integration.	ICCD	2021	DBLP DOI BibTeX RDF
30	Jiyuan Bai, Xiang Wang, Zikang Zhang, Chang Cai, Gengsheng Chen	A Hierarchical Fault Injection System for RISC-V Processors Targeting Single Event Upsets in Flip-Flops.	ASICON	2021	DBLP DOI BibTeX RDF
30	Ehsan Mahmoodi, Morteza Gholipour	Design space exploration of low-power flip-flops in FinFET technology.	Integr.	2020	DBLP DOI BibTeX RDF
30	Mojtaba Noorallahzadeh, Mohammad Mosleh	Parity-preserving reversible flip-flops with low quantum cost in nanoscale.	J. Supercomput.	2020	DBLP DOI BibTeX RDF
30	Neethu Anna Sabu, K. Batri	Design and Analysis of Power Efficient TG Based Dual Edge Triggered Flip-Flops with Stacking Technique.	J. Circuits Syst. Comput.	2020	DBLP DOI BibTeX RDF
30	Cecilia Jarne	What you need to know to train recurrent neural networks to make Flip Flops memories and more.	CoRR	2020	DBLP BibTeX RDF
30	Lamjed Touil, Abdelaziz Hamdi, Ismail Gassoumi, Abdellatif Mtibaa	Design of Low-Power Structural FIR Filter Using Data-Driven Clock Gating and Multibit Flip-Flops.	J. Electr. Comput. Eng.	2020	DBLP DOI BibTeX RDF
30	Kentaro Kojima, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi	Evaluation of Heavy-Ion-Induced Single Event Upset Cross Sections of a 65-nm Thin BOX FD-SOI Flip-Flops Composed of Stacked Inverters.	IEICE Trans. Electron.	2020	DBLP DOI BibTeX RDF
30	Duckhoon Ro, Changhong Min, Myounggon Kang, Ik Joon Chang, Hyung-Min Lee	A Radiation-Hardened SAR ADC with Delay-Based Dual Feedback Flip-Flops for Sensor Readout Systems.	Sensors	2020	DBLP DOI BibTeX RDF
30	Atousa Jafari, Mohsen Raji, Behnam Ghavami	Timing Reliability Improvement of Master-Slave Flip-Flops in the Presence of Aging Effects.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
30	Oliver Schrape, Marko S. Andjelkovic, Anselm Breitenreiter, Alexey Balashov, Milos Krstic	Design Concept for Radiation-Hardening of Triple Modular Redundancy TSPC Flip-Flops.	DSD	2020	DBLP DOI BibTeX RDF
30	Sarah Azimi, Corrado De Sio, Luca Sterpone	In-Circuit Mitigation Approach of Single Event Transients for 45nm Flip-Flops.	IOLTS	2020	DBLP DOI BibTeX RDF
30	Maxim Ladnushkin	Flip-flops fanout splitting in scan designs.	ITC	2020	DBLP DOI BibTeX RDF
30	Anindita Chakraborty, Vivek Saurabh, Partha Sarathi Gupta, Rituraj Kumar, Saikat Majumdar, Smriti Das, Hafizur Rahaman 0001	In-memory designing of Delay and Toggle flip-flops utilizing Memristor Aided loGIC (MAGIC).	Integr.	2019	DBLP DOI BibTeX RDF
30	A. Udhayakumar, S. Padma	Low Power Magnetic Non-volatile Flip-Flops with Self-Time Logical Writing for High-End Processors.	Circuits Syst. Signal Process.	2019	DBLP DOI BibTeX RDF
30	Reza Binaei, Mohammad Gholami	Design of novel D flip-flops with set and reset abilities in quantum-dot cellular automata nanotechnology.	Comput. Electr. Eng.	2019	DBLP DOI BibTeX RDF
30	Trailokya Nath Sasamal, Ashutosh Kumar Singh 0001, Umesh Ghanekar	Design and Implementation of QCA D-Flip-Flops and RAM Cell Using Majority Gates.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
30	Shiva Taghipour, Rahebeh Niaraki Asli	Impact of Negative Bias Temperature Instability on Gate-All-Around Flip-Flops.	J. Electron. Test.	2019	DBLP DOI BibTeX RDF
30	Ziyi Wang, Zhaohao Wang, Yansong Xu, Bi Wu, Weisheng Zhao	Erase-hidden and Drivability-improved Magnetic Non-Volatile Flip-Flops with NAND-SPIN Devices.	CoRR	2019	DBLP BibTeX RDF
30	Abdullah Ash-Saki, Sung-Hao Lin, Mahabubul Alam, Sandeep Krishna Thirumala, Sumeet Kumar Gupta, Swaroop Ghosh	A Family of Compact Non-Volatile Flip-Flops With Ferroelectric FET.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
30	Mahendra Rathor, Anirban Sengupta	Enhanced Functional Obfuscation of DSP core using Flip-Flops and Combinational logic.	ICCE-Berlin	2019	DBLP DOI BibTeX RDF
30	Jun Furuta, Yuto Tsukita, Kodai Yamada, Mitsunori Ebara, Kentaro Kojima, Kazutoshi Kobayashi	Impact of Combinational Logic Delay for Single Event Upset on Flip Flops in a 65 nm FDSOI Process.	IRPS	2019	DBLP DOI BibTeX RDF
30	Oliver Schrape, Anselm Breitenreiter, Steffen Zeidler 0001, Milos Krstic	Aspects on Timing Modeling of Radiation-Hardness by Design Standard Cell-Based △TMR Flip-Flops.	DSD	2019	DBLP DOI BibTeX RDF
30	Marco Lanuzza, Raffaele De Rose, Felice Crupi, Massimo Alioto	An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops.	ICECS	2019	DBLP DOI BibTeX RDF
30	Pascal Andreas Meinerzhagen, Sandip Kundu, Andres Malavasi, Trang Nguyen, Muhammad M. Khellah, James W. Tschanz, Vivek De	Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS.	ESSCIRC	2019	DBLP DOI BibTeX RDF
30	Maike Taddiken, Steffen Paul, Dagmar Peters-Drolshagen	Charge-Based Model for Reliability Analysis Flow of Flip- Flops under Process Variation and Aging.	SMACD	2019	DBLP DOI BibTeX RDF
30	Zhengyu Chen 0002, Jie Gu 0001	A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops With 140Giga-Cell-Updates/s Throughput.	ISSCC	2019	DBLP DOI BibTeX RDF
30	Yuto Tsukita, Mitsunori Ebara, Jun Furuta, Kazutoshi Kobayashi	Soft-Error Tolerance Depending on Supply Voltage by Heavy Ions on Radiation-Hardened Flip Flops in a 65 nm Bulk Process.	ASICON	2019	DBLP DOI BibTeX RDF