Search results for "low-jitter"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Ro-Min Weng, Chun-Yu Liu, Yun-Chih Lu	A low jitter DLL-based pulsewidth control loop with wide duty cycle adjustment.	APCCAS	2008	DBLP DOI BibTeX RDF
16	Yutaka Nakanishi, Fuminori Kobayashi, Hitoshi Kondoh	Low-jitter PLL by interpolate compensation.	APCCAS	2008	DBLP DOI BibTeX RDF
16	Belal Helal	Techniques for low jitter clock multiplication.		2008	RDF
16	Ki-Won Lee, Joo-Hwan Cho, Byoung-Jin Choi, Geun-Il Lee, Ho-Don Jung, Woo-Young Lee, Ki-Chon Park, Yongsuk Joo, Jaehoon Cha, Young-Jung Choi, Patrick B. Moran, Jin-Hong Ahn	A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL.	IEEE J. Solid State Circuits	2007	DBLP DOI BibTeX RDF
16	Ding-Shiuan Shen, Shen-Iuan Liu	A Low-Jitter Spread Spectrum Clock Generator Using FDMP.	IEEE Trans. Circuits Syst. II Express Briefs	2007	DBLP DOI BibTeX RDF
16	Paul Madeira, Marc-Andre LaCroix, John Hogeboom	A low jitter clocking strategy for a 7.5-Gb/s SerDes array in 65nm CMOS technology.	ESSCIRC	2007	DBLP DOI BibTeX RDF
16	Zheng Xu 0003, Kenneth L. Shepard	Low-Jitter Active Deskewing Through Injection-Locked Resonant Clocking.	CICC	2007	DBLP DOI BibTeX RDF
16	Moo-young Kim, Dongsuk Shin, Hyunsoo Chae, Sunghwa Ok, Chulwoo Kim	A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time.	CICC	2007	DBLP DOI BibTeX RDF
16	Takashi Kawamoto, Tomoaki Takahashi, Hiromitsu Inada, Takayuki Noto	Low-jitter and Large-EMI-reduction Spread-spectrum Clock Generator with Auto-calibration for Serial-ATA Applications.	CICC	2007	DBLP DOI BibTeX RDF
16	Li-min Lee, Chih-Kong Ken Yang	An Adaptive Low-Jitter LC-Based Clock Distribution.	ISSCC	2007	DBLP DOI BibTeX RDF
16	Régis Roubadia, Sami Ajram, Guy Cathébras	Design of a Low Jitter Multi-Phase Realigned PLL in submicronic CMOS technology.	ISCAS	2007	DBLP DOI BibTeX RDF
16	Chih-Hsing Lin, Ching-Te Chiu	A 2.24GHz Wide Range Low Jitter DLL-Based Frequency Multiplier using PMOS Active Load for Communication Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
16	Adnan Gundel, William N. Carr	A Low Jitter CMOS PLL Clock Synthesizer with 20-400 MHz Locking Range.	ISCAS	2007	DBLP DOI BibTeX RDF
16	Xiang Gao 0002, Eric A. M. Klumperink, Bram Nauta	Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers.	ISCAS	2007	DBLP DOI BibTeX RDF
16	Vijay Khawshe, Pravin V. Kumar, Renu Rangnekar, Kapil Vyas, Kashi Prabu, Mahabaleshwara, Manish Jain, Navin K. Mishra, Abhijit Abhyankar	A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL.	VLSI Design	2007	DBLP DOI BibTeX RDF
16	Ruiyuan Zhang, George S. La Rue	Fast acquisition clock and data recovery circuit with low jitter.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
16	Daehyun Chung, Chunghyun Ryu, Hyungsoo Kim, Choonheung Lee, Jinhan Kim, Kicheol Bae, Jiheon Yu, Hoi-Jun Yoo, Joungho Kim	Chip-package hybrid clock distribution network and DLL for low jitter clock delivery.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
16	Mitsutoshi Yahara, Kuniaki Fujimoto, Hirofumi Sasaki, Takashi Shibuya, Yoshinori Higashi	All Digital Dividing Ratio Changeable PLL Using Delay Clock Pulse with Low Jitter.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2006	DBLP DOI BibTeX RDF
16	Hsiao-Yun Chen, Chih-Hsien Lin, Shyh-Jye Jou	DC-Balance Low-Jitter Transmission Code for 4-PAM Signaling.	IEEE Trans. Circuits Syst. II Express Briefs	2006	DBLP DOI BibTeX RDF
16	Chia-Hsiung Kao, Ping-Yu Tsai, Jian-Jia Lan	A Low Jitter High Linearity Voltage Controlled Ring Oscillator.	IMECS	2006	DBLP BibTeX RDF
16	Aditya Dua, Nicholas Bambos	Low-Jitter Scheduling Algorithms for Deadline-Aware Packet Switches.	GLOBECOM	2006	DBLP DOI BibTeX RDF
16	Jongshin Shin, Ilwon Seo, Jiyoung Kim, Seung-Hee Yang, Chiwon Kim, Jaehyun Park, Hyungoo Kim, Myoungbo Kwak, GhyBoong Hong	A Low-Jitter Added SSCG with Seamless Phase Selection and Fast AFC for 3rd Generation Serial-ATA.	CICC	2006	DBLP DOI BibTeX RDF
16	JunYoung Park, Michael P. Flynn	A Low Jitter Multi-Phase PLL with Capacitive Coupling.	CICC	2006	DBLP DOI BibTeX RDF
16	Lu Ping, Ye Fan 0001, Junyan Ren	A low-jitter frequency synthesizer with dynamic phase interpolation for high-speed Ethernet.	ISCAS	2006	DBLP DOI BibTeX RDF
16	Roberto Nonis, Nicola Da Dalt, Pierpaolo Palestri, Luca Selmi	Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
16	Nicola Da Dalt, Edwin Thaller, Peter Gregorius, Lajos Gazsi	A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
16	Kwang-Jin Lee, Hyo-Chang Kim, Uk-Rae Cho, Hyun-Geun Byun, Suki Kim	A Low Jitter ADPLL for Mobile Applications.	IEICE Trans. Electron.	2005	DBLP DOI BibTeX RDF
16	Youn-Gui Song, Young-Shig Choi	A Low Jitter and Fast Locking Phase-Lock Loop with Adaptive Bandwidth Controller.	J. Inform. and Commun. Convergence Engineering	2005	DBLP BibTeX RDF
16	Yaohui Jin, Jingjing Zhang, Weisheng Hu	A Genetic Algorithm of High-Throughput and Low-Jitter Scheduling for Input-Queued Switches.	ICNC (3)	2005	DBLP DOI BibTeX RDF
16	Byung-Guk Kim, Kwang-Il Oh, Lee-Sup Kim, Dae-Woo Lee	A 500MHz DLL with second order duty cycle corrector for low jitter.	CICC	2005	DBLP DOI BibTeX RDF
16	Alvin Leng Sun Loke, Robert K. Barnes, Tin Tin Wee, Michael M. Oshima, Charles E. Moore, Ronald R. Kennedy, Jim O. Barnes, Robert A. Zimmer, Kari L. Arave, H. Herman M. Pang, Tom E. Cynkar, Aaron M. Volz, Jim R. Pfiester, R. J. Martin, Robert H. Miller, David A. Hood, Gordon W. Motley, Ed J. Rojas, Tom M. Walley, Michael J. Gilsdorf	A versatile low-jitter PLL in 90-nm CMOS for SerDes transmitter clocking.	CICC	2005	DBLP DOI BibTeX RDF
16	Larry Li, Hou-Ming Chen, Robert Chen-Hao Chang	A low jitter delay-locked loop with a realignment duty cycle corrector.	SoCC	2005	DBLP DOI BibTeX RDF
16	Ram Kelkar, Dave Flye, Anjali Malladi, Joseph Natonio, Chri Scoville, Ken Short, Pradeep Thiagarajan	A Low Jitter Programmable Frequency Synthesizer for 4.25Gbps Serial Link Applications.	SoCC	2005	DBLP DOI BibTeX RDF
16	Sadeka Ali, Gregory Briggs, Martin Margala	A High Frequency, Low Jitter Auto-Calibration Phase-Locked Loop with Built-in-Self-Test.	DFT	2005	DBLP DOI BibTeX RDF
16	Wei-Ming Lin, Hong-Yi Huang	A low-jitter mutual-correlated pulsewidth control loop circuit.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
16	Hsiang-Hui Chang, Rong-Jyi Yang, Shen-Iuan Liu	Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection.	IEEE Trans. Circuits Syst. I Regul. Pap.	2004	DBLP DOI BibTeX RDF
16	Hsin-Chuan Chen, Jen-Shiun Chiang	A low-jitter phase-interpolation DDS using dual-slope integration.	IEICE Electron. Express	2004	DBLP DOI BibTeX RDF
16	Nicola Da Dalt, Edwin Thaller, Peter Gregorius, Lajos Gazsi	A low jitter triple-band digital LC PLL in 130nm CMOS.	ESSCIRC	2004	DBLP DOI BibTeX RDF
16		Notice of Violation of IEEE Publication PrinciplesA 2-5GHz low jitter 0.13 μm CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter [frequency synthesizer application].	CICC	2004	DBLP DOI BibTeX RDF
16	Roberto Nonis, Nicola Da Dalt, Pierpaolo Palestri, Luca Selmi	Modeling, design and characterization of a new low jitter analog dual tuning LC-VCO PLL architecture.	ISCAS (4)	2004	DBLP BibTeX RDF
16	Yong-Cheol Bae, Gu-Yeon Wei	A mixed PLL/DLL architecture for low jitter clock generation.	ISCAS (4)	2004	DBLP BibTeX RDF
16	Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu	A fast locking and low jitter delay-locked loop using DHDL.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
16	John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, Manjusha Shankaradas	Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
16	Yongchul Song, Beomsup Kim	Low-jitter digital timing recovery techniques for CAP-based VDSL applications.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
16	Gabriele Manganaro, Sung-Ung Kwak, SeongHwan Cho, Anurag Pulincherry	A behavioral modeling approach to the design of a low jitter clock source.	IEEE Trans. Circuits Syst. II Express Briefs	2003	DBLP DOI BibTeX RDF
16	Hsiang-Hui Chang, Shang-Ping Chen, Shen-Iuan Liu	A shifted-averaging VCO with precise multiphase outputs and low jitter operation.	ESSCIRC	2003	DBLP DOI BibTeX RDF
16	Frank Herzel, Wolfgang Winkler, Johannes Borngräber	An integrated 10 GHz quadrature LC-VCO in SiGe: C BiCMOS - technology for low-jitter applications.	CICC	2003	DBLP DOI BibTeX RDF
16	John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, Manjusha Shankaradas	Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL.	DAC	2003	DBLP DOI BibTeX RDF	adaptive bandwidth, clock multiplication, frequency synthesis, self biased, analog circuits, PLL, phase-locked loop, clock generation
16	Keiji Kishine, Kiyoshi Ishii, Haruhiko Ichino	Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX.	IEEE J. Solid State Circuits	2002	DBLP DOI BibTeX RDF
16	Sander L. J. Gierkink, Ed van Tuijl	A coupled sawtooth oscillator combining low jitter with high control linearity.	IEEE J. Solid State Circuits	2002	DBLP DOI BibTeX RDF
16	Se Jun Kim, Sang Hoon Hong, Jae-Kyung Wee, Joo-Hwan Cho, Pil Soo Lee, Jin-Hong Ahn, Jin-Yong Chung	A low-jitter wide-range skew-calibrated dual-loop DLL using antifuse circuitry for high-speed DRAM.	IEEE J. Solid State Circuits	2002	DBLP DOI BibTeX RDF
16	Sungkyung Park 0003, Changsik Yoo, Sin-Chong Park	A Low-Jitter Delay-Locked Loop with Harmonic-Lock Prevention.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2002	DBLP BibTeX RDF
16	Debapriya Sahu	A Completely Integrated Low Jitter CMOS PLL for Analog Front Ends in Systems on Chip Environment.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
16	Adrian Maxim, Baker Scott, Edmund M. Schneider, Melvin Hagge, Steve Chacko, Dan Stiurca	A low-jitter 125-1250-MHz process-independent and ripple-poleless 0.18-μm CMOS PLL based on a sample-reset loop filter.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF
16	Dorin Emil Calbaza, Yvon Savaria	Direct digital frequency synthesis of low-jitter clocks.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF
16	Aman Kansal, Abhay Karandikar	Adaptive delay estimation for low jitter audio over Internet.	GLOBECOM	2001	DBLP DOI BibTeX RDF
16	Johan van der Tang, Cicero S. Vaucher	Design and optimization of a low jitter clock-conversion PLL for SONET/SDH optical transmitters.	ICECS	2001	DBLP DOI BibTeX RDF
16	Kuo-Hsing Cheng, Tse-Hua Yao, Shu-Yu Jiang, Wei-Bin Yang	A difference detector PFD for low jitter PLL.	ICECS	2001	DBLP DOI BibTeX RDF
16	Hee-Tae Ahn, David J. Allstot	A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
16	Jae Joon Kim, Sang-Bo Lee, Tae-Sung Jung, Chang-Hyun Kim, Soo-In Cho, Beomsup Kim	A low-jitter mixed-mode DLL for high-speed DRAM applications.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
16	Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim	An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
16	Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen	A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop.	VLSI Design	2000	DBLP DOI BibTeX RDF
16	Dorin Emil Calbaza, Yvon Savaria	Direct digital frequency synthesis of low-jitter clocks.	CICC	2000	DBLP DOI BibTeX RDF
16	Youcef Fouzar, Mohamad Sawan, Yvon Savaria	A new fully integrated CMOS phase-locked loop with low jitter and fast lock time.	ISCAS	2000	DBLP DOI BibTeX RDF
16	David J. Foley, Michael P. Flynn	A 3.3 V, 1.6 GHz, low-jitter, self-correcting DLL based clock synthesizer in 0.5 μm CMOS.	ISCAS	2000	DBLP DOI BibTeX RDF
16	David W. Boerstler	A low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
16	Woogeun Rhee	Design of low-jitter 1-GHz phase-locked loops for digital clock generation.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
16	Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen	A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
16	Nicholas G. Paulter Jr.	Low-jitter trigger system for pulse calibration and intercomparison of high-speed samplers.	IEEE Trans. Instrum. Meas.	1998	DBLP DOI BibTeX RDF
16	Sungjoon Kim, Kyeongho Lee, Yongsam Moon, Deog-Kyoon Jeong, Yunho Choi, Hyung Kyu Lim	A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
16	Howard C. Yang, Lance K. Lee, Ramon S. Co	A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V/5 V operation.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
16	John G. Maneatis	Low-jitter process-independent DLL and PLL based on self-biased techniques.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
16	Oliver Collins	The design of low jitter hard limiters.	IEEE Trans. Commun.	1996	DBLP DOI BibTeX RDF
16	Beomsup Kim, Todd C. Weigandt, Paul R. Gray	PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design.	ISCAS	1994	DBLP DOI BibTeX RDF
16	S. Wegerif, William Redman-White	An Integrated CMOS Image-rejection Mixer System for Low-jitter Secondary Frequency References.	ISCAS	1993	DBLP BibTeX RDF
15	Teera Phatrapornnant, Michael J. Pont	Reducing Jitter in Embedded Systems Employing a Time-Triggered Software Architecture and Dynamic Voltage Scaling.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	scheduling, Low power design, real-time systems and embedded systems
15	Hassan El Aabbaoui, B. Gorisse, Nathalie Rolland, Aziz Benlarbi-Delaï, J.-F. Lampin, Paul-Alain Rolland, V. Allouche, N. Fel, B. Riondet, P. Leclerc	20GHz bandwidth digitizer for single shot analysis.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Ming-Ju Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John H. Edmondson, John W. Poulton	CMOS High-Speed I/Os - Present and Future.	ICCD	2003	DBLP DOI BibTeX RDF
15	Viktor Fischer, Milos Drutarovský	True Random Number Generator Embedded in Reconfigurable Hardware.	CHES	2002	DBLP DOI BibTeX RDF
15	Luís Almeida 0001, José Alberto Fonseca	Analysis of a Simple Model for Non-Preemptive Blocking-Free Scheduling.	ECRTS	2001	DBLP DOI BibTeX RDF
11	Jonathan Rosenfeld, Eby G. Friedman	Design methodology for global resonant H-tree clock distribution networks.	ISCAS	2006	DBLP DOI BibTeX RDF
11	Jochen Rivoir	Low-Cost Analog Signal Generation Using a Pulse-Density Modulated Digital ATE Channel.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF	low-cost ATE, multi-site test, mixed-signal test, concurrent test, low-cost test, test resource partitioning
11	Jörg Diederich 0001, Mark Doll, Martina Zitterbart	Best-Effort Low-Delay Service.	LCN	2003	DBLP DOI BibTeX RDF
11	Frank O'Mahony, C. Patrick Yue, Mark Horowitz, S. Simon Wong	Design of a 10GHz clock distribution network using coupled standing-wave oscillators.	DAC	2003	DBLP DOI BibTeX RDF	distributed oscillators, on-chip phase measurement, resonant clocking, salphasic, standing wave, clock distribution, coupled oscillators
11	Won-Joo Hwang, Hideki Tode, Koso Murakami	QoS Based MAC Protocol for the Home Network.	LCN	2001	DBLP DOI BibTeX RDF
10	Vinayak Honkote, Baris Taskin	Zero clock skew synchronization with rotary clocking technology.	ISQED	2009	DBLP DOI BibTeX RDF
10	Ben Greenstein, Christopher Mar, Alex Pesterev, Shahin Farshchi, Eddie Kohler, Jack W. Judy, Deborah Estrin	Capturing high-frequency phenomena using a bandwidth-limited sensor network.	SenSys	2006	DBLP DOI BibTeX RDF	signal processing frameworks, sensor networks, acoustics, motes, health monitoring
10	Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale, Richard B. Brown	A 16-bit, low-power microsystem with monolithic MEMS-LC clocking.	ASP-DAC	2006	DBLP DOI BibTeX RDF
10	John P. Carr, Brian M. Frank	A 27 GHZ Phase-Lock Loop Phase Detector.	CCECE	2006	DBLP DOI BibTeX RDF
10	A. M. Majid, David C. Keezer, J. V. Karia	A 5 Gbps Wafer-Level Tester.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
10	Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale	A 16-bit low-power microcontroller with monolithic MEMS-LC clocking.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
10	Tales Heimfarth, Marcelo Götz, Franz J. Rammig, Flávio Rech Wagner	RTC: A Real-Time Communication Middleware on Top of RTAI-Linux .	ISORC	2003	DBLP DOI BibTeX RDF
10	Liqiang Zhao, Changxin Fan	A Multi-Cell Dynamic Reservation Protocol for Multimedia over IEEE 802.11 Ad Hoc WLAN.	AINA	2003	DBLP DOI BibTeX RDF	WLAN, Ad hoc, CBR, VBR, ABR
10	Won-Joo Hwang, Makoto Wada, Hideki Tode, Koso Murakami	HomeMAC: QoS-based MAC protocol for the home network.	ISCC	2002	DBLP DOI BibTeX RDF
10	Youcef Fouzar, Yvon Savaria, Mohamad Sawan	A new controlled gain phase-locked loop technique.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
8	Tran Cong Thien Qui, Shang Ping Lee, William Russell Pensyl, Daniel Keith Jernigan	Robust Hybrid Tracking with Life-Size Avatar in Mixed Reality Environment.	HCI (13)	2009	DBLP DOI BibTeX RDF
8	William Russell Pensyl, Daniel Keith Jernigan, Tran Cong Thien Qui, Hsin Pei Fang, Shang Ping Lee	Large area robust hybrid tracking with life-size avatar in mixed reality environment: for cultural and historical installation.	VRCAI	2008	DBLP DOI BibTeX RDF	cultural and historical installation, hybrid vision and inertial sensor, localization, mixed reality
8	José Carlos da Silva 0001, Michal Hujesko, João Varela	Design of a Data Concentrator Card for the Readout of the Compact Muon Solenoid Electromagnetic Calorimeter.	DELTA	2008	DBLP DOI BibTeX RDF
8	Shilpa Ambarish, Mahmoud Fawzy Wagdy	A Wide-Band Digital Phase-Locked Looop.	ITNG	2006	DBLP DOI BibTeX RDF
8	Djakhongir Siradjev, Ivan Gurin, Young-Tak Kim	Scalable DiffServ-over-MPLS Traffic Engineering with Per-flow Traffic Policing.	APNOMS	2006	DBLP DOI BibTeX RDF	DiffServ-over-MPLS, QoS, scalability, network processors