Search results for "manufacturability"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Chunyang Feng, Hai Zhou 0001, Changhao Yan, Jun Tao 0001, Xuan Zeng 0001	Provably good and practically efficient algorithms for CMP dummy fill.	DAC	2009	DBLP DOI BibTeX RDF	covering linear programming, dummy fill problem, design for manufacturability
18	Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang	Metal-density driven placement for cmp variation and routability.	ISPD	2008	DBLP DOI BibTeX RDF	VLSI, placement, physical design, manufacturability
18	Arthur Nieuwoudt, Jamil Kawa, Yehia Massoud	Impact of dummy filling techniques on interconnect capacitance and planarization in nano-scale process technology.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	design for manufacturability, dummy fill
18	Arthur Nieuwoudt, Jamil Kawa, Yehia Massoud	Investigating the Impact of Fill Metal on Crosstalk-Induced Delay and Noise.	ISQED	2008	DBLP DOI BibTeX RDF	fill generation, crosstalk, Design for manufacturability, dummy fill
18	Hailong Jiao, Lan Chen	Cellwise OPC Based on Reduced Standard Cell Library.	ISQED	2008	DBLP DOI BibTeX RDF	cellwise OPC, reduced standard cell library, design for manufacturability
18	Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan	ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction.	DAC	2008	DBLP DOI BibTeX RDF	routing, VLSI, manufacturability, OPC, lithography
18	Payman Zarkesh-Ha, Ken Doniger	Stochastic interconnect layout sensitivity model.	SLIP	2007	DBLP DOI BibTeX RDF	critical area analysis, layout sensitivity, reliability, stochastic model, yield, design for manufacturability, defect density
18	Philippe Magarshack	Design challenges in 45nm and below: DFM, low-power and design for reliability.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	design for reliability, low-power design, design for manufacturability
18	Kevin Lucas, Chi-Min Yuan, Robert Boone, Karl Wimmer, Kirk Strozewski, Olivier Toublan	Logic Design for Printability Using OPC Methods.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	optical proximity correction (OPC), reticle enhancement technology (RET), design for manufacturability (DFM)
18	Minsik Cho, David Z. Pan, Hua Xiang 0001, Ruchir Puri	Wire density driven global routing for CMP variation and timing.	ICCAD	2006	DBLP DOI BibTeX RDF	performance, VLSI, manufacturability, global routing
18	Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han	Novel full-chip gridless routing considering double-via insertion.	DAC	2006	DBLP DOI BibTeX RDF	redundant via insertion, routing, manufacturability
18	Di Wu 0017, Jiang Hu, Rabi N. Mahapatra	Coupling aware timing optimization and antenna avoidance in layer assignment.	ISPD	2005	DBLP DOI BibTeX RDF	VLSI, interconnect, probabilistic modeling, physical design, crosstalk, design for manufacturability (DFM), antenna effect
18	Murari Mani, Anirudh Devgan, Michael Orshansky	An efficient algorithm for statistical minimization of total power under timing yield constraints.	DAC	2005	DBLP DOI BibTeX RDF	manufacturability, leakage, statistical optimization
18	Naveed A. Sherwani, Susan Lippincott Mack, Alex Alexanian, Premal Buch, Carlo Guardiani, Harold Lehon, Peter Rabkin, Atul Sharan	DFM rules!	DAC	2005	DBLP DOI BibTeX RDF	design for manufacturability, yield optimization
18	Puneet Gupta 0001, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester	Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions.	DAC	2005	DBLP DOI BibTeX RDF	ACLV, layout, manufacturability, compensation, variation, focus
18	Matt Nowak, Riko Radojcic	Are there economic benefits in DFM?	DAC	2005	DBLP DOI BibTeX RDF	fabless, foundries, DFM, design for manufacturability
18	Marco Ottavi, Xiaopeng Wang, Fred J. Meyer, Fabrizio Lombardi	Simulation of reconfigurable memory core yield.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	Markov chain, manufacturability, yield, defect tolerance
18	Puneet Gupta 0001, Fook-Luen Heng	Toward a systematic-variation aware timing methodology.	DAC	2004	DBLP DOI BibTeX RDF	ACLV, layout, manufacturability, OPC, lithography
18	Lars Liebmann	Layout impact of resolution enhancement techniques: impediment or opportunity?	ISPD	2003	DBLP DOI BibTeX RDF	radically restricted designs, resolution enhancement techniques, design for manufacturability, lithography
18	Puneet Gupta 0001, Andrew B. Kahng, Dennis Sylvester, Jie Yang 0010	A cost-driven lithographic correction methodology based on off-the-shelf sizing tools.	DAC	2003	DBLP DOI BibTeX RDF	VLSI manufacturability, yield, OPC, lithography, RET
18	Yu Chen 0005, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky	Closing the smoothness and uniformity gap in area fill synthesis.	ISPD	2002	DBLP DOI BibTeX RDF	VLSI manufacturability, density analysis, dummy fill problem, monte-carlo, chemical-mechanical polishing
18	Vipul Singhal, C. B. Keshav, K. G. Surnanth, P. R. Suresh	Transistor Flaring in Deep Submicron-Design Considerations.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Deep Submicron (DSM), pullback, photolithography, Subwavelength-lithography, Optical Proximity Correction (OPC), SPICE-models, standard-ce1l library, Design for Manufacturability (DFM)
18	JungHyun Han, Inho Han	Manufacturable feature recognition and its integration with process planning.	Symposium on Solid Modeling and Applications	1999	DBLP DOI BibTeX RDF	feature dependency, machining sequence, manufacturability, feature recognition, process planning
18	Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, P. Simon	Design-Manufacturing Interface: Part II - Applications.	DATE	1998	DBLP DOI BibTeX RDF	metal utilization, etch rate variation, manufacturability, yield, critical area, antenna effect
18	Wojciech Maly, Pranab K. Nag, Hans T. Heineken, Jitendra Khare	Design-Manufacturing Interface: Part I - Vision.	DATE	1998	DBLP DOI BibTeX RDF	design, synthesis, manufacturability, yield, design rules
18	Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar	A hierarchical decomposition methodology for multistage clock circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	performance driven router, routing, process variations, manufacturability, clock
12	Jin Hu, Jarrod A. Roy, Igor L. Markov	Completing high-quality global routes.	ISPD	2010	DBLP DOI BibTeX RDF	global routing
12	Bao Liu 0001	Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture.	ASP-DAC	2009	DBLP DOI BibTeX RDF
12	Sandor Markon, Satoshi Maekawa	An improved optical device for floating displays.	IUCS	2009	DBLP DOI BibTeX RDF	dihedral corner reflector array, floating images, 3D display
12	Nancy Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li 0001, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi	The impact of BEOL lithography effects on the SRAM cell performance and yield.	ISQED	2009	DBLP DOI BibTeX RDF
12	Chun-Yu Chuang, Wai-Kei Mak	Accurate closed-form parameterized block-based statistical timing analysis applying skew-normal distribution.	ISQED	2009	DBLP DOI BibTeX RDF
12	Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera	Erect of regularity-enhanced layout on printability and circuit performance of standard cells.	ISQED	2009	DBLP DOI BibTeX RDF
12	Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang	Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
12	YuHua Cheng	A glance of technology efforts for design-for-manufacturing in nano-scale CMOS processes.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	nano-CMOS IC design, IC design methodology, CMOS design technology platform, design-for-manufacturing (DFM), design-for-yield
12	Myungsu Choi, Minsu Choi	Scalability of Globally Asynchronous QCA (Quantum-Dot Cellular Automata) Adder Design.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	QCA (quantum-dot cellular automata), Asynchronous architecture, Layout timing problem, Scalability, Robustness
12	Jason Cong, Yi Zou	Lithographic aerial image simulation with FPGA-based hardwareacceleration.	FPGA	2008	DBLP DOI BibTeX RDF	co-processor acceleration, lithography simulation, FPGA
12	Jason G. Brown, Brian Taylor, Ronald D. Blanton, Larry T. Pileggi	Automated Testability Enhancements for Logic Brick Libraries.	DATE	2008	DBLP DOI BibTeX RDF
12	Petr Mikusek, Vaclav Dvorak	On Lookup Table Cascade-Based Realizations of Arbiters.	DSD	2008	DBLP DOI BibTeX RDF
12	David Z. Pan	Synergistic modeling and optimization for nanometer IC design/manufacturing integration.	SBCCI	2008	DBLP DOI BibTeX RDF	design for manufacturing
12	David Z. Pan	Lithography friendly routing: from construct-by-correction to correct-by-construction.	SBCCI	2008	DBLP DOI BibTeX RDF	routing
12	Michael D. Moffitt, Jarrod A. Roy, Igor L. Markov	The coming of age of (academic) global routing.	ISPD	2008	DBLP DOI BibTeX RDF	optimization, routing, VLSI, benchmarks, computer-aided design, congestion, global routing, wirelength
12	David M. Krum, Jens Faenger, Brian Lathrop, Jo Ann G. Sison, Annie Lien	All roads lead to CHI: interaction in the automobile.	CHI Extended Abstracts	2008	DBLP DOI BibTeX RDF	driver interaction, cars, automotive industry, driver information systems, special interest group
12	Vaclav Dvorak	Communication Performance of Mesh- and Ring-Based NoCs.	ICN	2008	DBLP DOI BibTeX RDF	Tera-scale platform, Networks on chip, collective communications
12	Guo Yu, Peng Li 0001	Yield-aware hierarchical optimization of large analog integrated circuits.	ICCAD	2008	DBLP DOI BibTeX RDF
12	Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz	Is there always performance overhead for regular fabric?	ICCD	2008	DBLP DOI BibTeX RDF
12	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	flash adc, nano-cmos, ti comparator, process variation, analog-to-digital converter, low voltage, high speed
12	Srinivasa R. S. T. G, Srivatsava Jandhyala, Narahari Tondamuthuru R	Process Variability Analysis in DSM Through Statistical Simulations and its Implications to Design Methodologies.	ISQED	2008	DBLP DOI BibTeX RDF	Design Methodologies, Random, DSM, Variations, Systematic
12	Nathaniel J. August	A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel's Test Chips.	ISQED	2008	DBLP DOI BibTeX RDF	pre-silicon, validation, mixed-signal
12	Qing Su, Charles C. Chiang, Jamil Kawa	Hotspot Based Yield Prediction with Consideration of Correlations.	ISQED	2008	DBLP DOI BibTeX RDF	Systematic Yield, DFM (design for manufacturing), correlation, Yield, Hotspot, Yield Prediction
12	Fadi J. Kurdahi, Nikil D. Dutt, Ahmed M. Eltawil, Sani R. Nassif	Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips.	VLSI Design	2008	DBLP DOI BibTeX RDF
12	Sachin S. Sapatnekar, Eshel Haritan, Kurt Keutzer, Anirudh Devgan, Desmond Kirkpatrick, Stephen Meier, Duaine Pryor, Tom Spyrou	Reinventing EDA with manycore processors.	DAC	2008	DBLP DOI BibTeX RDF	parallelization, CAD, software, multicore, EDA, speedup, manycore
12	Tarek A. El-Moselhy, Ibrahim M. Elfadel, David Widiger	Efficient algorithm for the computation of on-chip capacitance sensitivities with respect to a large set of parameters.	DAC	2008	DBLP DOI BibTeX RDF	sensitivity analysis, capacitance extraction, adjoint method
12	Fan-Tien Cheng, Yeh-Tung Chen, Yu-Chuan Su, Deng-Lin Zeng	Method for Evaluating Reliance Level of a Virtual Metrology System.	ICRA	2007	DBLP DOI BibTeX RDF
12	Rishi Bhooshan, Bindu P. Rao	Optimum IR drop models for estimation of metal resource requirements for power distribution network.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
12	Davide Pandini, Giuseppe Desoli, Alessandro Cremonesi	Computing and design for software and silicon manufacturing.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
12	Andrew B. Kahng	Design challenges at 65nm and beyond.	DATE	2007	DBLP DOI BibTeX RDF
12	Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab	Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches.	ASP-DAC	2007	DBLP DOI BibTeX RDF	reconfigurable instant-on system, ultralow-power reconfigurable computing, complementary nanoelectromechanical carbon nanotube switches, coplanar carbon nanotubes, low operation voltages, built-in energy storage, CNEMS, stable on-off state, latching mechanism, nonvolatile memory-mode operation, CMOS transistors, system development, leakage current
12	Jun-Fu Huang, Victor C. Y. Chang, Sally Liu, Kelvin Y. Y. Doong, Keh-Jeng Chang	Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM.	ASP-DAC	2007	DBLP DOI BibTeX RDF
12	Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang	Efficient obstacle-avoiding rectilinear steiner tree construction.	ISPD	2007	DBLP DOI BibTeX RDF	routing, spanning tree, physical design, Steiner tree
12	David M. Krum, Dietrich Manstetten, Clifford Nass, K. Venkatesh Prasad, Roberto Sicconi	Taking CHI for a drive: interaction in the car.	CHI Extended Abstracts	2007	DBLP DOI BibTeX RDF	driver interaction, panel discussion, automotive industry, driver information systems
12	Davide Pandini	Innovative Design Platforms for Reliable SoCs in Advanced Nanometer Technologies.	IOLTS	2007	DBLP DOI BibTeX RDF
12	Jamil Kawa, Charles C. Chiang	DFM issues for 65nm and beyond.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	DFY, DFM
12	Michele Favalli	Delay Fault Detection Problems in Circuits Featuring a Low Combinational Depth.	DFT	2007	DBLP DOI BibTeX RDF
12	Rishi Bhooshan	Novel and Efficient IR-Drop Models for Designing Power Distribution Network for Sub-100nm Integrated Circuits.	ISQED	2007	DBLP DOI BibTeX RDF
12	Duane S. Boning, Karthik Balakrishnan, Hong Cai, Nigel Drego, Ali Farahanchi, Karen Gettings, Daihyun Lim, Ajay Somani, Hayden Taylor, Daniel Truque, Xiaolin Xie	Variation.	ISQED	2007	DBLP DOI BibTeX RDF
12	René Penning de Vries	Systems, Nano-technology and SiP.	VLSI Design	2007	DBLP DOI BibTeX RDF
12	Sankara Hari Gopalakrishnan, Krishnan Suresh	Estimating the impact of large design changes on field problems.	Symposium on Solid and Physical Modeling	2007	DBLP DOI BibTeX RDF	feature sensitivity, topological sensitivity, features, parametric optimization, design parameters
12	Wojciech Maly, Yi-Wei Lin, Malgorzata Marek-Sadowska	OPC-Free and Minimally Irregular IC Design Style.	DAC	2007	DBLP DOI BibTeX RDF
12	Norbert Dumas, Florence Azaïs, Laurent Latorre, Pascal Nouet	Electro-thermal Stimuli for MEMS Testing in FSBM Technology.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	bulk micromachining, electro-thermal stimuli, testing, defects, MEMS
12	Sandip Kundu	A design for failure analysis (DFFA) technique to ensure incorruptible signatures.	DATE	2006	DBLP DOI BibTeX RDF
12	Kuang-Yao Lee, Ting-Chi Wang	Post-routing redundant via insertion for yield/reliability improvement.	ASP-DAC	2006	DBLP DOI BibTeX RDF
12	Ding-Ming Kwai, Ching-Hua Hsiao, Chung-Ping Kuo, Chi-Hsien Chuang, Min-Chung Hsu, Yi-Chun Chen, Yu-Ling Sung, Hsien-Yu Pan, Chia-Hsin Lee, Meng-Fan Chang, Yung-Fa Chou	SRAM Cell Current in Low Leakage Design.	MTDT	2006	DBLP DOI BibTeX RDF
12	Jirí Jaros, Milos Ohlídal, Václav Dvorák	Complexity of Collective Communications on NoCs.	PARELEC	2006	DBLP DOI BibTeX RDF
12	Xiaoping Tang, Xin Yuan	Technology migration techniques for simplified layouts with restrictive design rules.	ICCAD	2006	DBLP DOI BibTeX RDF
12	Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan	An accurate sparse matrix based framework for statistical static timing analysis.	ICCAD	2006	DBLP DOI BibTeX RDF
12	Dezhen Zhang, Tian Chang, Rui Li 0055, Xiaopeng Wei	Evaluating design concepts using fuzzy arithmetic operations.	ISDA (1)	2006	DBLP DOI BibTeX RDF
12	Minsu Choi, Myungsu Choi, Zachary D. Patitz, Nohpill Park	Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design.	DFT	2006	DBLP DOI BibTeX RDF
12	Robert C. Aitken	DFM Metrics for Standard Cells.	ISQED	2006	DBLP DOI BibTeX RDF
12	C. Tabery, M. Craig, Gert Burbach, B. Wagner, S. McGowan, P. Etter, S. Roling, C. Haidinyak, E. Ehrichs	Process Window and Device Variations Evaluation using Array-Based Characterization Circuits.	ISQED	2006	DBLP DOI BibTeX RDF	transistor array, transistor matching, via yield, DOE ROM, novel test circuits, DFM
12	Artur Balasinski	Question: DRC or DfM ? Answer: FMEA and ROI.	ISQED	2006	DBLP DOI BibTeX RDF
12	Lawrence S. Melvin III, Daniel N. Zhang, Kirk J. Strozewski, Skye Wolfer	The Use of the Manufacturing Sensitivity Model Forms to Comprehend Layout Manufacturing Robustness For Use During Device Design.	ISQED	2006	DBLP DOI BibTeX RDF
12	Rasit Onur Topaloglu	Monte Carlo-Alternative Probabilistic Simulations for Analog Systems.	ISQED	2006	DBLP DOI BibTeX RDF
12	Amir Hossein Yamini, Vijaya Kumar Devabhaktuni	Equivalent Circuit and Electromagnetic Based CAD Tool for Dual-Mode Ku-Band Elliptic and Butterworth Filters.	CCECE	2006	DBLP DOI BibTeX RDF
12	Rasit Onur Topaloglu	Early, Accurate and Fast Yield Estimation through Monte Carlo-Alternative Probabilistic Behavioral Analog System Simulations.	VTS	2006	DBLP DOI BibTeX RDF
12	Mircea R. Stan, Garrett S. Rose, Matthew M. Ziegler	Hybrid CMOS/Molecular Electronic Circuits.	VLSI Design	2006	DBLP DOI BibTeX RDF
12	Sara McMains	Design for manufacturing feedback at interactive rates.	Symposium on Solid and Physical Modeling	2006	DBLP DOI BibTeX RDF
12	Vijay Pitchumani	A Hitchhiker's Guide to the DFM Universe.	APCCAS	2006	DBLP DOI BibTeX RDF
12	Xianlong Hong, Yici Cai, Hailong Yao, Duo Li	DFM-aware Routing for Yield Enhancement.	APCCAS	2006	DBLP DOI BibTeX RDF
12	El-Sayed Aziz, Constantin Chassapis	A decision-making framework model for design and manufacturing of mechanical transmission system development.	Eng. Comput.	2005	DBLP DOI BibTeX RDF	Intelligent design, Internet, Knowledge-based system, Web-based system, Concurrent engineering, Gear
12	Yu Chen 0005, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky, Yuhong Zheng	Compressible area fill synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
12	Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar	Placement and Routing in 3D Integrated Circuits.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	VLSI, Placement and routing
12	Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wong	CMP aware shuttle mask floorplanning.	ASP-DAC	2005	DBLP DOI BibTeX RDF
12	Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy	On Improving Defect Coverage of Stuck-at Fault Tests.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
12	Mehrdad Reshadi, Daniel Gajski	A cycle-accurate compilation algorithm for custom pipelined datapaths.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	NISC, cycle-accurate compiler, scheduling
12	Alex Yvart, Stefanie Hahmann, Georges-Pierre Bonneau	Smooth Adaptive Fitting of 3D Models Using Hierarchical Triangular Splines.	SMI	2005	DBLP DOI BibTeX RDF
12	Jaeho Lee 0004, Joon Young Park, Deok-Soo Kim, Hyun-Chan Lee	Triangular Prism Generation Algorithm for Polyhedron Decomposition.	ICCSA (3)	2005	DBLP DOI BibTeX RDF
12	Brian Stephen Smith, Sung Kyu Lim	QCA channel routing with wire crossing minimization.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	QCA channel routing, weighted minimum feedback edge set, wire crossing minimization
12	Vaclav Dvorak	Scheduling Collective Communications on Wormhole Fat Cubes.	SBAC-PAD	2005	DBLP DOI BibTeX RDF
12	R. Castagnetti, R. Venkatraman, Brandon Bartz, Carl Monzel, T. Briscoe, Andres Teene, S. Ramesh 0004	A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC.	ISQED	2005	DBLP DOI BibTeX RDF
12	Hua Xiang 0001, Kai-Yuan Chao, Martin D. F. Wong	Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer.	ISQED	2005	DBLP DOI BibTeX RDF	Layer migration, Max-cut, Capacitance coupling