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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 322 occurrences of 165 keywords
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Results
Found 391 publication records. Showing 391 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
18 | Manuel Hohenauer, Felix Engel 0001, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
A SIMD optimization framework for retargetable compilers. |
ACM Trans. Archit. Code Optim. |
2009 |
DBLP DOI BibTeX RDF |
SIMD, vectorization, ASIP, subword parallelism, retargetable compilers |
18 | Teemu Pitkänen, Jarno K. Tanskanen, Risto Mäkinen, Jarmo Takala |
Parallel Memory Architecture for Application-Specific Instruction-Set Processors. |
J. Signal Process. Syst. |
2009 |
DBLP DOI BibTeX RDF |
TTA, Transport triggered architecture, Low power, ASIP, Application-specific instruction-set processors, Parallel memory |
18 | Nicolas Beucher, Normand Bélanger, Yvon Savaria, Guy Bois |
High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse. |
J. Signal Process. Syst. |
2009 |
DBLP DOI BibTeX RDF |
ASIP, Acceleration, Video processing, Data reuse |
18 | Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovic, Qin Zhao, Frank Bouwens, Jos Hulzink, Jef L. van Meerbergen |
Design of 100 µW Wireless Sensor Nodes for Biomedical Monitoring. |
J. Signal Process. Syst. |
2009 |
DBLP DOI BibTeX RDF |
Low power, ASIP, ECG, Clock gating, Wireless sensor node |
18 | Mathieu Allard, Patrick Grogan, Jean-Pierre David |
A Scalable Architecture for Multivariate Polynomial Evaluation on FPGA. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
High performance computing, ASIP, multivariate, Polynomial evaluation |
18 | Ya-Shuai Lü, Li Shen 0007, Zhiying Wang 0003, Nong Xiao |
Dynamically utilizing computation accelerators for extensible processors in a software approach. |
CODES+ISSS |
2009 |
DBLP DOI BibTeX RDF |
computation accelerator, ASIP, dynamic binary translation |
18 | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose |
Fine-grain performance scaling of soft vector processors. |
CASES |
2009 |
DBLP DOI BibTeX RDF |
VESPA, soft vector processor, viram, FPGA, custom, SIMD, vector, ASIP, microarchitecture, application specific, soft processor |
18 | Unmesh D. Bordoloi, Huynh Phung Huynh, Samarjit Chakraborty, Tulika Mitra |
Evaluating design trade-offs in customizable processors. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
multi-objective design space exploration, pareto-optimal curve, processor customization, ASIP |
18 | Jae Hyun Baek, Sung Dae Kim, Myung Hoon Sunwoo |
SPOCS: Application Specific Signal Processor for OFDM Communication Systems. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
ASSP, Communications, FFT, DSP, OFDM, Application-Specific Instruction-Set Processor (ASIP), Bit manipulation |
18 | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose |
VESPA: portable, scalable, and flexible FPGA-based vector processors. |
CASES |
2008 |
DBLP DOI BibTeX RDF |
SPREE, VESPA, VIRAM, FPGA, custom, SIMD, vector, ASIP, microarchitecture, application specific, soft processor |
18 | Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song 0002, Satoshi Goto |
HyMacs: hybrid memory access optimization based on custom-instruction scheduling. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
asip, cad algorithm, hardware/software co-design |
18 | Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski |
C-based design flow: a case study on G.729A for voice over internet protocol (VoIP). |
DAC |
2008 |
DBLP DOI BibTeX RDF |
C-based design flow, C-to-RTL, G729A, NISC, HLS, VoIP, ASIP |
18 | Bita Gorjiara, Daniel Gajski |
Automatic architecture refinement techniques for customizing processing elements. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
GNR, nanocoded architectures, no-instruction-set computer (NISC), refinement, high-level synthesis, power, ASIP, datapath, netlist |
18 | Lars Bauer, Muhammad Shafique 0001, Jörg Henkel |
Run-time instruction set selection in a transmutable embedded processor. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
extensible embedded processors, special instruction, reconfigurable computing, ASIP, run-time adaptation |
18 | Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar |
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. |
Int. J. Parallel Program. |
2007 |
DBLP DOI BibTeX RDF |
Performance evaluation, VLIW, ASIP, Clustered VLIW processors |
18 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt |
Instruction set synthesis with efficient instruction encoding for configurable processors. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
ISA customization and specialization, bitwidth-economical, Application-specific instruction set processor (ASIP), configurable processor, instruction encoding |
18 | Anup Gangwar, M. Balakrishnan, Anshul Kumar |
Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
performance evaluation, VLIW, ASIP, clustered VLIW processors |
18 | Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
A low power VLIW processor generation method by means of extracting non-redundant activation conditions. |
CODES+ISSS |
2007 |
DBLP DOI BibTeX RDF |
low power, ASIP, clock gating, VLIW processor |
18 | Hanno Scharwächter, Jonghee M. Youn, Rainer Leupers, Yunheung Paek, Gerd Ascheid, Heinrich Meyr |
A code-generator generator for multi-output instructions. |
CODES+ISSS |
2007 |
DBLP DOI BibTeX RDF |
ISS, code-selection, compiler/architecture co-design, ASIP |
18 | I-Wei Wu, Shih-Chia Huang, Chung-Ping Chung, Jean Jyh-Jiun Shann |
Instruction Set Extension Generation with Considering Physical Constraints. |
HiPEAC |
2007 |
DBLP DOI BibTeX RDF |
Pipestage Timing Constraint, ASIP, Instruction set extension, Extensible Processors |
18 | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose |
Application-specific customization of soft processor microarchitecture. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
Nios, RTL generation, SPREE, FPGA, customization, embedded processor, ASIP, microarchitecture, application specific, soft processor |
18 | Swarnalatha Radhakrishnan, Hui Guo 0001, Sri Parameswaran, Aleksandar Ignjatovic |
Application specific forwarding network and instruction encoding for multi-pipe ASIPs. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
multi-pipe ASIP, VLIW, forwarding, instruction encoding |
18 | David E. Taylor, Andreas Herkersdorf, Andreas C. Döring, Gero Dittmann |
Robust header compression (ROHC) in next-generation network processors. |
IEEE/ACM Trans. Netw. |
2005 |
DBLP DOI BibTeX RDF |
ROHC, hardware assist, FPGA, ASIC, network processor, ASIP, reconfigurable hardware, header compression |
18 | Partha Biswas, Nikil D. Dutt |
Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
DSP, VLIW, ASIP, Coprocessors, instruction set extensions, code size reduction |
18 | Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang |
Instruction set extension with shadow registers for configurable processors. |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
shadow register, compilation, ASIP, configurable processor |
18 | Peter Yiannacouras, Jonathan Rose, J. Gregory Steffan |
The microarchitecture of FPGA-based soft processors. |
CASES |
2005 |
DBLP DOI BibTeX RDF |
Nios, RTL generation, SPREE, application specic tradeoff, FPGA, pipeline, exploration, embedded processor, ASIP, microarchitecture, soft processor |
18 | Özgün Paker, Jens Sparsø, Niels Haandbæk, Mogens Isager, Lars Skovby Nielsen |
A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing. |
J. VLSI Signal Process. |
2004 |
DBLP DOI BibTeX RDF |
ASIP-application specific instruction set processor, low power, multiprocessor, heterogeneous, scalable architecture, audio signal processing |
18 | Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang |
Application-specific instruction generation for configurable processor architectures. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
binate covering, compilation, ASIP, technology mapping, configurable processor |
18 | Timothy Sherwood, Mark Oskin, Brad Calder |
Balancing design options with Sherpa. |
CASES |
2004 |
DBLP DOI BibTeX RDF |
peicewise linear model, computer architecture, design space exploration, application specific processor (ASIP), area minimization |
18 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt |
Energy-efficient instruction set synthesis for application-specific processors. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
low power, customization, application-specific instruction set processor (ASIP), instruction encoding, energy-delay product |
18 | Dirk Fischer 0001, Jürgen Teich, Michael Thies, Ralph Weper |
Efficient architecture/compiler co-exploration for ASIPs. |
CASES |
2002 |
DBLP DOI BibTeX RDF |
architecture/compiler codesign, multiobjective design space exploration, ASIP, retargetable compilation |
18 | Oliver Schliebusch, Andreas Hoffmann 0002, Achim Nohl, Gunnar Braun, Heinrich Meyr |
Architecture Implementation Using the Machine Description Language LISA. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
Design, Implementation, Synthesis, VHDL, Exploration, SystemC, ASIP, Verilog, LISA |
18 | Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung |
Flexible instruction processors. |
CASES |
2000 |
DBLP DOI BibTeX RDF |
instruction processors, high-level synthesis, ASIP |
18 | Valentina Salapura, Michael Gschwind |
Hardware/Software Co-Design of a Fuzzy RISC Processor. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
hardware/software co-evaluation, processor core, MIPS RISC processor, fuzzy processing, fuzzy rule evaluation, instruction set definition, performance evaluation, VHDL, logic synthesis, application specific instruction set processor (ASIP), hardware/software co-design, instruction set architecture, subword parallelism |
13 | Grant Martin |
Processor Stew (review of Processor Description Languages by P. Mishra and N. Dutt, Eds.; 2008) [Book reviews]. |
IEEE Des. Test Comput. |
2009 |
DBLP DOI BibTeX RDF |
|
13 | Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs). |
SAMOS |
2009 |
DBLP DOI BibTeX RDF |
|
13 | Lars Bauer, Muhammad Shafique 0001, Jörg Henkel |
Efficient Resource Utilization for an Extensible Processor Through Dynamic Instruction Set Adaptation. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
13 | William N. Chelton, Mohammed Benaissa |
Fast Elliptic Curve Cryptography on FPGA. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Muhammad Rashid, Ludovic Apvrille, Renaud Pacalet |
Evaluation of ASIPs Design with LISATek. |
SAMOS |
2008 |
DBLP DOI BibTeX RDF |
LISATek, ASIPs, JPEG, Customized Instructions |
13 | Timo Vogt, Norbert Wehn |
A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Björn Franke |
Fast cycle-approximate instruction set simulation. |
SCOPES |
2008 |
DBLP DOI BibTeX RDF |
|
13 | José Luis Núñez-Yáñez, Eddie Hung, Vassilios A. Chouliaras |
A configurable and programmable motion estimation processor for the H.264 video codec. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Muhammad Rashid, Ludovic Apvrille, Renaud Pacalet |
Application Specific Processors for Multimedia Applications. |
CSE |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Sebastien Fontaine, Sylvain Goyette, J. M. Pierre Langlois, Guy Bois |
Acceleration of a 3D target tracking algorithm using an application specific instruction set processor. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Steve Leibson, Grant Martin |
Design and verification of complex SoC with configurable, extensible processors. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Paolo Bonzini, Dilek Harmanci, Laura Pozzi |
A Study of Energy Saving in Customizable Processors. |
SAMOS |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Anupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
Design space exploration of partially re-configurable embedded processors. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
Rethinking custom ISE identification: a new processor-agnostic method. |
CASES |
2007 |
DBLP DOI BibTeX RDF |
ISE identification, custom processors, maximal cluster |
13 | Peter Hallschmid, Resve A. Saleh |
Automatic Cache Tuning for Energy-Efficiency using Local Regression Modeling. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun |
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. |
J. VLSI Signal Process. |
2006 |
DBLP DOI BibTeX RDF |
C compiler retargeting, embedded processor design, architecture description language, processor model, electronic system level |
13 | Perttu Salmela, Pekka Jääskeläinen, Tuomas Järvinen, Jarmo Takala |
Software Pipelining Support for Transport Triggered Architecture Processors. |
SAMOS |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Shaahin Hessabi, Mehdi Modarressi, Maziar Goudarzi, Hani JavanHemmat |
A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems. |
ICSAMOS |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Swarnalatha Radhakrishnan, Hui Guo 0001, Sri Parameswaran |
Customization of application specific heterogeneous multi-pipeline processors. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
13 | William N. Chelton, Mohammed Benaissa |
High-Speed Pipelined EGG Processor on FPGA. |
SiPS |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Timo Vogt, Norbert Wehn |
A Reconfigurable Applcation Specific Instruction Set Processor for Viterbi and Log-MAP Decoding. |
SiPS |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Kwang Woo Lee, Sung Dae Kim, Myung Hoon Sunwoo |
VSIP : Video Specific Instruction Set Processor for H.264/AVC. |
SiPS |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Tim Good, Mohammed Benaissa |
AES as stream cipher on a small FPGA. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Pablo Ituero, Marisa López-Vallejo |
New Schemes in Clustered VLIW Processors Applied to Turbo Decoding. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Mehdi Modarressi, Shaahin Hessabi, Maziar Goudarzi |
A Reconfigurable Cache Architecture for Object-Oriented Embedded Systems. |
CCECE |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Eugene Hyun, Mihai Sima, Michael McGuire |
Reconfigurable Implementation of Wavelet Transform on an Fpga-Augmented NIOS Processor. |
CCECE |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Mehdi Modarressi, Shaahin Hessabi, Maziar Goudarzi |
A Data Prefetching Mechanism for Object-Oriented Embedded Systems Using Run-Time Profiling. |
DELTA |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Sung Dae Kim, Choong Jin Hyun, Myung Hoon Sunwoo |
VSIP : Implementation of Video Specific Instruction-set Processor. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Hoonmo Yang, Moonkey Lee |
Embedded Processor Validation Environment Using a Cycle-Accurate Retargetable Instruction-Set Simulator. |
J. Supercomput. |
2005 |
DBLP DOI BibTeX RDF |
cycle-accurate, validation, system-on-chip (SoC), architecture description language (ADL), retargetable, instruction-set simulator |
13 | Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan |
Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
performance optimization, power modeling, Motion estimation algorithm |
13 | Wei Qin, Sharad Malik |
A Study of Architecture Description Languages from a Model-based Perspective. |
MTV |
2005 |
DBLP DOI BibTeX RDF |
|
13 | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti |
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
13 | Roshan G. Ragel, Sri Parameswaran, Sayed Mohammad Kia |
Micro embedded monitoring for security in application specific instruction-set processors. |
CASES |
2005 |
DBLP DOI BibTeX RDF |
micro embedded monitoring, microinstructions, self-monitoring instructions, application specific instruction-set processors, security monitoring |
13 | Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr |
Optimization Techniques for ADL-Driven RTL Processor Synthesis. |
IEEE International Workshop on Rapid System Prototyping |
2005 |
DBLP DOI BibTeX RDF |
|
13 | Alberto Ferrante, Giuseppe Piscopo, Stefano Scaldaferri |
Application-Driven Optimization of VLIW Architectures: A Hardware-Software Approach. |
IEEE Real-Time and Embedded Technology and Applications Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
13 | Mohammad Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers |
Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study. |
ASAP |
2005 |
DBLP DOI BibTeX RDF |
|
13 | Aleksandar Beric, Ramanathan Sethuraman, Jef L. van Meerbergen, Gerard de Haan |
Memory-Centric Motion Estimator. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
13 | Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun |
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. |
SAMOS |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Gero Dittmann |
Organizing Libraries of DFG Patterns. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Yuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
Synthesizable HDL generation method for configurable VLIW processors. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Ravi Saini, Pramod Tanwar, A. S. Mandal, S. C. Bose, Raj Singh, Chandra Shekhar 0001 |
Design of an Application Specific Instruction Set Processor for Parametric Speech Synthesis. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl |
Processor/Memory Co-Exploration on Multiple Abstraction Levels. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
13 | Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann 0002, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr |
Instruction encoding synthesis for architecture exploration using hierarchical processor models. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
instruction set architectures, instruction encoding |
13 | Akira Kitajima, Toshiyuki Sasaki, Yoshinori Takeuchi, Masaharu Imai |
Design of Application Specific CISC Using PEAS-III. |
IEEE International Workshop on Rapid System Prototyping |
2002 |
DBLP DOI BibTeX RDF |
|
13 | Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Joon Nam, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Chan-Soo Hwang, Yong Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung |
MetaCore: an application-specific programmable DSP development system. |
IEEE Trans. Very Large Scale Integr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
13 | V. A. Zivkovic, Ronald J. W. T. Tangelder, Hans G. Kerkhoff |
Design and Test Space Exploration of Transport-Triggered Architectures. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
Hierarchical test generation and design for testability methods for ASPPs and ASIPs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
13 | Daniel Benyamin, William H. Mangione-Smith |
Function unit specialization through code analysis. |
ICCAD |
1999 |
DBLP DOI BibTeX RDF |
|
13 | S. Ramanathan, V. Visvanathan, S. K. Nandy 0001 |
Synthesis of Configurable Architectures for DSP Algorithms. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
13 | Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Jun Nam, Jang-Ho Cho, Sung-Won Seo, Chang-Ho Ryu, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Jong-Sun Kim, Hyun-Dhong Yoon, Jae-Yeol Kim, Kun-Moo Lee, Chan-Soo Hwang, In-Hyung Kim, Jun Sung Kim, Kwang-Il Park, Kyu Ho Park, Yong Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung |
MetaCore: An Application Specific DSP Development System. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
high-level synthesis, telecommunication |
13 | Martyn Edwards |
Software acceleration using programmable logic: is it worth the effort? |
CODES |
1997 |
DBLP DOI BibTeX RDF |
software acceleration, performance evaluation, hardware architecture |
13 | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. |
DAC |
1997 |
DBLP DOI BibTeX RDF |
|
13 | Luigi Carro, G. A. Pereira, C. Alba, Altamiro Amadeu Susin |
System Design using ASIPs. |
ECBS |
1996 |
DBLP DOI BibTeX RDF |
|
13 | J. Shu, Thomas Charles Wilson, Dilip K. Banerji |
Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
|
13 | Jie Gong, Daniel D. Gajski, Alexandru Nicolau |
Performance evaluation for application-specific architectures. |
IEEE Trans. Very Large Scale Integr. Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
13 | Pierre G. Paulin, Clifford Liem, Trevor C. May, Shailesh Sutarwala |
DSP design tool requirements for embedded systems: A telecommunications industrial perspective. |
J. VLSI Signal Process. |
1995 |
DBLP DOI BibTeX RDF |
|
13 | Ing-Jer Huang, Alvin M. Despain |
Generating instruction sets and microarchitectures from applications. |
ICCAD |
1994 |
DBLP DOI BibTeX RDF |
|
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