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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 322 occurrences of 165 keywords
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Results
Found 391 publication records. Showing 391 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
18 | Manuel Hohenauer, Felix Engel 0001, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
A SIMD optimization framework for retargetable compilers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 6(1), pp. 2:1-2:27, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
SIMD, vectorization, ASIP, subword parallelism, retargetable compilers |
18 | Teemu Pitkänen, Jarno K. Tanskanen, Risto Mäkinen, Jarmo Takala |
Parallel Memory Architecture for Application-Specific Instruction-Set Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 57(1), pp. 21-32, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
TTA, Transport triggered architecture, Low power, ASIP, Application-specific instruction-set processors, Parallel memory |
18 | Nicolas Beucher, Normand Bélanger, Yvon Savaria, Guy Bois |
High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 56(2-3), pp. 155-165, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
ASIP, Acceleration, Video processing, Data reuse |
18 | Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovic, Qin Zhao, Frank Bouwens, Jos Hulzink, Jef L. van Meerbergen |
Design of 100 µW Wireless Sensor Nodes for Biomedical Monitoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 57(1), pp. 107-119, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Low power, ASIP, ECG, Clock gating, Wireless sensor node |
18 | Mathieu Allard, Patrick Grogan, Jean-Pierre David |
A Scalable Architecture for Multivariate Polynomial Evaluation on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings, pp. 107-112, 2009, IEEE Computer Society, 978-0-7695-3917-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
High performance computing, ASIP, multivariate, Polynomial evaluation |
18 | Ya-Shuai Lü, Li Shen 0007, Zhiying Wang 0003, Nong Xiao |
Dynamically utilizing computation accelerators for extensible processors in a software approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 51-60, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
computation accelerator, ASIP, dynamic binary translation |
18 | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose |
Fine-grain performance scaling of soft vector processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009, pp. 97-106, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
VESPA, soft vector processor, viram, FPGA, custom, SIMD, vector, ASIP, microarchitecture, application specific, soft processor |
18 | Unmesh D. Bordoloi, Huynh Phung Huynh, Samarjit Chakraborty, Tulika Mitra |
Evaluating design trade-offs in customizable processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 244-249, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
multi-objective design space exploration, pareto-optimal curve, processor customization, ASIP |
18 | Jae Hyun Baek, Sung Dae Kim, Myung Hoon Sunwoo |
SPOCS: Application Specific Signal Processor for OFDM Communication Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 53(3), pp. 383-397, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
ASSP, Communications, FFT, DSP, OFDM, Application-Specific Instruction-Set Processor (ASIP), Bit manipulation |
18 | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose |
VESPA: portable, scalable, and flexible FPGA-based vector processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2008 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 61-70, 2008, ACM. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
SPREE, VESPA, VIRAM, FPGA, custom, SIMD, vector, ASIP, microarchitecture, application specific, soft processor |
18 | Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song 0002, Satoshi Goto |
HyMacs: hybrid memory access optimization based on custom-instruction scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 89-94, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
asip, cad algorithm, hardware/software co-design |
18 | Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski |
C-based design flow: a case study on G.729A for voice over internet protocol (VoIP). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 72-75, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
C-based design flow, C-to-RTL, G729A, NISC, HLS, VoIP, ASIP |
18 | Bita Gorjiara, Daniel Gajski |
Automatic architecture refinement techniques for customizing processing elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 379-384, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
GNR, nanocoded architectures, no-instruction-set computer (NISC), refinement, high-level synthesis, power, ASIP, datapath, netlist |
18 | Lars Bauer, Muhammad Shafique 0001, Jörg Henkel |
Run-time instruction set selection in a transmutable embedded processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 56-61, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
extensible embedded processors, special instruction, reconfigurable computing, ASIP, run-time adaptation |
18 | Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar |
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 35(6), pp. 507-527, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Performance evaluation, VLIW, ASIP, Clustered VLIW processors |
18 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt |
Instruction set synthesis with efficient instruction encoding for configurable processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(1), pp. 9:1-9:37, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
ISA customization and specialization, bitwidth-economical, Application-specific instruction set processor (ASIP), configurable processor, instruction encoding |
18 | Anup Gangwar, M. Balakrishnan, Anshul Kumar |
Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(1), pp. 1:1-1:29, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
performance evaluation, VLIW, ASIP, clustered VLIW processors |
18 | Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
A low power VLIW processor generation method by means of extracting non-redundant activation conditions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 227-232, 2007, ACM, 978-1-59593-824-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
low power, ASIP, clock gating, VLIW processor |
18 | Hanno Scharwächter, Jonghee M. Youn, Rainer Leupers, Yunheung Paek, Gerd Ascheid, Heinrich Meyr |
A code-generator generator for multi-output instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 131-136, 2007, ACM, 978-1-59593-824-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
ISS, code-selection, compiler/architecture co-design, ASIP |
18 | I-Wei Wu, Shih-Chia Huang, Chung-Ping Chung, Jean Jyh-Jiun Shann |
Instruction Set Extension Generation with Considering Physical Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings, pp. 291-305, 2007, Springer, 978-3-540-69337-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Pipestage Timing Constraint, ASIP, Instruction set extension, Extensible Processors |
18 | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose |
Application-specific customization of soft processor microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 201-210, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Nios, RTL generation, SPREE, FPGA, customization, embedded processor, ASIP, microarchitecture, application specific, soft processor |
18 | Swarnalatha Radhakrishnan, Hui Guo 0001, Sri Parameswaran, Aleksandar Ignjatovic |
Application specific forwarding network and instruction encoding for multi-pipe ASIPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 241-246, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
multi-pipe ASIP, VLIW, forwarding, instruction encoding |
18 | David E. Taylor, Andreas Herkersdorf, Andreas C. Döring, Gero Dittmann |
Robust header compression (ROHC) in next-generation network processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 13(4), pp. 755-768, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
ROHC, hardware assist, FPGA, ASIC, network processor, ASIP, reconfigurable hardware, header compression |
18 | Partha Biswas, Nikil D. Dutt |
Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(10), pp. 1216-1226, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
DSP, VLIW, ASIP, Coprocessors, instruction set extensions, code size reduction |
18 | Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang |
Instruction set extension with shadow registers for configurable processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 99-106, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
shadow register, compilation, ASIP, configurable processor |
18 | Peter Yiannacouras, Jonathan Rose, J. Gregory Steffan |
The microarchitecture of FPGA-based soft processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005, pp. 202-212, 2005, ACM, 1-59593-149-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Nios, RTL generation, SPREE, application specic tradeoff, FPGA, pipeline, exploration, embedded processor, ASIP, microarchitecture, soft processor |
18 | Özgün Paker, Jens Sparsø, Niels Haandbæk, Mogens Isager, Lars Skovby Nielsen |
A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 37(1), pp. 95-110, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ASIP-application specific instruction set processor, low power, multiprocessor, heterogeneous, scalable architecture, audio signal processing |
18 | Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang |
Application-specific instruction generation for configurable processor architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 183-189, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
binate covering, compilation, ASIP, technology mapping, configurable processor |
18 | Timothy Sherwood, Mark Oskin, Brad Calder |
Balancing design options with Sherpa. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2004, Washington DC, USA, September 22 - 25, 2004, pp. 57-68, 2004, ACM, 1-58113-890-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
peicewise linear model, computer architecture, design space exploration, application specific processor (ASIP), area minimization |
18 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt |
Energy-efficient instruction set synthesis for application-specific processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 330-333, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
low power, customization, application-specific instruction set processor (ASIP), instruction encoding, energy-delay product |
18 | Dirk Fischer 0001, Jürgen Teich, Michael Thies, Ralph Weper |
Efficient architecture/compiler co-exploration for ASIPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 27-34, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
architecture/compiler codesign, multiobjective design space exploration, ASIP, retargetable compilation |
18 | Oliver Schliebusch, Andreas Hoffmann 0002, Achim Nohl, Gunnar Braun, Heinrich Meyr |
Architecture Implementation Using the Machine Description Language LISA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 239-244, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Design, Implementation, Synthesis, VHDL, Exploration, SystemC, ASIP, Verilog, LISA |
18 | Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung |
Flexible instruction processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2000 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2000, San Jose, California, USA, November 7-18, 2000, pp. 193-200, 2000, ACM, 1-58113-338-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
instruction processors, high-level synthesis, ASIP |
18 | Valentina Salapura, Michael Gschwind |
Hardware/Software Co-Design of a Fuzzy RISC Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 875-882, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
hardware/software co-evaluation, processor core, MIPS RISC processor, fuzzy processing, fuzzy rule evaluation, instruction set definition, performance evaluation, VHDL, logic synthesis, application specific instruction set processor (ASIP), hardware/software co-design, instruction set architecture, subword parallelism |
13 | Grant Martin |
Processor Stew (review of Processor Description Languages by P. Mishra and N. Dutt, Eds.; 2008) [Book reviews]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 26(2), pp. 76-77, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
13 | Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 204-214, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
13 | Lars Bauer, Muhammad Shafique 0001, Jörg Henkel |
Efficient Resource Utilization for an Extensible Processor Through Dynamic Instruction Set Adaptation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(10), pp. 1295-1308, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | William N. Chelton, Mohammed Benaissa |
Fast Elliptic Curve Cryptography on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(2), pp. 198-205, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Muhammad Rashid, Ludovic Apvrille, Renaud Pacalet |
Evaluation of ASIPs Design with LISATek. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008. Proceedings, pp. 177-186, 2008, Springer, 978-3-540-70549-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
LISATek, ASIPs, JPEG, Customized Instructions |
13 | Timo Vogt, Norbert Wehn |
A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 38-43, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Björn Franke |
Fast cycle-approximate instruction set simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCOPES ![In: Proceedings of the 11th International Workshop on Software and Compilers for Embedded Systems, Munich, Germany, March 13-14, 2008, pp. 69-78, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | José Luis Núñez-Yáñez, Eddie Hung, Vassilios A. Chouliaras |
A configurable and programmable motion estimation processor for the H.264 video codec. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 149-154, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Muhammad Rashid, Ludovic Apvrille, Renaud Pacalet |
Application Specific Processors for Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSE ![In: Proceedings of the 11th IEEE International Conference on Computational Science and Engineering, CSE 2008, São Paulo, SP, Brazil, July 16-18, 2008, pp. 109-116, 2008, IEEE Computer Society, 978-0-7695-3193-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Sebastien Fontaine, Sylvain Goyette, J. M. Pierre Langlois, Guy Bois |
Acceleration of a 3D target tracking algorithm using an application specific instruction set processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 255-259, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Steve Leibson, Grant Martin |
Design and verification of complex SoC with configurable, extensible processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 385, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Paolo Bonzini, Dilek Harmanci, Laura Pozzi |
A Study of Energy Saving in Customizable Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings, pp. 304-312, 2007, Springer, 978-3-540-73622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Anupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
Design space exploration of partially re-configurable embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 319-324, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
Rethinking custom ISE identification: a new processor-agnostic method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 125-134, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
ISE identification, custom processors, maximal cluster |
13 | Peter Hallschmid, Resve A. Saleh |
Automatic Cache Tuning for Energy-Efficiency using Local Regression Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 732-737, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun |
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 43(2-3), pp. 235-246, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
C compiler retargeting, embedded processor design, architecture description language, processor model, electronic system level |
13 | Perttu Salmela, Pekka Jääskeläinen, Tuomas Järvinen, Jarmo Takala |
Software Pipelining Support for Transport Triggered Architecture Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings, pp. 237-247, 2006, Springer, 3-540-36410-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Shaahin Hessabi, Mehdi Modarressi, Maziar Goudarzi, Hani JavanHemmat |
A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2006), Samos, Greece, July 17-20, 2006, pp. 7-13, 2006, IEEE, 1-4244-0155-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Swarnalatha Radhakrishnan, Hui Guo 0001, Sri Parameswaran |
Customization of application specific heterogeneous multi-pipeline processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 746-751, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | William N. Chelton, Mohammed Benaissa |
High-Speed Pipelined EGG Processor on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada, pp. 136-141, 2006, IEEE, 1-4244-0382-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Timo Vogt, Norbert Wehn |
A Reconfigurable Applcation Specific Instruction Set Processor for Viterbi and Log-MAP Decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada, pp. 142-147, 2006, IEEE, 1-4244-0382-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Kwang Woo Lee, Sung Dae Kim, Myung Hoon Sunwoo |
VSIP : Video Specific Instruction Set Processor for H.264/AVC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada, pp. 124-129, 2006, IEEE, 1-4244-0382-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Tim Good, Mohammed Benaissa |
AES as stream cipher on a small FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Pablo Ituero, Marisa López-Vallejo |
New Schemes in Clustered VLIW Processors Applied to Turbo Decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 2006 IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP 2006), 11-13 September 2006, Steamboat Springs, Colorado, USA, pp. 291-296, 2006, IEEE Computer Society, 0-7695-2682-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Mehdi Modarressi, Shaahin Hessabi, Maziar Goudarzi |
A Reconfigurable Cache Architecture for Object-Oriented Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 959-962, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Eugene Hyun, Mihai Sima, Michael McGuire |
Reconfigurable Implementation of Wavelet Transform on an Fpga-Augmented NIOS Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 1052-1055, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Mehdi Modarressi, Shaahin Hessabi, Maziar Goudarzi |
A Data Prefetching Mechanism for Object-Oriented Embedded Systems Using Run-Time Profiling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 249-254, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Sung Dae Kim, Choong Jin Hyun, Myung Hoon Sunwoo |
VSIP : Implementation of Video Specific Instruction-set Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1075-1078, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Hoonmo Yang, Moonkey Lee |
Embedded Processor Validation Environment Using a Cycle-Accurate Retargetable Instruction-Set Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 33(1-2), pp. 19-32, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
cycle-accurate, validation, system-on-chip (SoC), architecture description language (ADL), retargetable, instruction-set simulator |
13 | Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan |
Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(6), pp. 714-726, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
performance optimization, power modeling, Motion estimation algorithm |
13 | Wei Qin, Sharad Malik |
A Study of Architecture Description Languages from a Model-based Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA, pp. 3-11, 2005, IEEE Computer Society, 0-7695-2627-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
13 | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti |
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 940-943, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
13 | Roshan G. Ragel, Sri Parameswaran, Sayed Mohammad Kia |
Micro embedded monitoring for security in application specific instruction-set processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005, pp. 304-314, 2005, ACM, 1-59593-149-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
micro embedded monitoring, microinstructions, self-monitoring instructions, application specific instruction-set processors, security monitoring |
13 | Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr |
Optimization Techniques for ADL-Driven RTL Processor Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 8-10 June 2005, Montreal, Canada, pp. 165-171, 2005, IEEE Computer Society, 0-7695-2361-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
13 | Alberto Ferrante, Giuseppe Piscopo, Stefano Scaldaferri |
Application-Driven Optimization of VLIW Architectures: A Hardware-Software Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real-Time and Embedded Technology and Applications Symposium ![In: 11th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2005), 7-10 March 2005, San Francisco, CA, USA, pp. 128-137, 2005, IEEE Computer Society, 0-7695-2302-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
13 | Mohammad Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers |
Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece, pp. 154-160, 2005, IEEE Computer Society, 0-7695-2407-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
13 | Aleksandar Beric, Ramanathan Sethuraman, Jef L. van Meerbergen, Gerard de Haan |
Memory-Centric Motion Estimator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 816-819, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
13 | Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun |
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings, pp. 463-473, 2004, Springer, 3-540-22377-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Gero Dittmann |
Organizing Libraries of DFG Patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 726-727, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Yuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
Synthesizable HDL generation method for configurable VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 842-845, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Ravi Saini, Pramod Tanwar, A. S. Mandal, S. C. Bose, Raj Singh, Chandra Shekhar 0001 |
Design of an Application Specific Instruction Set Processor for Parametric Speech Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 773-775, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl |
Processor/Memory Co-Exploration on Multiple Abstraction Levels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10966-10973, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
13 | Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann 0002, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr |
Instruction encoding synthesis for architecture exploration using hierarchical processor models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 262-267, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
instruction set architectures, instruction encoding |
13 | Akira Kitajima, Toshiyuki Sasaki, Yoshinori Takeuchi, Masaharu Imai |
Design of Application Specific CISC Using PEAS-III. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 1-3 July 2002, Darmstadt, Germany, pp. 12-17, 2002, IEEE Computer Society, 0-7695-1703-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
13 | Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Joon Nam, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Chan-Soo Hwang, Yong Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung |
MetaCore: an application-specific programmable DSP development system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(2), pp. 173-183, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | V. A. Zivkovic, Ronald J. W. T. Tangelder, Hans G. Kerkhoff |
Design and Test Space Exploration of Transport-Triggered Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 146-151, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
Hierarchical test generation and design for testability methods for ASPPs and ASIPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(3), pp. 357-370, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
13 | Daniel Benyamin, William H. Mangione-Smith |
Function unit specialization through code analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 257-260, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
13 | S. Ramanathan, V. Visvanathan, S. K. Nandy 0001 |
Synthesis of Configurable Architectures for DSP Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 350-357, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
13 | Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Jun Nam, Jang-Ho Cho, Sung-Won Seo, Chang-Ho Ryu, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Jong-Sun Kim, Hyun-Dhong Yoon, Jae-Yeol Kim, Kun-Moo Lee, Chan-Soo Hwang, In-Hyung Kim, Jun Sung Kim, Kwang-Il Park, Kyu Ho Park, Yong Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung |
MetaCore: An Application Specific DSP Development System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 800-803, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
high-level synthesis, telecommunication |
13 | Martyn Edwards |
Software acceleration using programmable logic: is it worth the effort? ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Fifth International Workshop on Hardware/Software Codesign, CODES/CASHE 1997, March 24-26, 1997, Braunschweig, Germany, pp. 135-139, 1997, IEEE Computer Society, 0-8186-7895-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
software acceleration, performance evaluation, hardware architecture |
13 | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 534-539, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
13 | Luigi Carro, G. A. Pereira, C. Alba, Altamiro Amadeu Susin |
System Design using ASIPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: IEEE Symposium and Workshop on Engineering of Computer Based Systems (ECBS'96), March 11-15, 1996, Friedrichshafen, Germany., pp. 80-85, 1996, IEEE Computer Society, 0-8186-7355-9. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
13 | J. Shu, Thomas Charles Wilson, Dilip K. Banerji |
Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 73-76, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
13 | Jie Gong, Daniel D. Gajski, Alexandru Nicolau |
Performance evaluation for application-specific architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(4), pp. 483-490, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
13 | Pierre G. Paulin, Clifford Liem, Trevor C. May, Shailesh Sutarwala |
DSP design tool requirements for embedded systems: A telecommunications industrial perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 9(1-2), pp. 23-47, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
13 | Ing-Jer Huang, Alvin M. Despain |
Generating instruction sets and microarchitectures from applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 391-396, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
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