Search results for "Caches"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
20	Lars Bækgaard, Leo Mark	Incremental Computation of Nested Relational Query Expressions.	ACM Trans. Database Syst.	1995	DBLP DOI BibTeX RDF	nested query expressions, unnesting, view pointer caches, incremental computation, set differences
20	Shannon V. Morton, Sam S. Appleton, Michael J. Liebelt	ECSTAC: a fast asynchronous microprocessor.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous microprocessor, ECSTAC, two-phase communication, processor pipeline, register tagging, branch techniques, block simulation, caches, logic design, asynchronous circuits, microprocessor chips
20	Theodore Johnson	A performance comparison of fast distributed mutual exclusion algorithms.	IPPS	1995	DBLP DOI BibTeX RDF	O(log n) messages, distributed virtual memory, computational complexity, distributed algorithms, distributed algorithms, software performance evaluation, performance comparison, distributed object systems, distributed synchronization, mutual exclusion algorithms, coherent caches
20	John G. Cleary, Murray Pearson, Husam Kinawi	The architecture of an optimistic CPU: the WarpEngine.	HICSS (1)	1995	DBLP DOI BibTeX RDF	optimistic CPU, WarpEngine, shared memory CPU, single instructions, memory latency tolerance, executable instructions, TimeWarp algorithm, optimistic, single linear address space, single thread of control, reliability, caches, parallel architectures, fault tolerant computing, concurrency control, synchronisation, synchronisation, shared memory systems, memory architecture, cache storage, memory system, memory model, time stamped, memory accesses, local memory
20	David J. Lilja	The Impact of Parallel Loop Scheduling Strategies on Prefetching in a Shared Memory Multiprocessor.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	parallel loop scheduling, numerical Fortran programs, single-word cache blocks, guidedself-scheduling, scheduling, parallel programming, prefetching, shared memory multiprocessor, shared memory systems, cache coherence, trace-driven simulations, buffer storage, data caches, memory performance, false sharing, performanceevaluation, cache pollution
20	Michel Dubois 0001, Christoph Scheurich	Memory Access Dependencies in Shared-Memory Multiprocessors.	IEEE Trans. Software Eng.	1990	DBLP DOI BibTeX RDF	memory access dependencies, logical concurrency model, pipelining, multiprocessing systems, rules, shared-memory multiprocessors, multiprogramming, storage allocation, multiprocessor architectures, private caches
20	Jean-Loup Baer, Yi-Bing Lin	Improving Quicksort Performance with a Codewort Data Structure.	IEEE Trans. Software Eng.	1989	DBLP DOI BibTeX RDF	codeword data structure, long, alphanumeric sequences, bytes, codeword generator, character count, first nonequal byte, quicksort algorithm, architecture-dependent parameters, in-line expansion, data structures, caches, sorting, compiler optimizations, register allocation, performance improvement, ordering, pointer, records, keys, swaps, write policies
19	Mirza Omer Beg, Peter van Beek	A graph theoretic approach to cache-conscious placement of data for direct mapped caches.	ISMM	2010	DBLP DOI BibTeX RDF	cache consciousness, data placement in cache, offline algorithms, memory management, cache optimization
19	Gabriel H. Loh	Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy.	MICRO	2009	DBLP DOI BibTeX RDF
19	Mainak Chaudhuri	PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches.	HPCA	2009	DBLP DOI BibTeX RDF
19	Martin Schoeberl, Wolfgang Puffitsch, Benedikt Huber	Towards Time-Predictable Data Caches for Chip-Multiprocessors.	SEUS	2009	DBLP DOI BibTeX RDF
19	Chuanjun Zhang, Bing Xue	Divide-and-conquer: a bubble replacement for low level caches.	ICS	2009	DBLP DOI BibTeX RDF	high-performance computing, divide-and-conquer, cache replacement policy
19	Jie Tao 0001, Dominic Hillenbrand, Holger Marten	Instruction Hints for Super Efficient Data Caches.	ICCS (2)	2009	DBLP DOI BibTeX RDF	simulation, architecture design, Cache optimization
19	Jiang Lin, Qingda Lu, Xiaoning Ding, Zhao Zhang 0010, Xiaodong Zhang 0001, P. Sadayappan	Enabling software management for multicore caches with a lightweight hardware support.	SC	2009	DBLP DOI BibTeX RDF	multicore, shared cache, cache management
19	Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem	ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors.	HiPEAC	2009	DBLP DOI BibTeX RDF
19	Nikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki	Reactive NUCA: near-optimal block placement and replication in distributed caches.	ISCA	2009	DBLP DOI BibTeX RDF	block migration, block placement, block replication, cache indexing, cache lookup, non-uniform cache access, nuca, r-nuca, reactive nuca, rotational interleaving, cache, replication, chip multiprocessor, cmp, placement, multicore, multi-core, migration, cache coherence, data replication, coherence, interleaving, data migration, data placement, shared cache, cache management, lookup, last-level cache, private cache
19	Yan Pan, Joonho Kong, Serkan Ozdemir, Gokhan Memik, Sung Woo Chung	Selective wordline voltage boosting for caches to manage yield under process variations.	DAC	2009	DBLP DOI BibTeX RDF	access time failure, selective wordline voltage boosting, cache, process variations, yield
19	Xiaogang Qiu, Michel Dubois 0001	The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
19	Yun Liang 0001, Tulika Mitra	Static analysis for fast and accurate design space exploration of caches.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	probabilistic cache states, cache, design space exploration
19	Kyoungwoo Lee, Aviral Shrivastava, Nikil D. Dutt, Nalini Venkatasubramanian	Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures.	DIPES	2008	DBLP DOI BibTeX RDF
19	Ozcan Ozturk 0001, Seung Woo Son 0001, Mahmut T. Kandemir, Mustafa Karaköy	Prefetch throttling and data pinning for improving performance of shared caches.	SC	2008	DBLP DOI BibTeX RDF
19	Eui-Young Chung, Cheol Hong Kim, Sung Woo Chung	An Accurate and Energy-Efficient Way Determination Technique for Instruction Caches by Early Tab Matching.	DELTA	2008	DBLP DOI BibTeX RDF	way predictioin, low power, Instruction cache
19	Shekhar Srikantaiah, Mahmut T. Kandemir, Mary Jane Irwin	Adaptive set pinning: managing shared caches in chip multiprocessors.	ASPLOS	2008	DBLP DOI BibTeX RDF	inter-processor, intra-processor, set pinning, CMP, shared cache
19	Afrin Naz, Krishna M. Kavi, Jung-Hwan Oh 0001, Pierfrancesco Foglia	Reconfigurable split data caches: a novel scheme for embedded systems.	SAC	2007	DBLP DOI BibTeX RDF	split cache, embedded systems, cache, locality, reconfigurability
19	Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai	Utilization of SECDED for soft error and variation-induced defect tolerance in caches.	DATE	2007	DBLP DOI BibTeX RDF
19	Isabelle Puaut, Christophe Pais	Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison.	DATE	2007	DBLP DOI BibTeX RDF
19	Rathijit Sen, Y. N. Srikant	WCET estimation for executables in the presence of data caches.	EMSOFT	2007	DBLP DOI BibTeX RDF
19	Sangyeun Cho, Lei Jin 0002, Kiyeon Lee	Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems.	RTCSA	2007	DBLP DOI BibTeX RDF
19	Jugash Chandarlapati, Mainak Chaudhuri	LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation.	ICCD	2007	DBLP DOI BibTeX RDF
19	Ricardo A. Baeza-Yates, Flavio Junqueira, Vassilis Plachouras, Hans Friedrich Witschel	Admission Policies for Caches of Search Engine Results.	SPIRE	2007	DBLP DOI BibTeX RDF
19	Apala Guha, Kim M. Hazelwood, Mary Lou Soffa	Reducing Exit Stub Memory Consumption in Code Caches.	HiPEAC	2007	DBLP DOI BibTeX RDF
19	Georgios Keramidas, Polychronis Xekalakis, Stefanos Kaxiras	Applying Decay to Reduce Dynamic Power in Set-Associative Caches.	HiPEAC	2007	DBLP DOI BibTeX RDF
19	Naveen Muralimanohar, Rajeev Balasubramonian	Interconnect design considerations for large NUCA caches.	ISCA	2007	DBLP DOI BibTeX RDF	non-uniform cache architecture, network-on-chip, interconnect, memory hierarchies, cache models
19	Ewa Kusmierek, Yingfei Dong, David Hung-Chang Du	Loopback: exploiting collaborative caches for large-scale streaming.	IEEE Trans. Multim.	2006	DBLP DOI BibTeX RDF
19	Georgios Keramidas, Pavlos Petoumenos, Stefanos Kaxiras, Alexandros Antonopoulos, Dimitrios N. Serpanos	Preventing Denial-of-Service Attacks in Shared CMP Caches.	SAMOS	2006	DBLP DOI BibTeX RDF
19	Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Jos T. J. van Eijndhoven	Compositional, efficient caches for a chip multi-processor.	DATE	2006	DBLP DOI BibTeX RDF
19	Seetharami R. Seelam, Jayaraman Suresh Babu, Patricia J. Teller	Rate-Controlled Scheduling of Expired Writes for Volatile Caches.	QEST	2006	DBLP DOI BibTeX RDF
19	Arul Sandeep Gade, Yul Chu	A Case for Dual-Mapping One-Way Caches.	ARCS	2006	DBLP DOI BibTeX RDF
19	Anup Mayank, Chinya V. Ravishankar, Krishna Bandaru, Trivikram Phatak	Decentralized Hash-Based Coordination of Distributed Multimedia Caches.	ICN/ICONS/MCL	2006	DBLP DOI BibTeX RDF
19	Abel Guilhermino Silva-Filho, Pablo Viana, Edna Barros, Manoel Eusébio de Lima	Tuning Mechanism for Two-Level Cache Hierarchy Intended for Instruction Caches and Low Energy Consumption.	SBAC-PAD	2006	DBLP DOI BibTeX RDF
19	Hiroaki Kobayashi, Isao Kotera, Hiroyuki Takizawa	Locality analysis to control dynamically way-adaptable caches.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
19	Yan Meng, Timothy Sherwood, Ryan Kastner	Exploring the limits of leakage power reduction in caches.	ACM Trans. Archit. Code Optim.	2005	DBLP DOI BibTeX RDF	cache intervals, leakage power, Limits
19	Tohru Ishihara, Farzan Fallah	A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors.	DATE	2005	DBLP DOI BibTeX RDF
19	Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge	Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage.	DATE	2005	DBLP DOI BibTeX RDF
19	Derek Bruening, Saman P. Amarasinghe	Maintaining Consistency and Bounding Capacity of Software Code Caches.	CGO	2005	DBLP DOI BibTeX RDF
19	Yan Meng, Timothy Sherwood, Ryan Kastner	On the Limits of Leakage Power Reduction in Caches.	HPCA	2005	DBLP DOI BibTeX RDF
19	Saibhushan Musalappa, Shivakumar Sundaram, Yul Chu	Energy savings for data caches: ELRU-SEQ replacement policy.	IPCCC	2005	DBLP DOI BibTeX RDF
19	Lingling Jin, Wei Wu 0024, Jun Yang 0002, Chuanjun Zhang, Youtao Zhang	Dynamic Co-allocation of Level One Caches.	ICESS	2005	DBLP DOI BibTeX RDF
19	Antonio Martí Campoy, Eugenio Tamura, Sergio Sáez, Francisco Rodríguez 0003, José V. Busquets-Mataix	On Using Locking Caches in Embedded Real-Time Systems.	ICESS	2005	DBLP DOI BibTeX RDF	genetic algorithms, performance evaluation, predictability, response time, Cache memories, schedulability analysis, execution time, embedded real-time systems
19	Emre Özer 0001, Resit Sendag, David Gregg	Multiple-Valued Caches for Power-Efficient Embedded Systems.	ISMVL	2005	DBLP DOI BibTeX RDF
19	Nasir Mohyuddin, Rashed Zafar Bhatti, Michel Dubois 0001	Controlling leakage power with the replacement policy in slumberous caches.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	tranquility level, leakage power, replacement policy, drowsy cache
19	Johnsy K. John, Jie S. Hu, Sotirios G. Ziavras	Optimizing the Thermal Behavior of Subarrayed Data Caches.	ICCD	2005	DBLP DOI BibTeX RDF
19	Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt	A first look at the interplay of code reordering and configurable caches.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	cache exploration, code reorganization, low power, low energy, cache optimization, architecture tuning, cache hierarchy, configurable cache, code layout, code reordering
19	Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería	Store Buffer Design in First-Level Multibanked Data Caches.	ISCA	2005	DBLP DOI BibTeX RDF
19	Xiaoqin Ma, Gene Cooperman	Fast Query Processing by Distributing an Index over CPU Caches.	CLUSTER	2005	DBLP DOI BibTeX RDF
19	Akihito Sakanaka, Seiichirou Fujii, Toshinori Sato	A leakage-energy-reduction technique for highly-associative caches in embedded systems.	SIGARCH Comput. Archit. News	2004	DBLP DOI BibTeX RDF	cache memories, embedded processors, leakage current
19	Mark Brehob, Stephen Wagner, Eric Torng, Richard J. Enbody	Optimal Replacement Is NP-Hard for Nonstandard Caches.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	optimal cache replacement policy, interval scheduling, skew cache, multilateral cache, approximation algorithm, Cache, victim cache
19	Juan L. Aragón, Dan Nicolaescu, Alexander V. Veidenbaum, Ana-Maria Badulescu	Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors.	DATE	2004	DBLP DOI BibTeX RDF
19	Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt	Automatic Tuning of Two-Level Caches to Embedded Applications.	DATE	2004	DBLP DOI BibTeX RDF	cache exploration, embedded systems, low power, low energy, cache optimization, architecture tuning, cache hierarchy, Configurable cache
19	Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería	Contents Management in First-Level Multibanked Data Caches.	Euro-Par	2004	DBLP DOI BibTeX RDF
19	Masamichi Takagi, Kei Hiraki	Inter-reference gap distribution replacement: an improved replacement algorithm for set-associative caches.	ICS	2004	DBLP DOI BibTeX RDF	cache memory, replacement algorithm, set-associative cache
19	Arindam Mallik, Matthew C. Wildrick, Gokhan Memik	Design and implementation of correlating caches.	ISLPED	2004	DBLP DOI BibTeX RDF
19	Seiichiro Fujii, Toshinori Sato	Non-uniform Set-Associative Caches for Power-Aware Embedded Processors.	EUC	2004	DBLP DOI BibTeX RDF
19	John Y. Fong, Randy Acklin, John Roscher, Feng Li, Cindy Laird, Cezary Pietrzyk	Nonvolatile Repair Caches Repair Embedded SRAM and New Nonvolatile Memories.	DFT	2004	DBLP DOI BibTeX RDF
19	Changkyu Kim, Doug Burger, Stephen W. Keckler	Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches.	IEEE Micro	2003	DBLP DOI BibTeX RDF
19	Praveen Kalla, Xiaobo Sharon Hu, Jörg Henkel	LRU-SEQ: A Novel Replacement Policy for Transition Energy Reduction in Instruction Caches.	ICCAD	2003	DBLP DOI BibTeX RDF
19	Zhigang Hu, Stefanos Kaxiras, Margaret Martonosi	Let caches decay: reducing leakage energy via exploitation of cache generational behavior.	ACM Trans. Comput. Syst.	2002	DBLP DOI BibTeX RDF	generational behavior, Cache memories, leakage power, cache decay
19	Jussi Kangasharju, Felix Hartanto, Martin Reisslein, Keith W. Ross	Distributing Layered Encoded Video through Caches.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	streaming layered video, utility heuristics, stochastic knapsack, Proxy caching
19	Naila Rahman	Algorithms for Hardware Caches and TLB.	Algorithms for Memory Hierarchies	2002	DBLP DOI BibTeX RDF
19	Abdolreza Abhari, Sivarama P. Dandamudi, Shikharesh Majumdar	Exploiting Web Document Structure to Improve Storage Management in Proxy Caches.	HiPC	2002	DBLP DOI BibTeX RDF
19	Hans Vandierendonck, Alex Ramírez, Koenraad De Bosschere, Mateo Valero	A Comparative Study of Redundancy in Trace Caches (Research Note).	Euro-Par	2002	DBLP DOI BibTeX RDF
19	Susan Cotterell, Frank Vahid	Synthesis of customized loop caches for core-based embedded systems.	ICCAD	2002	DBLP DOI BibTeX RDF	customized architectures, embedded systems, low power, synthesis, estimation, memory hierarchy, low energy, tuning, instruction fetching, architecture tuning, loop cache
19	Dana S. Henry, Gabriel H. Loh, Rahul Sami	Speculative Clustered Caches for Clustered Processors.	ISHPC	2002	DBLP DOI BibTeX RDF
19	Fabian Wolf, Jan Staschulat, Rolf Ernst	Associative caches in formal software timing analysis.	DAC	2002	DBLP DOI BibTeX RDF	real-time, timing analysis, embedded software, cache analysis
19	Goetz Graefe, Per-Åke Larson	B-Tree Indexes and CPU Caches.	ICDE	2001	DBLP DOI BibTeX RDF
19	Lars Arge, Jeffrey S. Chase, Jeffrey Scott Vitter, Rajiv Wickremesinghe	Efficient Sorting Using Registers and Caches.	WAE	2000	DBLP DOI BibTeX RDF
19	Seon Wook Kim, Rudolf Eigenmann	Compiler Techniques for Energy Saving in Instruction Caches of Speculative Parallel Microarchitectures.	ICPP	2000	DBLP DOI BibTeX RDF	speculative microarchitecture, compiler, branch prediction, energy saving, instruction cache
19	Peter Sanders 0001	Accessing Multiple Sequences Through Set Associative Caches.	ICALP	1999	DBLP DOI BibTeX RDF	multi merge, memory hierarchy, external memory algorithm, Set associative cache
19	Toni Cortes, Jesús Labarta	Linear Aggressive Prefetching: A Way to Increase the Performance of Cooperative Caches.	IPPS/SPDP	1999	DBLP DOI BibTeX RDF
19	Tor E. Jeremiassen	A DSP with Caches-A Study of the GSM-EFR Codec on the TI C6211.	ICCD	1999	DBLP DOI BibTeX RDF	GSM-EFR Speech Codec, Performance, Cache, DSP
19	Tom Thomas, Brian W. Anthony	Area, Performance, and Yield Implications of Redundancy in On-Chip Caches.	ICCD	1999	DBLP DOI BibTeX RDF	cache, redundancy, microprocessor, yield, SRAM, yield enhancement, microprocessor design, embedded SRAM
19	Elizabeth A. M. Shriver, Arif Merchant, John Wilkes	An Analytic Behavior Model for Disk Drives with Readahead Caches and Request Reordering.	SIGMETRICS	1998	DBLP DOI BibTeX RDF
19	Rajesh Raina, Robert F. Molyneaux	Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	High-Level Design Validation, Silicon Validation, Pseudo-Random Testing, Microprocessor Testing
19	Sanjeev Kumar, Christopher B. Wilkerson	Exploiting Spatial Locality in Data Caches Using Spatial Footprints.	ISCA	1998	DBLP DOI BibTeX RDF
19	Somnath Ghosh, Margaret Martonosi, Sharad Malik	Precise Miss Analysis for Program Transformations with Caches of Arbitrary Associativity.	ASPLOS	1998	DBLP DOI BibTeX RDF
19	Edward D. Moreno, Sergio Takeo Kofuji	Efficiency of remote access caches in future SMP-based CC-NUMA multiprocessors: initial results.	ISPAN	1997	DBLP DOI BibTeX RDF	shared remote access cache, future SMP based CC-NUMA multiprocessors, symmetric multiprocessor nodes, future architectures, realistic hardware parameters, state of the art systems components, SPLASH-2 benchmark suite, performance application, baseline architecture, approach-1, slow network, approach-2, fast network, 32-processor system, four-processor SMP nodes, two-processor SMP nodes, multiprocessing systems, execution time, cost effectiveness
19	Kenneth M. Wilson, Kunle Olukotun	Designing High Bandwidth On-Chip Caches.	ISCA	1997	DBLP DOI BibTeX RDF
19	Marc Abrams, Charles R. Standridge, Ghaleb Abdulla, Edward A. Fox, Stephen M. Williams	Removal Policies in Network Caches for World-Wide Web Documents.	SIGCOMM	1996	DBLP DOI BibTeX RDF	Internet, World Wide Web (WWW)
19	Richard E. Kessler, Mark D. Hill	Page Placement Algorithms for Large Real-Indexed Caches.	ACM Trans. Comput. Syst.	1992	DBLP DOI BibTeX RDF
19	Michel Dubois 0001, Luiz André Barroso, Yung-Syau Chen, Koray Öner	Scalability Problems in Multiprocessors with Private Caches.	PARLE	1992	DBLP DOI BibTeX RDF
19	Jon A. Solworth, Cyril U. Orji	Write-Only Disk Caches.	SIGMOD Conference	1990	DBLP DOI BibTeX RDF
19	Andrew Braunstein, Mark Riley, John Wilkes	Improving the Efficiency of UNIX File Buffer Caches.	SOSP	1989	DBLP DOI BibTeX RDF	UNIX
19	Scott McFarling	Program Optimization for Instruction Caches.	ASPLOS	1989	DBLP DOI BibTeX RDF	RISC
18	Shrikanth Ganapathy, Ramon Canal, Antonio González 0001, Antonio Rubio 0001	MODEST: a model for energy estimation under spatio-temporal variability.	ISLPED	2010	DBLP DOI BibTeX RDF	dsm scaling, spatio-temporal variability, cache design
18	Pejman Lotfi-Kamran, Michael Ferdman, Daniel Crisan, Babak Falsafi	TurboTag: lookup filtering to reduce coherence directory power.	ISLPED	2010	DBLP DOI BibTeX RDF	bloom, low power, filter, coherence, directory
18	Li Zhao 0002, Ravi R. Iyer 0001, Srihari Makineni, Don Newell, Liqun Cheng	NCID: a non-inclusive cache, inclusive directory architecture for flexible and efficient cache hierarchies.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	cache, directory
18	Mohamed M. Sabry, Martino Ruggiero, Pablo García Del Valle	Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	multi-core, virtual platform, L2 cache
18	Guy E. Blelloch, Phillip B. Gibbons, Harsha Vardhan Simhadri	Low depth cache-oblivious algorithms.	SPAA	2010	DBLP DOI BibTeX RDF	sparse-matrix vector multiply, schedulers, parallel algorithms, multiprocessors, sorting, graph algorithms, cache-oblivious algorithms
18	Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran	SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy.	DAC	2010	DBLP DOI BibTeX RDF	miss rate, simulation, round robin, cache simulation, L1 cache
18	Jaume Abella 0001, Javier Carretero, Pedro Chaparro, Xavier Vera, Antonio González 0001	Low Vccmin fault-tolerant cache with highly predictable performance.	MICRO	2009	DBLP DOI BibTeX RDF	Vccmin, cache, faults, predictable performance