Search results for "SOC"

Hits ?▲	Authors	Title	Venue	Year	Link
26	Shanshan Dai, Caleb R. Tulloss, Xiaoyu Lian, Kangping Hu, Sherief Reda, Jacob K. Rosenstein	Low Power Current-Mode Relaxation Oscillators for Temperature and Supply Voltage Monitoring.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
26	Jonas Gava, Ricardo Reis 0001, Luciano Ost	RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation Technique.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
26	Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon	3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
26	Adi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky	abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
26	Alessandro Veronesi, Davide Bertozzi, Milos Krstic	Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
26	Yinghua Hu, Kaixin Yang, Shahin Nazarian, Pierluigi Nuzzo 0002	SANSCrypt: Sporadic-Authentication-Based Sequential Logic Encryption.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
26	Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury	Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
26	Arnaud Poittevin, Chhandak Mukherjee, Ian O'Connor, Cristell Maneux, Guilhem Larrieu, Marina Deng, Sébastien Le Beux, François Marc, Aurélie Lecestre, Cédric Marchand 0002, Abhishek Kumar	3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
26	Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek	SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
26	David Cordova, Wim Cops, Yann Deval, François Rivet, Hervé Lapuyade, Nicolas Nodenot, Yohan Piccin	Low-Power High-Speed ADCs for ADC-Based Wireline Receivers in 22 nm FDSOI.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
26	Michail Maniatakos, Ibrahim Abe M. Elfadel, Matteo Sonza Reorda, H. Fatih Ugurdag, José Monteiro 0001, Ricardo Reis 0001 (eds.)	VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things - 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017, Revised and Extended Selected Papers	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
26	Nicola Bombieri, Graziano Pravadelli, Masahiro Fujita, Todd M. Austin, Ricardo Reis 0001 (eds.)	VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, Revised and Extended Selected Papers	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
26	Solon Falas, Charalambos Konstantinou, Maria K. Michael	Hardware-Enabled Secure Firmware Updates in Embedded Systems.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
26	Y. Serhan Gener, Furkan Aydin, Sezer Gören 0001, H. Fatih Ugurdag	Semi- and Fully-Random Access LUTs for Smooth Functions.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
26	Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis 0001	Process Variability Impact on the SET Response of FinFET Multi-level Design.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
26	László Szilágyi, Jan Plíva, Ronny Henker	Offset-Compensation Systems for Multi-Gbit/s Optical Receivers.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
26	Atishay, Ankit Gupta 0010, Rashmi Sonawat, Helik Kanti Thacker, Prasanth B	A Statistical Wafer Scale Error and Redundancy Analysis Simulator.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
26	Michelangelo Grosso, Matteo Sonza Reorda, Salvatore Rinaudo	Software-Based Self-Test for Delay Faults.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
26	Longfei Wang, Soner Seçkiner, Selçuk Köse	Reliability Enhanced Digital Low-Dropout Regulator with Improved Transient Performance.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
26	Leonardo B. Moraes, Alexandra Lackmann Zimpeck, Cristina Meinhardt, Ricardo A. L. Reis	Robust FinFET Schmitt Trigger Designs for Low Power Applications.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
26	Patsy Cadareanu, Ganesh Gore, Edouard Giacomin, Pierre-Emmanuel Gaillardon	A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
26	João Vieira, Edouard Giacomin, Yasir Mahmood Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon	Accelerating Inference on Binary Neural Networks with Digital RRAM Processing.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
26	Chen-Ying Hsieh, Ardalan Amiri Sani, Nikil D. Dutt	Exploiting Heterogeneous Mobile Architectures Through a Unified Runtime Framework.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
26	Rafael B. Schvittz, Denis Teixeira Franco, Leomar S. da Rosa, Paulo F. Butzen	An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
26	Vitor V. Bandeira, Felipe Rosa 0001, Ricardo Reis 0001, Luciano Ost	Efficient Soft Error Vulnerability Analysis Using Non-intrusive Fault Injection Techniques.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
26	Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik	On Test Generation for Microprocessors for Extended Class of Functional Faults.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
26	Bruno Forlin, Cezar Reinbrecht, Johanna Sepúlveda	Security Aspects of Real-Time MPSoCs: The Flaws and Opportunities of Preemptive NoCs.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
26	Valentino Peluso, Andrea Calimera	Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
26	Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada	A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
26	Md. Adnan Zaman, Rajeev Joshi, Srinivas Katkoori	Optimizing Performance and Energy Overheads Due to Fanout in In-Memory Computing Systems.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
26	Anna Bernasconi 0001, Antonio Boffa, Fabrizio Luccio, Linda Pagli	The Connection Layout in a Lattice of Four-Terminal Switches.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
26	Luca Stornaiuolo, Marco Rabozzi, Marco D. Santambrogio, Donatella Sciuto, Catalin Bogdan Ciobanu, Giulio Stramondo, Ana Lucia Varbanescu	Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
26	Swagata Mandal, Yaswanth Tavva, Debjyoti Bhattacharjee, Anupam Chattopadhyay	ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
26	Víctor H. Champac, Andres F. Gomez, Freddy Forero, Kaushik Roy 0001	Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
26	Xiaorui Liu, Anastasis Keliris, Charalambos Konstantinou, Marios Sazos, Michail Maniatakos	Assessment of Low-Budget Targeted Cyberattacks Against Power Systems.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
26	Francesco Barchi, Gianvito Urgese, Enrico Macii, Andrea Acquaviva	Mapping Spiking Neural Networks on Multi-core Neuromorphic Platforms: Problem Formulation and Performance Analysis.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
26	Tim Fritzmann, Thomas Schamberger, Christoph Frisch, Konstantin Braun, Georg Maringer, Johanna Sepúlveda	Efficient Hardware/Software Co-design for NTRU.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
26	Shahzad Muzaffar, Ibrahim Abe M. Elfadel	An Instruction Set Architecture for Secure, Low-Power, Dynamic IoT Communication.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
26	Riccardo Cantoro, Sara Carbonara, Andrea Floridia, Ernesto Sánchez 0001, Matteo Sonza Reorda, Jan-Gerd Mess	Improved Test Solutions for COTS-Based Systems in Space Applications.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
26	Utkarsh Gupta, Irina Ilioaea, Vikas Rao, Arpitha Srinath, Priyank Kalla, Florian Enescu	Rectification of Arithmetic Circuits with Craig Interpolants in Finite Fields.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF
26	Thomas Hollstein, Jaan Raik, Sergei Kostin, Anton Tsertov, Ian O'Connor, Ricardo Reis 0001 (eds.)	VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability - 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, Revised Selected Papers	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
26	Mohammed Ismail 0001	A self-powered IoT SoC platform for wearable health care.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
26	Wala Saadeh, Muhammad Awais Bin Altaf	A Wearable Neuro-Degenerative Diseases Classification System Using Human Gait Dynamics.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
26	Thiago Santos Copetti, Guilherme Cardoso Medeiros, Letícia Maria Bolzani Poehls, Tiago R. Balen	Evaluating the Impact of Resistive Defects on FinFET-Based SRAMs.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
26	Markus Stefan Wamser, Georg Sigl	Pushing the Limits Further: Sub-Atomic AES.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
26	Daniele Cesarini, Andrea Bartolini, Luca Benini	Modeling and Evaluation of Application-Aware Dynamic Thermal Control in HPC Nodes.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
26	Sukarn Agarwal, Hemangee K. Kapoor	Lifetime Enhancement of Non-Volatile Caches by Exploiting Dynamic Associativity Management Techniques.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
26	Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Jun Zhou 0017	On the Efficiency of Early Bird Sampling (EBS) an Error Detection-Correction Scheme for Data-Driven Voltage Over-Scaling.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
26	Vivek Nautiyal, Lalit Gupta, Gaurav Singla, Jitendra Dasani, Sagar Dwivedi, Martin Kinkade	Self-timed Power-on Reset Circuit for Pseudo Dual/Two Port SRAM Used in Low-Voltage IoT Applications.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
26	Stefano Aldegheri, Nicola Bombieri	Integrating Simulink, OpenVX, and ROS for Model-Based Design of Embedded Vision Applications.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
26	Shahzad Muzaffar, Ibrahim Abe M. Elfadel	Pulsed Decimal Encoding for IoT Single-Channel Dynamic Signaling.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
26	Matthias Thiele, Steve Bigalke, Jens Lienig	Electromigration Analysis of VLSI Circuits Using the Finite Element Method.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
26	Youngsoo Shin, Chi-Ying Tsui, Jae-Joon Kim, Kiyoung Choi, Ricardo Reis 0001 (eds.)	VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected Papers	VLSI-SoC (Selected Papers)	2016	DBLP DOI BibTeX RDF
26	Yanzhe Li, Kai Huang 0002, Luc Claesen	SoC oriented real-time high-quality stereo vision system.	VLSI-SoC	2016	DBLP DOI BibTeX RDF
26	Maedeh Hemmat, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram	Robust Hybrid TFET-MOSFET Circuits in Presence of Process Variations and Soft Errors.	VLSI-SoC (Selected Papers)	2016	DBLP DOI BibTeX RDF
26	Guillaume Plassan, Hans-Jörg Peter, Katell Morin-Allory, Shaker Sarwary, Dominique Borrione	Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings.	VLSI-SoC (Selected Papers)	2016	DBLP DOI BibTeX RDF
26	Xueqing Li, Kaisheng Ma, Sumitha George, John Sampson, Vijaykrishnan Narayanan	Enabling Internet-of-Things with Opportunities Brought by Emerging Devices, Circuits and Architectures.	VLSI-SoC (Selected Papers)	2016	DBLP DOI BibTeX RDF
26	Nimrod Wald, Elad Amrani, Avishay Drori, Shahar Kvatinsky	Logic with Unipolar Memristors - Circuits and Design Methodology.	VLSI-SoC (Selected Papers)	2016	DBLP DOI BibTeX RDF
26	Yanzhe Li, Kai Huang 0002, Luc Claesen	A Novel Hardware-Oriented Stereo Matching Algorithm and Its Architecture Design in FPGA.	VLSI-SoC (Selected Papers)	2016	DBLP DOI BibTeX RDF
26	Alexander W. Rath, Sebastian Simon, Volkan Esen, Wolfgang Ecker	Earth Mover's Distance as a Comparison Metric for Analog Behavior.	VLSI-SoC (Selected Papers)	2016	DBLP DOI BibTeX RDF
26	Valentino Peluso, Roberto Giorgio Rizzo, Andrea Calimera, Enrico Macii, Massimo Alioto	Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping.	VLSI-SoC (Selected Papers)	2016	DBLP DOI BibTeX RDF
26	Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino	Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits.	VLSI-SoC (Selected Papers)	2016	DBLP DOI BibTeX RDF
26	Syed Mohsin Abbas, Chi-Ying Tsui	Approximate Matrix Inversion for Linear Pre-coders in Massive MIMO.	VLSI-SoC (Selected Papers)	2016	DBLP DOI BibTeX RDF
26	Johannes Schreiner, Wolfgang Ecker	Digital Hardware Design Based on Metamodels and Model Transformations.	VLSI-SoC (Selected Papers)	2016	DBLP DOI BibTeX RDF
26	Alex Orailoglu, H. Fatih Ugurdag, Luís Miguel Silveira, Martin Margala, Ricardo Reis 0001 (eds.)	VLSI-SoC: At the Crossroads of Emerging Trends - 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended Selected Papers	VLSI-SoC (Selected Papers)	2015	DBLP DOI BibTeX RDF
26	Luc Claesen, María Teresa Sanz-Pascual, Ricardo Reis 0001, Arturo Sarmiento-Reyes (eds.)	VLSI-SoC: Internet of Things Foundations - 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2014, Playa del Carmen, Mexico, October 6-8, 2014, Revised and Extended Selected Papers	VLSI-SoC (Selected Papers)	2015	DBLP DOI BibTeX RDF
26	Manikantan Srinivasan, C. Siva Ram Murthy, Anusuya Balasubramanian	Modular performance analysis of Multicore SoC-based small cell LTE base station.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
26	Manikandan Pandiyan, Geetha Mani, Jovitha Jerome, Natarajan S.	Integrating wearable low power CMOS ECG acquisition SoC with decision making system for WSBN applications.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
26	Xabier Iturbe, Didier Keymeulen, Emre Ozer 0001, Patrick Yiu, Daniel Berisford, Kevin P. Hand, Robert Carlson	An integrated SoC for science data processing in next-generation space flight instruments avionics.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
26	Hyungil Park, Ingi Lim, Sungweon Kang, Whan-woo Kim	10Mbps human body communication SoC for BAN.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
26	Anvesha Amaravati, Manan Chugh, Arijit Raychowdhury	A SAR Pipeline ADC Embedding Time Interleaved DAC Sharing for Ultra-low Power Camera Front Ends.	VLSI-SoC (Selected Papers)	2015	DBLP DOI BibTeX RDF
26	Xabier Iturbe, Didier Keymeulen, Patrick Yiu, Daniel Berisford, Robert Carlson, Kevin P. Hand, Emre Ozer 0001	On the Use of System-on-Chip Technology in Next-Generation Instruments Avionics for Space Exploration.	VLSI-SoC (Selected Papers)	2015	DBLP DOI BibTeX RDF
26	Asim Khan, Muhammad Umar Karim Khan, Muhammad Bilal 0001, Chong-Min Kyung	A Hardware Accelerator for Real Time Sliding Window Based Pedestrian Detection on High Resolution Images.	VLSI-SoC (Selected Papers)	2015	DBLP DOI BibTeX RDF
26	Alessandro Danese, Francesca Filini, Tara Ghasempouri, Graziano Pravadelli	Automatic Generation and Qualification of Assertions on Control Signals: A Time Window-Based Approach.	VLSI-SoC (Selected Papers)	2015	DBLP DOI BibTeX RDF
26	Raimund Ubar, Lembit Jürimägi, Elmet Orasson, Jaan Raik	Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs.	VLSI-SoC (Selected Papers)	2015	DBLP DOI BibTeX RDF
26	Alberto Bocca, Alessandro Sassone, Donghwa Shin, Alberto Macii, Enrico Macii, Massimo Poncino	A Temperature-Aware Battery Cycle Life Model for Different Battery Chemistries.	VLSI-SoC (Selected Papers)	2015	DBLP DOI BibTeX RDF
26	Masahiro Fujita	Delay Testing Based on Multiple Faulty Behaviors.	VLSI-SoC (Selected Papers)	2015	DBLP DOI BibTeX RDF
26	Lilian Bossuet, Pierre Bayon, Viktor Fischer	Electromagnetic Transmission of Intellectual Property Data to Protect FPGA Designs.	VLSI-SoC (Selected Papers)	2015	DBLP DOI BibTeX RDF
26	Chun-Jen Tsai, Tsung-Han Wu, Hung-Cheng Su, Cheng-Yang Chen	JAIP-MP: A Four-Core Java Application Processor for Embedded Systems.	VLSI-SoC (Selected Papers)	2015	DBLP DOI BibTeX RDF
26	Jesus-Andres Mendoza-Bonilla, Alejandro Cortez-Ibarra, Edgar-Andrei Vega-Ochoa, Francisco Rangel-Patino, Brandon Gore	Backplane/FDA correlation-FDA replacing commercial backplanes for SoC ethernet electrical validation.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
26	Farshad Moradi, Mohammad Tohidi, Behzad Zeinali, Jens Kargaard Madsen	8T-SRAM Cell with Improved Read and Write Margins in 65 nm CMOS Technology.	VLSI-SoC (Selected Papers)	2014	DBLP DOI BibTeX RDF
26	Kerem Seyid, Ömer Çogal, Vladan Popovic, Hossein Afshari, Alexandre Schmid, Yusuf Leblebici	Real-Time Omnidirectional Imaging System with Interconnected Network of Cameras.	VLSI-SoC (Selected Papers)	2014	DBLP DOI BibTeX RDF
26	Liang Wang 0020, Xiaohang Wang 0001, Terrence S. T. Mak	Dynamic Programming-Based Lifetime Reliability Optimization in Networks-on-Chip.	VLSI-SoC (Selected Papers)	2014	DBLP DOI BibTeX RDF
26	Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir, Manuel J. Barragán	Statistical Evaluation of Digital Techniques for $\sum\varDelta$ ADC BIST.	VLSI-SoC (Selected Papers)	2014	DBLP DOI BibTeX RDF
26	Jinwook Jung, Dongsoo Lee, Youngsoo Shin	Design and Optimization of Multiple-Mesh Clock Network.	VLSI-SoC (Selected Papers)	2014	DBLP DOI BibTeX RDF
26	Vincent Beroulle, Philippe Candelier, Stephan De Castro, Giorgio Di Natale, Jean-Max Dutertre, Marie-Lise Flottes, David Hély, Guillaume Hubert, Régis Leveugle, Feng Lu, Paolo Maistri, Athanasios Papadimitriou, Bruno Rouzeyre, Clément Tavernier, Pierre Vanhauwaert	Laser-Induced Fault Effects in Security-Dedicated Circuits.	VLSI-SoC (Selected Papers)	2014	DBLP DOI BibTeX RDF
26	Shilpa Pendyala, Srinivas Katkoori	Interval Arithmetic and Self Similarity Based Subthreshold Leakage Optimization in RTL Datapaths.	VLSI-SoC (Selected Papers)	2014	DBLP DOI BibTeX RDF
26	Dominik Auras, Uwe Deidersen, Rainer Leupers, Gerd Ascheid	A Parallel MCMC-Based MIMO Detector: VLSI Design and Algorithm.	VLSI-SoC (Selected Papers)	2014	DBLP DOI BibTeX RDF
26	Sreenivaas S. Muthyala, Nur A. Touba	Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs.	VLSI-SoC (Selected Papers)	2014	DBLP DOI BibTeX RDF
26	Dongwoo Lee, Kiyoung Choi	Energy-Efficient Partitioning of Hybrid Caches in Multi-core Architecture.	VLSI-SoC (Selected Papers)	2014	DBLP DOI BibTeX RDF
26	Thomas Marconi, Christian Spagnol, Emanuel M. Popovici, Sorin Cotofana	Transmission Channel Noise Aware Energy Effective LDPC Decoding.	VLSI-SoC (Selected Papers)	2014	DBLP DOI BibTeX RDF
26	Alessandro Lonardi, Graziano Pravadelli	On the Co-simulation of SystemC with QEMU and OVP Virtual Platforms.	VLSI-SoC (Selected Papers)	2014	DBLP DOI BibTeX RDF
26	Andreas Burg, Ayse K. Coskun, Matthew R. Guthaus, Srinivas Katkoori, Ricardo Reis 0001 (eds.)	VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design - 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers	VLSI-SoC (Selected Papers)	2013	DBLP DOI BibTeX RDF
26	Wael Adi, Shaza Zeitouni, X. Huang, Marc Fyrbiak, Christian Kison, Marc Jeske, Z. Alnahhas	IP-core protection for a non-volatile Self-reconfiguring SoC environment.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
26	Yankin Tanurhan, Pieter van der Wolf	Processors as SoC building blocks.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
26	Jonathan van de Belt, Paul D. Sutton, Linda Doyle	Accelerating software radio: Iris on the Zynq SoC.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
26	Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal	Power-aware SoC test optimization through dynamic voltage and frequency scaling.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
26	Baris Özgül, Jan Langer, Juanjo Noguera, Kees A. Vissers	Software-programmable digital pre-distortion on the Zynq SoC.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
26	Abdulkadir Akin, Luis Manuel Gaemperle, Halima Najibi, Alexandre Schmid, Yusuf Leblebici	Enhanced Compressed Look-up-Table Based Real-Time Rectification Hardware.	VLSI-SoC (Selected Papers)	2013	DBLP DOI BibTeX RDF
26	Yuan Ren, Tobias G. Noll	Quantitative Optimization and Early Cost Estimation of Low-Power Hierarchical-Architecture SRAMs Based on Accurate Cost Models.	VLSI-SoC (Selected Papers)	2013	DBLP DOI BibTeX RDF