Search results for "self-test"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Zhaoliang Pan, Melvin A. Breuer	Estimating Error Rate in Defective Logic Using Signature Analysis.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Binning integrated circuits, effective yield, signature testing, error rate, error tolerance, yield loss
16	Hafizur Rahaman 0001, Jimson Mathew, Dhiraj K. Pradhan	Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m).	VLSI Design	2007	DBLP DOI BibTeX RDF
16	Jiann-Chyi Rau, Po-Han Wu, Chia-Jung Liu	A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits.	APCCAS	2006	DBLP DOI BibTeX RDF
16	Cheng-Wen Wu	SOC Testing Methodology and Practice.	DATE	2005	DBLP DOI BibTeX RDF
16	Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero	On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors.	DFT	2005	DBLP DOI BibTeX RDF
16	Lei Li 0036, Krishnendu Chakrabarty	Test set embedding for deterministic BIST using a reconfigurable interconnection network.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
16	Ozgur Sinanoglu, Alex Orailoglu	Autonomous Yet Deterministic Test of SOC Cores.	ITC	2004	DBLP DOI BibTeX RDF
16	Christophe Fagot, Olivier Gascuel, Patrick Girard 0001, Christian Landrault	A Ring Architecture Strategy for BIST Test Pattern Generation.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	pseudo-random testing, deterministic BIST, logic BIST
16	Elham Safi, Zohreh Karimi, Maghsoud Abbaspour, Zainalabedin Navabi	Utilizing Various ADL Facets for Instruction Level CPU Test.	MTV	2003	DBLP DOI BibTeX RDF
16	Hiroshi Takahashi, Yasunori Tsugaoka, Hidekazu Ayano, Yuzo Takamatsu	BIST Based Fault Diagnosis Using Ambiguous Test Set.	DFT	2003	DBLP DOI BibTeX RDF
16	Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin	X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST Architecture.	ITC	2003	DBLP DOI BibTeX RDF
16	Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas	A new built-in TPG method for circuits with random patternresistant faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
16	Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras	RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST.	ITC	2002	DBLP DOI BibTeX RDF
16	Kun-Han Tsai, Janusz Rajski, Malgorzata Marek-Sadowska	Star test: the theory and its applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
16	C. P. Ravikumar, Gaurav Chandra, Ashutosh Verma	Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based Systems.	VLSI Design	2000	DBLP DOI BibTeX RDF
16	Paulo F. Flores, Horácio C. Neto, Krishnendu Chakrabarty, João Marques-Silva 0001	Test pattern generation for width compression in BIST.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
16	Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia	Pseudo-exhaustive built-in TPG for sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
16	Mody Lempel, Sandeep K. Gupta 0001, Melvin A. Breuer	Test embedding with discrete logarithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
16	Chien-In Henry Chen, Joel T. Yuen	Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
16	Frans P. M. Beenker, Barry J. Dekker, Richard Stans, Max van der Star	Implementing Macro Test in Silicon Compiler Design.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
15	Anand Gopalan, Tejasvi Das, Clyde Washburn, P. R. Mukund	An Ultra-Fast, On-Chip BiST for RF Low Noise Amplifiers.	VLSI Design	2005	DBLP DOI BibTeX RDF
15	Nektarios Kranitis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Low-Cost Software-Based Self-Testing of RISC Processor Cores.	DATE	2003	DBLP DOI BibTeX RDF
15	Andrzej Krasniewski	Design of Dependable Hardware: What BIST is most Efficient?	EDCC	1996	DBLP DOI BibTeX RDF
15	Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu	A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories.	MTDT	2004	DBLP DOI BibTeX RDF
15	Praveen Parvathala, Kaila Maneparambil, William Lindsay	FRITS - A Microprocessor Functional BIST Method.	ITC	2002	DBLP DOI BibTeX RDF
15	Andreas Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Functional Self-Testing for Bus-Based Symmetric Multiprocessors.	DATE	2008	DBLP DOI BibTeX RDF
14	V. Vireen, N. Venugopalachary, G. Seetharaman, B. Venkataramani	Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs.	VLSI Design	2009	DBLP DOI BibTeX RDF
14	Yao-Hsin Chou, Sy-Yen Kuo, I-Ming Tsai	QBIST: Quantum Built-in Self-Test for any Boolean Circuit.	VTS	2008	DBLP DOI BibTeX RDF
14	Zhanglei Wang, Krishnendu Chakrabarty	Built-in Self-test and Defect Tolerance in Molecular Electronics-based Nanofabrics.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	nanofabric, CAEN, chemically assembled, reconfiguration, BIST, nanotechnology, defect tolerance, molecular electronics
14	Murari Kejariwal, Prasad Ammisetti, John Melanson	Built-in self-test mode in a multi-path feedforward compensated operational amplifier.	ISCAS	2006	DBLP DOI BibTeX RDF
14	R. Dean Adams, Robert Abbott, Xiaoliang Bai, Dwayne Burek, Eric MacDonald	An Integrated Memory Self Test and EDA Solution.	MTDT	2004	DBLP DOI BibTeX RDF
14	Hak-soo Yu, Sungbae Hwang, Jacob A. Abraham	DSP-Based Statistical Self Test of On-Chip Converters.	VTS	2003	DBLP DOI BibTeX RDF
14	Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li 0001, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin	A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	memory BIST, memory diagnostics, memory testing, RAM, semiconductor memory
14	Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni, Dimitris Nikolos	A Versatile Built-In Self-Test Scheme for Delay Fault Testing.	DATE	2000	DBLP DOI BibTeX RDF
14	Gloria Huertas, Diego Vázquez, Adoración Rueda, José L. Huertas	Built-In Self-Test in Mixed-Signal ICs: A DTMF Macrocell.	VLSI Design	2000	DBLP DOI BibTeX RDF
14	Ivo Schanstra, Dharmajaya Lukita, Ad J. van de Goor, Kees Veelenturf, Paul J. van Wijnen	Semiconductor manufacturing process monitoring using built-in self-test for embedded memories.	ITC	1998	DBLP DOI BibTeX RDF	diagnosis, BIST, fault localization, process monitoring, bitmap, RAM testing, microcode
14	Benoît R. Veillette, Gordon W. Roberts	Stimulus generation for built-in self-test of charge-pump phase-locked loops.	ITC	1998	DBLP DOI BibTeX RDF
14	Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer	Automated synthesis of large phase shifters for built-in self-test.	ITC	1998	DBLP DOI BibTeX RDF
14	Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda	Circular Self-Test Path for FSMs.	IEEE Des. Test Comput.	1996	DBLP DOI BibTeX RDF
14	T. C. Davies, Dhamin Al-Khalili, Valek Szwarc	A floating-point systolic array processing element with serial communication and built-in self-test.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
14	Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja	A Tutorial on Built-in Self-Test. I. Principles.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
14	Chun-Yeh Liu, Kewal K. Saluja, Shambhu J. Upadhyaya	BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic Arrays.	DAC	1987	DBLP DOI BibTeX RDF
14	Dong Xiang, Mingjing Chen, Jia-Guang Sun	Scan BIST with biased scan test signals.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	random testability, test signal, biased random testing, scan-based BIST
14	Malav Shah, Dipankar Nagchoudhuri	BIST Scheme for Low Heat Dissipation and Reduced Test Application Time.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
14	Hanqing Xing, Degang Chen 0001, Randall L. Geiger	Linearity test for high resolution DACs using low-accuracy DDEM flash ADCs.	ISCAS	2006	DBLP DOI BibTeX RDF
14	Reza M. Rad, Mohammad Tehranipoor	SCT: An Approach For Testing and Configuring Nanoscale Devices.	VTS	2006	DBLP DOI BibTeX RDF
14	Shao Chee Ong	Enabling Test-Time Optimized Pseudorandom Bit Stream (PRBS) 2^31 BER Testing on Automated Test Equipment for 10Gbps Device.	DELTA	2006	DBLP DOI BibTeX RDF
14	Masood ul-Hasan, Yichuang Sun	Oscillation-based Test Method for Continuous-time OTA-C Filters.	APCCAS	2006	DBLP DOI BibTeX RDF
14	Luís Rolíndez, Salvador Mir, Guillaume Prenat, Ahcène Bounceur	A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns.	DATE	2004	DBLP DOI BibTeX RDF
14	Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya	Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults.	VLSI Design	2004	DBLP DOI BibTeX RDF
14	Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu	Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
14	Der-Cheng Huang, Wen-Ben Jone	A parallel transparent BIST method for embedded memory arrays bytolerating redundant operations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
14	Lihong Tong, Kazuki Suzuki, Hideo Ito	Optimal Seed Generation for Delay Fault Detection BIST.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
14	Hamidreza Hashempour, Fred J. Meyer, Fabrizio Lombardi	Test Time Reduction in a Manufacturing Environment by Combining BIST and ATE.	DFT	2002	DBLP DOI BibTeX RDF
14	Hamed Farshbaf, Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi	Fault Simulation for VHDL Based Test Bench and BIST Evaluation.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
14	Irith Pomeranz, Sudhakar M. Reddy	On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	irredundant faults, built-in test generation, test generation, synchronous sequential circuits, Initial states
14	Michael Cogswell, Don Pearl, James Sage, Alan Troidl	An Automatic Validation Methodology for Logic BIST in High Performance VLSI Design.	ICCD	2000	DBLP DOI BibTeX RDF
14	Ondrej Novák	Pseudorandom, Weighted Random and Pseudoexhaustive Test Patterns Generated in Universal Cellular Automata.	EDCC	1999	DBLP DOI BibTeX RDF	linear cyclic codes, hardware test pattern generators, weighted random testing, Cellular automata, BIST, linear feedback shift registers, pseudoexhaustive testing
14	Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Test Vector Inhibiting Technique for Low Energy BIST Design.	VTS	1999	DBLP DOI BibTeX RDF
14	Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik	Efficient test-point selection for scan-based BIST.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
14	Rainer Dorsch, Hans-Joachim Wunderlich	Accumulator based deterministic BIST.	ITC	1998	DBLP DOI BibTeX RDF	hardware pattern generator, BIST, embedded cores
14	Magdy S. Abadir, Ashish Parikh, Linda Bal, Peter Sandborn, Cynthia F. Murphy	High Level Test Economics Advisor (Hi-TEA).	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	MCM testing strategies, multichip module, test economics
14	David L. Landis	A test methodology for wafer scale system.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
14	Hans-Joachim Wunderlich	Multiple distributions for biased random test patterns.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
14	Lorena Anghel, Riccardo Cantoro, Riccardo Masante, Michele Portolan, Sandro Sartoni, Matteo Sonza Reorda	Self-Test Library Generation for In-Field Test of Path Delay Faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
14	Senling Wang, Xihong Zhou, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima	Test Point Insertion for Multi-Cycle Power-On Self-Test.	ACM Trans. Design Autom. Electr. Syst.	2023	DBLP DOI BibTeX RDF
14	Annachiara Ruospo, Gabriele Gavarini, A. Porsia, Matteo Sonza Reorda, Ernesto Sánchez 0001, Riccardo Mariani, J. Aribido, Jyotika Athavale	Image Test Libraries for the on-line self-test of functional units in GPUs running CNNs.	ETS	2023	DBLP DOI BibTeX RDF
14	Yang Sun, Spencer K. Millican	Applying Artificial Neural Networks to Logic Built-in Self-test: Improving Test Point Insertion.	J. Electron. Test.	2022	DBLP DOI BibTeX RDF
14	Vishnupriya Shivakumar, Chinnaiyan Senthilpari, Zubaida Binti Yusoff	Test power and area optimized logic built-in self-test with higher fault coverage for automobile SoCs.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
14	Jia-Ruei Liang, Ya-Ni Hsieh, Jiun-Lang Huang	Test Response Compaction for Software-Based Self-Test.	ITC-Asia	2022	DBLP DOI BibTeX RDF
14	Irith Pomeranz	Storage-Based Logic Built-In Self-Test with Variable-Length Test Data.	DFT	2022	DBLP DOI BibTeX RDF
14	Tao Chen 0006, Chulhyun Park, Hao Meng, Dadian Zhou, José Silva-Martínez, Randall L. Geiger, Degang Chen 0001	A Low-Cost On-Chip Built-In Self-Test Solution for ADC Linearity Test.	IEEE Trans. Instrum. Meas.	2020	DBLP DOI BibTeX RDF
14	Serge N. Demidenko, Moi-Tin Chew, B. T. Nguyen, Melanie Po-Leen Ooi, Ye Chow Kuang	Logic Built-In Self-Test Instrumentation System for Engineering Test Technology Education.	I2MTC	2020	DBLP DOI BibTeX RDF
14	Yang Sun, Spencer K. Millican, Vishwani D. Agrawal	Special Session: Survey of Test Point Insertion for Logic Built-in Self-test.	VTS	2020	DBLP DOI BibTeX RDF
14	Kuen-Jong Lee, Bo-Ren Chen, Michael Andreas Kochte	On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2019	DBLP DOI BibTeX RDF
14	Ching-Yuan Chen, Jiun-Lang Huang	Reinforcement-Learning-Based Test Program Generation for Software-Based Self-Test.	ATS	2019	DBLP DOI BibTeX RDF
14	Dong Xiang, Xiaoqing Wen, Laung-Terng Wang	Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
14	Adeboye Stephen Oyeniran, Artjom Jasnetski, Anton Tsertov, Raimund Ubar	High-level test data generation for software-based self-test in microprocessors.	MECO	2017	DBLP DOI BibTeX RDF
14	Kuen-Jong Lee, Pin-Hao Tang, Michael A. Kochte	An on-chip self-test architecture with test patterns recorded in scan chains.	ITC	2016	DBLP DOI BibTeX RDF
14	Mahdieh Nadi Senejani, Mahdiar Hosein Ghadiry, Chia Yee Ooi, Muhammad Nadzir Marsono	Built-in Self Test Power and Test Time Analysis in On-chip Networks.	Circuits Syst. Signal Process.	2015	DBLP DOI BibTeX RDF
14	Ran Wang 0002, Krishnendu Chakrabarty, Sudipta Bhawmik	Built-In Self-Test and Test Scheduling for Interposer-Based 2.5D IC.	ACM Trans. Design Autom. Electr. Syst.	2015	DBLP DOI BibTeX RDF
14	Christian G. Zöllin	Test planning for low-power built-in self test.		2015	RDF
14	Prakash Narayanan, Satish Ravichandran, Balaji Ramayanam	Novel self-test methods to reduce on-chip memory requirements and improved test coverage.	IOLTS	2014	DBLP DOI BibTeX RDF
14	Aiwu Ruan, Shi Kang, Yu Wang, Xiao Han, Zujian Zhu, Yongbo Liao, Peng Li	A Built-In Self-Test (BIST) system with non-intrusive TPG and ORA for FPGA test and diagnosis.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
14	Yuki Fukazawa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue	A Transient Fault Tolerant Test Pattern Generator for On-line Built-in Self-Test.	Asian Test Symposium	2013	DBLP DOI BibTeX RDF
14	Yu-Jen Huang, Jin-Fu Li 0001	Low-Cost Self-Test Techniques for Small RAMs in SOCs Using Enhanced IEEE 1500 Test Wrappers.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
14	Hyunjin Kim, Jacob A. Abraham	A Built-in Self-Test Scheme for Memory Interfaces Timing Test and Measurement.	J. Electron. Test.	2012	DBLP DOI BibTeX RDF
14	Davide Sabena, Luca Sterpone, Matteo Sonza Reorda	On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors.	VLSI-SoC (Selected Papers)	2012	DBLP DOI BibTeX RDF
14	Hyunjin Kim, Jacob A. Abraham	A Built-In Self-Test scheme for DDR memory output timing test and measurement.	VTS	2012	DBLP DOI BibTeX RDF
14	Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Benoit Nadeau-Dostie	Test generator with preselected toggling for low power built-in self-test.	VTS	2012	DBLP DOI BibTeX RDF
14	Balwinder Singh, Sukhleen Bindra Narang, Arun Khosla	Analysis of Cellular Automata and Genetic Algorithm based Test Pattern Generators for Built In Self Test.	BIC-TA (1)	2012	DBLP DOI BibTeX RDF
14	A. Ahmad	A Simulation Experiment on a Built-In Self Test Equipped with Pseudorandom Test Pattern Generator and Multi-Input Shift Register (MISR)	CoRR	2011	DBLP BibTeX RDF
14	Yu-Jen Huang, Jin-Fu Li 0001, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu	A built-in self-test scheme for the post-bond test of TSVs in 3D ICs.	VTS	2011	DBLP DOI BibTeX RDF
14	Abhishek P. Chhetri, Forrest Wen, Yizhong Wang, Kang Zhang 0001	Shape discrimination test on handheld devices for patient self-test.	IHI	2010	DBLP DOI BibTeX RDF
14	Amit Dutta, Malav Shah, G. Swathi, Rubin A. Parekhji	Design techniques and tradeoffs in implementing non-destructive field test using logic BIST self-test.	IOLTS	2009	DBLP DOI BibTeX RDF
14	Xinhui Zhang, Chien-In Henry Chen, Arvindkumar Chakravarthy	Structure Design and Optimization of 2-D LFSR-Based Multisequence Test Generator in Built-In Self-Test.	IEEE Trans. Instrum. Meas.	2008	DBLP DOI BibTeX RDF
14	Tomoo Inoue, Takashi Fujii, Hideyuki Ichihara	A Self-Test of Dynamically Reconfigurable Processors with Test Frames.	IEICE Trans. Inf. Syst.	2008	DBLP DOI BibTeX RDF
14	Aftab Farooqi	MARKOV source based test length optimized scan built-in-self-test architecture.		2008	RDF
14	Shanrui Zhang, Minsu Choi, Nohpill Park, Fabrizio Lombardi	Cost-Driven Optimization of Coverage of Combined Built-In Self-Test/Automated Test Equipment Testing.	IEEE Trans. Instrum. Meas.	2007	DBLP DOI BibTeX RDF
14	V. V. Belkin, S. G. Sharshunov	ISA Based Functional Test Generation with Application to Self-Test of RISC Processors.	DDECS	2006	DBLP DOI BibTeX RDF