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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 14306 occurrences of 4820 keywords
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Found 45278 publication records. Showing 45278 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
26 | José M. Mendías, Román Hermida |
Correct High-Level Synthesis: a Formal Perspective. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
automatic formal synthesis, formal verification, high-level synthesis, streams |
26 | Pradeep Prabhakaran, Prithviraj Banerjee |
Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
timing driven synthesis, High-level synthesis, floorplanning |
26 | Sumit Roy 0003, Prithviraj Banerjee |
A Comparison of Parallel Approaches for Algebraic Factorization in Logic Synthesis. |
IPPS |
1997 |
DBLP DOI BibTeX RDF |
algebraic factorization, circuit replication, totally independent factorization, L-shaped partitioning strategy, rectangle interaction, ex1010 circuit, sequential kernel extraction algorithms, SIS sequential circuit synthesis system, quality degradation, parallel algorithms, logic synthesis, logic CAD, circuit partitions, divide-and-conquer strategy |
26 | Oliver Bringmann 0001, Wolfgang Rosenstiel |
Resource sharing in hierarchical synthesis. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
Hierarchical Synthesis, High-Level Synthesis, Resource Sharing |
26 | Shashank K. Mehta, Kent L. Einspahr, Sharad C. Seth |
Synthesis for Testability by Two-Clock Control. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
two-clock control scheme, split coding system, FSM benchmark, timing, finite state machine, sequential circuit, encoding, logic synthesis, Hamiltonian cycle, synthesis for testability, state transition graph |
26 | Tony Ezzat, Tomaso A. Poggio |
Facial Analysis and Synthesis Using Image-Based Models. |
FG |
1996 |
DBLP DOI BibTeX RDF |
facial synthesis, analysis by synthesis, image-based facial models, facial analysis |
26 | Sukumar Nandi, Parimal Pal Chaudhuri |
Theory and applications of cellular automata for synthesis of easily testable combinational logic. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
testable combinational logic, combinational logic blocks, test machine, data path synthesis phase, autonomous mode, aliasing error probability, associated lines, test application overheads, test parallelism, simultaneous testing, multiple combinational modules, graph theory, fault diagnosis, logic testing, high level synthesis, test generation, cellular automata, cellular automata, design for testability, combinational circuits, logic CAD, stuck-at faults, shift registers, cost effectiveness, registers, test vectors, test responses, state transition graph |
26 | Glenn Holt, Akhilesh Tyagi |
EPNR: an energy-efficient automated layout synthesis package. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
EPNR, energy-efficient automated layout synthesis package, MCNC Logic Synthesis '93 benchmarks, VPNR, VLSI energy minimization problems, VLSI, logic testing, placement, logic CAD, circuit layout CAD, global routing, logic arrays, standard cells, channel routing |
26 | Ireneusz Karkowski |
Architectural synthesis with possibilistic programming. |
HICSS (1) |
1995 |
DBLP DOI BibTeX RDF |
possibilistic programming, fuzzy mathematical programming, simultaneous scheduling, FOAS, computational complexity, computational complexity, fuzzy logic, high level synthesis, high-level synthesis, circuit CAD, mathematical programming, possibility theory |
26 | Santonu Sarkar, Anupam Basu, Arun K. Majumdar |
Synchronization of communicating modules and processes in high level synthesis. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
communicating modules, object oriented design framework, nonblocking channel, real life image processing, synchronization, high level synthesis, high level synthesis, application specific integrated circuits, synchronisation, object-oriented methods, component reuse, ASIC designs, image processing equipment |
26 | Dorothy E. Setliff, Rob A. Rutenbar |
Knowledge Representation and Reasoning in a Software Synthesis Architecture. |
IEEE Trans. Software Eng. |
1992 |
DBLP DOI BibTeX RDF |
software synthesis architecture, reasoning strategies, automatic program synthesis architecture, ELF, procedure-level decomposition, synthetic router, data structures, knowledge representation, knowledge representation, computer-aided design, inference mechanisms, automatic programming, circuit layout CAD, design space, VLSI circuits, domain-specific knowledge |
26 | Siliang Lv, Shangfei Wang, Xufa Wang |
Emotional speech synthesis by XML file using interactive genetic algorithms. |
GEC Summit |
2009 |
DBLP DOI BibTeX RDF |
emotion, speech synthesis, interactive genetic algorithms |
26 | Jason Cong, Bin Liu 0006, Zhiru Zhang |
Behavior-level observability don't-cares and application to low-power behavioral synthesis. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
low power, observability, behavioral synthesis |
26 | Thomas Chatain, Paul Gastin, Nathalie Sznajder |
Natural Specifications Yield Decidability for Distributed Synthesis of Asynchronous Systems. |
SOFSEM |
2009 |
DBLP DOI BibTeX RDF |
Distributed synthesis, Asynchronous systems |
26 | Purandar Bhaduri, S. Ramesh |
Interface synthesis and protocol conversion. |
Formal Aspects Comput. |
2008 |
DBLP DOI BibTeX RDF |
Component compatibility, Interface synthesis, Interface automata, Protocol conversion |
26 | Wan-Chun Ma, Andrew Jones 0001, Jen-Yuan Chiang, Tim Hawkins, Sune Frederiksen, Pieter Peers, Marko Vukovic, Ming Ouhyoung, Paul E. Debevec |
Facial performance synthesis using deformation-driven polynomial displacement maps. |
ACM Trans. Graph. |
2008 |
DBLP DOI BibTeX RDF |
facial performance synthesis, polynomial displacement maps |
26 | Jason Cong, Wei Jiang |
Pattern-based behavior synthesis for FPGA resource reduction. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
FPGA, pattern, behavior synthesis |
26 | Jian Xiang, Hongli Zhu |
Automatic Subspace Synthesis of Motion Styles Based on Isomap. |
ICIC (2) |
2008 |
DBLP DOI BibTeX RDF |
synthesis, subspace, Isomap, Motion style |
26 | Matthew Hockenberry, Leonardo Bonanni |
Renaissance panel: the roles of creative synthesis in innovation. |
CHI Extended Abstracts |
2008 |
DBLP DOI BibTeX RDF |
creative synthesis, hybrid practices, design, management, creativity, innovation, art, interdisciplinary |
26 | Martin Lukac, Marek A. Perkowski |
Projective Measurement-Based Logic Synthesis of Quantum Circuits. |
ISMVL |
2008 |
DBLP DOI BibTeX RDF |
Projective Measurement, Logic Synthesis, Quantum Circuits |
26 | France Mihelic, Bostjan Vesnicer, Janez Zibert, Elmar Nöth |
Prosodic Events Recognition in Evaluation of Speech-Synthesis System Performance. |
TSD |
2008 |
DBLP DOI BibTeX RDF |
Speech synthesis, prosody, system evaluation |
26 | Ruchir Puri, William H. Joyner, Shekhar Borkar, Ty Garibay, Jonathan Lotz, Robert K. Montoye |
Custom is from Venus and synthesis from Mars. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
IC synthesis techniques, custom IC design, VLSI design |
26 | Don S. Batory |
From implementation to theory in product synthesis. |
POPL |
2007 |
DBLP DOI BibTeX RDF |
features, program synthesis, category theory, mixins, model driven design, virtual classes, AHEAD, GenVoca |
26 | Greg Stitt, Frank Vahid, Walid A. Najjar |
A code refinement methodology for performance-improved synthesis from C. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
code refinement, coding guidelines, FPGA, embedded systems, compilation, synthesis, hardware/software partitioning |
26 | Yiping Wang, Wencheng Wang, Enhua Wu |
Optimizing the parameters for patch-based texture synthesis. |
VRCIA |
2006 |
DBLP DOI BibTeX RDF |
patch-based texture synthesis, texture features, adaptive optimization |
26 | Jicheng Fu, Farokh B. Bastani, I-Ling Yen |
Automated AI Planning and Code Pattern Based Code Synthesis. |
ICTAI |
2006 |
DBLP DOI BibTeX RDF |
Automated code synthesis, Graphplan, AI planning, Embedded real-time systems, Code patterns |
26 | Lujin Wang, Xianfeng Gu, Klaus Mueller 0001, Shing-Tung Yau |
Uniform texture synthesis and texture mapping using global parameterization. |
Vis. Comput. |
2005 |
DBLP DOI BibTeX RDF |
Global conformal parameterization, Texture mapping, Texture synthesis, Riemann surfaces |
26 | Tomasz S. Czajkowski, Jonathan Rose |
A synthesis oriented omniscient manual editor. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
virtex-e, synthesis, manual |
26 | Martin Lukac, Marek A. Perkowski, Hilton Goi, Mikhail Pivtoraiko, Chung Hyo Yu, Kyusik Chung, Hyunkoo Jeech, Byung-Guk Kim, Yong Duk Kim |
Evolutionary Approach to Quantum and Reversible Circuits Synthesis. |
Artif. Intell. Rev. |
2003 |
DBLP DOI BibTeX RDF |
minimizing transformation, Quantum CAD, Quantum Logic Synthesis, genetic algorithm |
26 | Yiu-Hing Chan, Prabhakar Kudva, Lisa B. Lacey, Gregory A. Northrop, Thomas E. Rosser |
Physical synthesis methodology for high performance microprocessors. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
synthesis, microprocessors, high-performance |
26 | Xin Tong 0001, Jingdan Zhang, Ligang Liu, Xi Wang, Baining Guo, Heung-Yeung Shum |
Synthesis of bidirectional texture functions on arbitrary surfaces. |
ACM Trans. Graph. |
2002 |
DBLP DOI BibTeX RDF |
3D textons, texture mapping, texture synthesis, surfaces, bidirectional texture function, reflectance and shading models |
26 | Vijay Raghunathan, Anand Raghunathan, Mani B. Srivastava, Milos D. Ercegovac |
High-Level Synthesis with SIMD Units. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
SIMD functional units, High-level synthesis, high performance design |
26 | Robert Siegmund, Dietmar Müller 0001 |
A novel synthesis technique for communication controller hardware from declarative data communication protocol specifications. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
controller hardware synthesis, interface-based design, protocol specification |
26 | Alvin J. Surkan |
Spoken-word direction of computer program synthesis. |
APL |
2000 |
DBLP DOI BibTeX RDF |
chatting in context, computer program synthesis, constructive composition of functional programs, incremental verbal software specification, spoken computer commands, talking with computers, voice computing, voice-directed programming, APL, human-computer interface |
26 | Bernd Fischer 0002, Jon Whittle 0001 |
An Integration of Deductive Retrieval into Deductive Synthesis. |
ASE |
1999 |
DBLP DOI BibTeX RDF |
deductive retrieval, software engineering, software reuse, program synthesis |
26 | Pao-Ann Hsiung, Chung-Hwang Chen, Trong-Yen Lee, Sao-Jie Chen |
ICOS: an intelligent concurrent object-oriented synthesis methodology for multiprocessor systems. |
ACM Trans. Design Autom. Electr. Syst. |
1998 |
DBLP DOI BibTeX RDF |
concurrent object-oriented system-level synthesis, fuzzy design-space exploration, learning |
26 | Youn-Long Lin |
Recent developments in high-level synthesis. |
ACM Trans. Design Autom. Electr. Syst. |
1997 |
DBLP DOI BibTeX RDF |
high level synthesis, design methodology, VLSI design, design automation |
26 | Premal Buch, Amit Narayan, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli |
Logic synthesis for large pass transistor circuits. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
logic synthesis, BDD, Pass transistor logic |
26 | Pao-Ann Hsiung, Trong-Yen Lee, Sao-Jie Chen |
Object-Oriented Technology Transfer to Multiprocessor System-Level Synthesis. |
TOOLS (24) |
1997 |
DBLP DOI BibTeX RDF |
Learning, Synthesis, Object-Oriented Modeling, Design Management |
26 | Anand Raghunathan, Niraj K. Jha |
An iterative improvement algorithm for low power data path synthesis. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
Low power VLSI design, Power consumption, Behavioral synthesis |
26 | Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose |
Logic synthesis for a single large look-up table. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
single large look-up table, LUT-based field-programmable gate array architectures, simulation time minimisation, compile-code, software simulation, field programmable gate arrays, Boolean function, logic design, logic synthesis, hardware accelerator, programmable logic arrays, table lookup, logic simulation, FPGA architectures, logic functions, on-chip memory, memory constraint |
26 | Daniel Y. Chao, David T. Wang |
A synthesis technique of general petri nets. |
J. Syst. Integr. |
1994 |
DBLP DOI BibTeX RDF |
ordinary Petri nets, general Petri nets, liveness boundedness, structural relationship, synthesis, rule, deadlock, Concurrent system, reversible, flexible manufacturing system |
26 | Ajoy Kumar Datta, Sukumar Ghosh |
Modular Synthesis of Deadlock-Free Control Structures. |
FSTTCS |
1986 |
DBLP DOI BibTeX RDF |
regular nets, Petri nets, synthesis, deadlock |
26 | Yexin Zheng, Chao Huang |
A novel Toffoli network synthesis algorithm for reversible logic. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Lech Józwiak, Szymon Bieganski |
Technology Library Modelling for Information-driven Circuit Synthesis. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Mehdi Saeedi, Naser MohammadZadeh, Mehdi Sedighi, Morteza Saheb Zamani |
Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Alan Mishchenko, Michael L. Case, Robert K. Brayton, Stephen Jang |
Scalable and scalably-verifiable sequential synthesis. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Leevi Peltola, Cumhur Erkut, Perry R. Cook, Vesa Välimäki |
Synthesis of Hand Clapping Sounds. |
IEEE Trans. Speech Audio Process. |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Patrick Ndjiki-Nya, Christoph Stüber, Thomas Wiegand |
Texture Synthesis Method for Generic Video Sequences. |
ICIP (3) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Sven Schewe, Bernd Finkbeiner |
Bounded Synthesis. |
ATVA |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Vyas Krishnan, Srinivas Katkoori |
A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Tao Xu 0002, Krishnendu Chakrabarty |
Integrated Droplet Routing in the Synthesis of Microfluidic Biochips. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Nagarajan Ranganathan, Ravi Namballa, Narender Hanchate |
CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL. |
ISVLSI |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Wen-hui Li, Meng Yu, Zhen-hua Zhang, Dong-fei Liu, Jian-yuan Wang |
A Fast Temporal Texture Synthesis Algorithm Using Segment Genetic Algorithm. |
ISMIS |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Jia-Wei Chiou, Chuan-Kai Yang |
A New Algorithm for Solid Texture Synthesis. |
ISVC (2) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Jae-Jin Lee, Gi-Yong Song |
High-Level Synthesis Using SPARK and Systolic Array. |
ARC |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Tsung-Hsi Chiang, Lan-Rong Dung |
System-level verification on high-level synthesis of dataflow graph. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Rui Zhang, Pallav Gupta, Lin Zhong 0001, Niraj K. Jha |
Threshold network synthesis and optimization and its application to nanotechnologies. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Lech Józwiak, Szymon Bieganski |
High-quality Sub-function Construction in the Information-driven Circuit Synthesis with Gates. |
DSD |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Keoncheol Shin, Taewhan Kim |
An integrated approach to timing-driven synthesis and placement of arithmetic circuits. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Sebastián Uchitel, Jeff Kramer, Jeff Magee |
Synthesis of Behavioral Models from Scenarios. |
IEEE Trans. Software Eng. |
2003 |
DBLP DOI BibTeX RDF |
scenario-based specification, sequence chart combination, requirements analysis, Requirements specification, Message Sequence Charts |
26 | Ravi Varadarajan |
Convergence of placement technology in physical synthesis: is placement really a point tool? |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang |
Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Josep Carmona 0001, Jordi Cortadella, Enric Pastor |
Synthesis of Reactive Systems: Application to Asynchronous Circuit Design. |
Concurrency and Hardware Design |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Loïs Guiller, Frederic Neuveux, S. Duggirala, R. Chandramouli, Rohit Kapur |
Integrating DFT in the Physical Synthesis Flow. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Petr Motlícek, Geneviève Baudoin, Jan Cernocký, Gérard Chollet |
Minimization of Transition Noise and HNM Synthesis in Very Low Bit Rate Speech Coding. |
TSD |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Montek Singh, Steven M. Nowick |
Synthesis for logical initializability of synchronous finite-state machines. |
IEEE Trans. Very Large Scale Integr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Tamal Mukherjee, L. Richard Carley, Rob A. Rutenbar |
Efficient handling of operating range and manufacturing linevariations in analog cell synthesis. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Manas Saksena, Panagiota Karvelas, Yun Wang |
Automatic Synthesis of Multi-Tasking Implementations from Real-Time Object-Oriented Models. |
ISORC |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Orna Kupferman, Moshe Y. Vardi |
µ-Calculus Synthesis. |
MFCS |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Wander O. Cesário, Ahmed Amine Jerraya, Zoltan Sugar, Imed Moussa |
Rethinking Behavioral Synthesis for a Better Integration within Existing Design Flows. |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Darko Kirovski, Chunho Lee, Miodrag Potkonjak, William H. Mangione-Smith |
Application-driven synthesis of memory-intensive systems-on-chip. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Ganesh Lakshminarayana, Niraj K. Jha |
High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Abhijit Ghosh, Joachim Kunkel, Stan Y. Liao |
Hardware Synthesis from C/C++. |
DATE |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Ganesh Lakshminarayana, Niraj K. Jha |
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
transceiver, spread spectrum communication, RF CMOS, digital radio, ISM frequency band |
26 | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1997 |
DBLP DOI BibTeX RDF |
|
26 | Sandeep Bhatia, Niraj K. Jha |
Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1996 |
DBLP DOI BibTeX RDF |
|
26 | Giovanni De Micheli, David C. Ku |
HERCULES - a System for High-Level Synthesis. |
DAC |
1988 |
DBLP BibTeX RDF |
|
25 | Sujit Dey, Anand Raghunathan, Kenneth D. Wagner |
Design for Testability Techniques at the Behavioral and Register-Transfer Levels. |
J. Electron. Test. |
1998 |
DBLP DOI BibTeX RDF |
behavioral synthesis for testability, behavioral synthesis for BIST, high-level test generation, RTL synthesis for testability, design for testability |
25 | Huy Nguyen 0001, Abhijit Chatterjee |
OPTIMUS: a new program for OPTIMizing linear circuits with number-splitting and shift-and-add decompositions. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
linear network synthesis, OPTIMUS program, linear circuits, shift-and-add decomposition, behavioral synthesis tool, architectural transformations, numerical matrix transformation algorithms, number-splitting transformation, optimization, high level synthesis, multiplications, circuit CAD, circuit optimisation, matrix decomposition |
25 | Jay K. Adams, Donald E. Thomas |
Multiple-process behavioral synthesis for mixed hardware-software systems. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
automated iterative improvement technique, concurrency optimization, concurrency tradeoffs, cost/performance ratio, hardware-software tradeoffs, mixed hardware-software systems, multiple-process behavioral synthesis, software engineering, resource allocation, concurrency control, controllers, optimisation, high level synthesis, logic design, multiprocessing systems, microprocessors, ASICs, application specific integrated circuits, ASIC, microprocessor chips, cost-benefit analysis |
25 | Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man |
Synthesis of pipelined DSP accelerators with dynamic scheduling. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
DSP algorithms, FFT butterfly accelerator block, application specific DSP accelerators, highly pipelined data paths, pipelined DSP accelerator synthesis, pipelined bit-parallel hardware, silicon, scheduling, parallel architectures, application specific integrated circuits, dynamic scheduling, pipeline processing, circuit CAD, digital signal processing chips, datapath, controller architecture, network synthesis, run-time schedules |
25 | Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt, Min Xu |
A comprehensive estimation technique for high-level synthesis. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
HLS benchmarks, RT level components, RTL datapaths, estimation technique, delays, high level synthesis, high-level synthesis, timing, design space exploration, granularity, hardware description languages, data flow graphs, registers, system buses, timing model, buses, behavioral description, layout area |
25 | Krzysztof Kuchcinski |
Constraints-driven scheduling and resource assignment. |
ACM Trans. Design Autom. Electr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
scheduling, high-level synthesis, Constraint programming, system-level synthesis, resource assignment |
24 | Luis A. Plana, Doug A. Edwards, Sam Taylor, Luis A. Tarazona, Andrew Bardsley |
Performance-driven syntax-directed synthesis of asynchronous processors. |
CASES |
2007 |
DBLP DOI BibTeX RDF |
handshake components, syntax-directed synthesis, asynchronous circuits |
24 | Miljan Vuletic, Christophe Dubach, Laura Pozzi, Paolo Ienne |
Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines. |
CODES+ISSS |
2005 |
DBLP DOI BibTeX RDF |
virtual machine, synthesis, accelerator |
24 | Gwenolé Corre, Eric Senn, Pierre Bomel, Nathalie Julien, Eric Martin 0001 |
Memory accesses management during high level synthesis. |
CODES+ISSS |
2004 |
DBLP DOI BibTeX RDF |
memory aware, behavioral synthesis |
24 | Hyunuk Jung, Soonhoi Ha |
Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis. |
CODES+ISSS |
2004 |
DBLP DOI BibTeX RDF |
automatic hardware synthesis, VHDL, system level design, dataflow graph(DFG), HW/SW codesign |
24 | Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar |
An efficient technique for exploring register file size in ASIP synthesis. |
CASES |
2002 |
DBLP DOI BibTeX RDF |
ASIP Synthesis, retargetable estimation, storage exploration, design space exploration, instruction scheduling, register file, global analysis, register spill, liveness analysis |
24 | Johnny Öberg, Anshul Kumar, Ahmed Hemani |
Grammar-Based Hardware Synthesis of Data Communication Protocols. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
Grammar-based Specification, Data Communication Protocols, Design Space Exploration, Hardware Synthesis |
24 | Filip Thoen, Marco Cornero, Gert Goossens, Hugo De Man |
Real-time multi-tasking in software synthesis for information processing systems. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
automatic processor mapping, automatically generated application-specific solution, concurrent process system specification, flexible execution models, hardware resource utilization, information processing systems, internal representation model, mobile satellite communication, personal terminal receiver demodulator, real-time multi-tasking, static information, time utilization, real-time systems, embedded systems, concurrency control, processor scheduling, timing constraints, computer aided software engineering, software synthesis, multiprocessing programs |
24 | Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid |
Techniques for synthesizing binaries to an advanced register/memory structure. |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
smart buffers, FPGA, embedded systems, synthesis, decompilation, binaries |
24 | Hajime Shibata, Adrian Stoica, Nobuo Fujii |
Controllable decoding for automated analog circuit structure design. |
Soft Comput. |
2004 |
DBLP DOI BibTeX RDF |
Automated circuit synthesis, Genetic algorithm, Analog circuit |
24 | Narendra V. Shenoy, Mahesh A. Iyer, Robert F. Damiano, Kevin Harer, Hi-Keung Tony Ma, Paul Thilking |
A Robust Solution to the Timing Convergence Problem in High-Performance Design. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
timing convergence, maximum capacitance, synthesis, placement, design-rules |
24 | Ralph H. J. M. Otten, Robert K. Brayton |
Planning for Performance. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
high-level synthesis, telecommunication |
24 | David Haigh, Fang Qun Tan, Christos Papavassiliou |
Systematic synthesis method for analogue circuits. Part II. Active-RC circuit synthesis. |
ISCAS (1) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Christian Blumenröhr, Dirk Eisenbiegler |
An Efficient Representation for Formal Synthesis. |
ISSS |
1997 |
DBLP DOI BibTeX RDF |
|
24 | Yonghong Yang, Zhenyu (Peter) Gu, Changyun Zhu, Robert P. Dick, Li Shang |
ISAC: Integrated Space-and-Time-Adaptive Chip-Package Thermal Analysis. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Sandeep S. Kulkarni, Ali Ebnenasir |
Adding Fault-Tolerance Using Pre-synthesized Components. |
EDCC |
2005 |
DBLP DOI BibTeX RDF |
Formal methods, Distributed programs, Detectors, Correctors, Automatic addition of fault-tolerance |
23 | Xijin Tang 0001 |
Qualitative Meta-synthesis Techniques for Analysis of Public Opinions for in-depth Study. |
Complex (2) |
2009 |
DBLP DOI BibTeX RDF |
qualitative meta-synthesis, CorMap, iView, meta-synthesis, word association |
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