Search results for "circuit"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
20	Mark C. Hansen, John P. Hayes	High-level test generation using physically-induced faults.	VTS	1995	DBLP DOI BibTeX RDF	high-level test generation, physically-induced faults, industry-standard single stuck-line faults, independent functional faults, near-minimal size, fault diagnosis, logic testing, integrated circuit testing, design for testability, automatic testing, functional tests, failure analysis, benchmark circuits, circuit under test
20	Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel	Cyclic stress tests for full scan circuits.	VTS	1995	DBLP DOI BibTeX RDF	cyclic stress tests, fully testable unpackaged dies, burn-in process, cyclic input sequences, stress related problems, ISCAS89 benchmark circuits, monitored burn-in problems, IC reliability, VLSI, VLSI, logic testing, integrated circuit testing, CMOS, CMOS logic circuits, boundary scan testing, MCMs, integrated circuit reliability, full scan circuits
20	Russell J. Clark 0001, Ronald R. Hutchins	Deploying ATM in a data network: an analysis of SVC requirements.	LCN	1995	DBLP DOI BibTeX RDF	telecommunication traffic recording, telecommunication switching, campus data networks, SVC requirements, connectionless network layer protocols, connection-oriented service, call setups, concurrent SVCs, large campus networks, circuit-based network, networking requirements, college campus, IP traffic logs, ATM deployment scenarios, circuit replacement algorithms, SVC setup rates, hold times, switched virtual circuits, asynchronous transfer mode, ATM, local area networks, IP, educational technology, ATM switches, educational computing, data network
20	Gloria Kissin	Upper and Lower Bounds on Switching Energy in VLSI.	J. ACM	1991	DBLP DOI BibTeX RDF	1-switchable functions, AND function, CID VLSI circuit, OR functions, USM, circuit scheme, compare functions, parity function, switching energy, uniswitch, energy-efficient, embedding, energy consumption, layout, average-case analysis, addition, upper and lower bounds
20	David W. Capson, Sai-Kit Eng	A Tiered-Color Illumination Approach for Machine Inspection of Solder Joints.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	PCB inspection, tiered-color illumination, machine inspection, solder joints, color contours, colour vision, printed circuit manufacture, soldering, computer vision, statistical analysis, computerised pattern recognition, computerised pattern recognition, inspection, binary image, printed circuit boards, color vision, flaw detection
20	Cosmin Radu Popa	A New FGMOST Euclidean Distance Computational Circuit Based on Algebraic Mean of the Input Potentials.	ICANN (1)	2009	DBLP DOI BibTeX RDF	Computational circuits, FGMOST, VLSI design
20	Lech Józwiak, Szymon Bieganski	Technology Library Modelling for Information-driven Circuit Synthesis.	DSD	2008	DBLP DOI BibTeX RDF
20	Woonki Na, Bei Gou	A thermal equivalent circuit for PEM fuel cell temperature control design.	ISCAS	2008	DBLP DOI BibTeX RDF
20	Bas M. Putter	On-chip RC measurement and calibration circuit using Wheatstone bridge.	ISCAS	2008	DBLP DOI BibTeX RDF
20	Nathan O. Scott, Gerhard W. Dueck	Pairwise decomposition of toffoli gates in a quantum circuit.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	elementary quantum gates, synthesis, minimization, reversible logic, quantum circuits
20	Abhisek Pan, James W. Tschanz, Sandip Kundu	A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic Circuit.	DFT	2008	DBLP DOI BibTeX RDF
20	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy 0001	Low-Power and testable circuit synthesis using Shannon decomposition.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Shannon expansion, dynamic supply gating, test coverage, Design-for-test, IDDQ, noise immunity, test power
20	Eva Sciacca, Salvatore Spinella, Angelo Marcello Anile	Possibilistic Worst Case Distance and Applications to Circuit Sizing.	IFSA (2)	2007	DBLP DOI BibTeX RDF
20	Il Song Han	Membership Function Circuit for Neural/Fuzzy Hardware of Analog-Mixed Operation Based on the Programmable Conductance.	FUZZ-IEEE	2007	DBLP DOI BibTeX RDF
20	Lukas Dolivka, Jirí Hospodka	Using deferential evolution algorithm for the multi-objective optimization of a switched-current circuit.	IEEE Congress on Evolutionary Computation	2007	DBLP DOI BibTeX RDF
20	Huifei Rao, Jie Chen 0002, Changhong Yu, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu, Hong Zhao	Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design.	ISCAS	2007	DBLP DOI BibTeX RDF
20	Daniel Bernhard Fasnacht, Tobi Delbrück	Dichromatic spectral measurement circuit in vanilla CMOS.	ISCAS	2007	DBLP DOI BibTeX RDF
20	Subhasish Mitra	Circuit Failure Prediction Enables Robust System Design Resilient to Aging and Wearout.	IOLTS	2007	DBLP DOI BibTeX RDF
20	Alan Rosen, Daniel Rosen	A Robotic Optical Circuit that Generates a 3D-visual Image: Solution to the inverse optics problem for robotic visual seeing by reverse engineering the neurophysiology of the modalities of the retinal receptors.	IJCNN	2007	DBLP DOI BibTeX RDF
20	Mridul Agarwal, Bipul C. Paul, Ming Zhang, Subhasish Mitra	Circuit Failure Prediction and Its Application to Transistor Aging.	VTS	2007	DBLP DOI BibTeX RDF
20	Kunhyuk Kang, Keejong Kim, Kaushik Roy 0001	Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop.	DAC	2007	DBLP DOI BibTeX RDF
20	Jae-Joon Kim, Kaushik Roy 0001	A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-on-Insulator CMOS Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
20	Toshihiro Katashita, Atusi Maeda, Kenji Toda, Yoshinori Yamaguchi	A Method of Generating Highly Efficient String Matching Circuit for Intrusion Detection.	FPL	2006	DBLP DOI BibTeX RDF
20	Pan Zhongliang, Chen Ling, Liu Shouqiang, Guangzhao Zhang	Neural Network Approach for Multiple Fault Test of Digital Circuit.	ISDA (3)	2006	DBLP DOI BibTeX RDF
20	Benjamas Tongprasit, Tadashi Shibata	Power-balanced reconfigurable floating-gate-MOS logic circuit for tamper resistant VLSI.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Volkan Kursun, Zhiyu Liu	Wide temperature spectrum low leakage dynamic circuit technique for sub-65nm CMOS technologies.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Alex K. Y. Wong, Kong-Pang Pun, Yuan-Ting Zhang, Oliver Chiu-sing Choy	An ECG measurement IC using driven-right-leg circuit.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Sanjay Kumar Wadhwa, G. K. Siddhartha, Anand Gaurav	Zero Steady State Current Power on Reset Circuit with Brown-Out Detector.	VLSI Design	2006	DBLP DOI BibTeX RDF
20	Ruei-Jhe Tsai, Hsin-Wen Ting, Chi-Sheng Lin, Bin-Da Liu	A CAM/WTA-Based High Speed and Low Power Longest Prefix Matching Circuit Design.	APCCAS	2006	DBLP DOI BibTeX RDF
20	Zhongyuan Zhang, Fangcheng Lu, Yutong Chen	A High Frequency Circuit Model for Current Transformer Based on the Scattering Parameter.	APCCAS	2006	DBLP DOI BibTeX RDF
20	Daisuke Atuti, Takashi Morie, Kazuyuki Aihara	A Current-Sampling-Mode Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach Driven by Quantized Nonlinear Waveforms.	APCCAS	2006	DBLP DOI BibTeX RDF
20	Mohammad Reza Jahed-Motlagh, Behnam Kia	Chua Circuit Based Reconfigurable Computing System.	APCCAS	2006	DBLP DOI BibTeX RDF
20	Hao Yu 0001, Lei He 0001, Zhenyu Qi, Sheldon X.-D. Tan	A wideband hierarchical circuit reduction for massively coupled interconnects.	ASP-DAC	2005	DBLP DOI BibTeX RDF
20	Bo Hu, Zhao Li, Lili Zhou, C.-J. Richard Shi, Kwang-Hyun Baek, Myung-Jun Choe	Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
20	Takahide Sato, Shigetaka Takagi, Nobuo Fujii, Yasuyuki Hashimoto, Kohji Sakata, Hiroyuki Okada	Feedforward-type parasitic capacitance canceler and its application to 4 Gb/s T/H circuit.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
20	Shubhajit Roy Chowdhury, C. Pramanik, Hiranmay Saha	ASIC Design of the Linearisation Circuit of a PTC Thermistor.	VLSI Design	2005	DBLP DOI BibTeX RDF
20	Dong Xiang, Janak H. Patel	Partial Scan Design Based on Circuit State Information and Functional Analysis.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Valid state, invalid state, testability improvement potential, conflict, testability measure, partial scan design
20	Loc Vu-Quoc, Yuhu Zhai, Khai D. T. Ngo	Efficient simulation of coupled circuit-field problems: generalized Falk method.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
20	Görschwin Fey, Junhao Shi, Rolf Drechsler	BDD Circuit Optimization for Path Delay Fault Testability.	DSD	2004	DBLP DOI BibTeX RDF
20	Lech Józwiak, Szymon Bieganski	Information Trans-Coders in Information-Driven Circuit Synthesis.	DSD	2004	DBLP DOI BibTeX RDF
20	Guanghui Li 0001, Xiaowei Li 0001	Circuit-Width Based Heuristic for Boolean Reasoning.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
20	Yehya H. Ghallab, Wael M. Badawy	A Novel pH Sensor Current Mode Read-Out Circuit Using Operational Floating Current Conveyor.	ICMENS	2004	DBLP DOI BibTeX RDF	Chemical sensor, ISFET pH sensor, Differential ISFET, Operational Floating Current Conveyor, Current mode circuits
20	Raoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri	A high level language for pre-layout extraction in parasite-aware analog circuit synthesis.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	MSL, pre-layout extraction, parasitics, analog VLSI
20	Pavel V. Nikitin, Vikram Jandhyala, Daniel A. White, Nathan Champagne, John D. Rockway, C.-J. Richard Shi, Chuanyi Yang, Yong Wang 0006, Gong Ouyang, Rob Sharpe, John W. Rockway	Modeling and Simulation of Circuit-Electromagnetic Effects in Electronic Design Flow.	ISQED	2004	DBLP DOI BibTeX RDF
20	Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada	A Power Supply Circuit Recycling Charge in Adiabatic Dynamic CMOS Logic Circuits.	DELTA	2004	DBLP DOI BibTeX RDF
20	Ganesh Kothapalli	Excitation Modes and Transient Response of a Winner-take-all Circuit.	DELTA	2004	DBLP DOI BibTeX RDF
20	Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell	CMOS Circuit Design for Minimum Dynamic Power and Highest Speed.	VLSI Design	2004	DBLP DOI BibTeX RDF
20	D. Satyanarayana, Santanu Chattopadhyay, Jakki Sasidhar	Low Power Combinational Circuit Synthesis targeting Multiplexer based FPGAs.	VLSI Design	2004	DBLP DOI BibTeX RDF
20	Vidyasagar Nookala, Sachin S. Sapatnekar	A method for correcting the functionality of a wire-pipelined circuit.	DAC	2004	DBLP DOI BibTeX RDF	synchronous design, wire pipelining
20	O'tega Ejofodomi, Shani E. Ross, Ahmed Jendoubi, Mohamed F. Chouikha, Jianchao Zeng 0002	Online Handwritten Circuit Recognition on a Tablet PC.	AIPR	2004	DBLP DOI BibTeX RDF
20	Yu-Liang Wu, Chak-Chung Cheung, David Ihsin Cheng, Hongbing Fan	Further improve circuit partitioning using GBAW logic perturbation techniques.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
20	Hafiz Md. Hasan Babu, Md. Rafiqul Islam 0001, Ahsan Raja Chowdhury, Syed Mostahed Ali Chowdhury	Reversible Logic Synthesis for Minimization of Full-Adder Circuit.	DSD	2003	DBLP DOI BibTeX RDF
20	Minoru Watanabe, Fuminori Kobayashi	An Optically Differential Reconfigurable Gate Array with a Dynamic Reconfiguration Circuit.	IPDPS	2003	DBLP DOI BibTeX RDF
20	Hidehiro Nakano, Keita Miyachi, Toshimichi Saito	A simple nonautonomous chaotic circuit with a periodic pulse-train input.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
20	Alan A. Stocker	Compact integrated transconductance amplifier circuit for temporal differentiation.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
20	Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell	Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program.	VLSI Design	2003	DBLP DOI BibTeX RDF
20	Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen	Circuit simplification for the symbolic analysis of analogintegrated circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
20	Shuichi Ichikawa, Shoji Yamamoto	Data Dependent Circuit for Subgraph Isomorphism Problem.	FPL	2002	DBLP DOI BibTeX RDF
20	Tetsuya Uemura, Pinaki Mazumder	Rise time analysis of MOBILE circuit.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
20	Seong-Kweon Kim, Shigehito Saigusa, Suguru Kameda, Hiroyuki Nakase, Kazuo Tsubouchi	New current attenuator circuit in the current mode FFT LSI for OFDM.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
20	Chun-Hung Chen, Karen Donohue, Jianwu Lin, Enver Yücesan	Efficient Approach for Monte Carlo Simulation Experiments and Its Applications to Circuit Systems Design.	Annual Simulation Symposium	2001	DBLP DOI BibTeX RDF
20	Ming-Dou Ker, Tung-Yang Chen	Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
20	Benjamin Becker, George J. Cokkinides, Michael Sechrest	Field, Circuit, and Visualization Based Simulation Methodology for Passive Electronic Components.	Annual Simulation Symposium	2000	DBLP DOI BibTeX RDF
20	Yuji Kasai, Hidenori Sakanashi, Masahiro Murakawa, Shogo Kiryu, Neil Marston, Tetsuya Higuchi	Initial Evaluation of an Evolvable Microwave Circuit.	ICES	2000	DBLP DOI BibTeX RDF
20	Vitalij Ocheretnij, Michael Gössel, Vladimir V. Saposhnikov, Valerij V. Saposhnikov	A New Method of Redundancy Addition for Circuit Optimization.	EUROMICRO	2000	DBLP DOI BibTeX RDF
20	Manish Sharma, Janak H. Patel	Bounding Circuit Delay by Testing a Very Small Subset of Paths.	VTS	2000	DBLP DOI BibTeX RDF	Linear relations between path delays, Basis path set, Delay fault testing
20	Adrián Núñez-Aldana, Ranga Vemuri	An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis.	DATE	1999	DBLP DOI BibTeX RDF
20	Sung Dae Lee, Myungjun Jang, Won Hyo Lee	An On-Chip Automatic Tuning Circuit using Integration Level Approximation.	ASP-DAC	1999	DBLP DOI BibTeX RDF
20	Spiridon Vlassis, Stilianos Siskos	High speed and high resolution WTA circuit.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
20	D. B. LaFontaine	Full duplex transhybrid circuit for voice communications through a single crosspoint.	ISCAS (4)	1999	DBLP DOI BibTeX RDF
20	Ramakrishna Voorakaranam, Abhijit Chatterjee	Feedback Driven Backtrace of Analog Signals and its Application to Circuit Verification and Test.	ARVLSI	1999	DBLP DOI BibTeX RDF	analog verification, fault diagnosis, test generation, analog testing, Backtrace
20	Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah, Chai Wah Wu	JiffyTune: circuit optimization using time-domain sensitivities.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
20	Kazuyuki Amano, Akira Maruoka	A Superpolynomial Lower Bound for a Circuit Computing the Clique Function with At Most (1/6) log log n Negation Gates.	MFCS	1998	DBLP DOI BibTeX RDF
20	Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj	Timing and area optimization for standard-cell VLSI circuit design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
20	Jun Gu, Ruchir Puri	Asynchronous circuit synthesis with Boolean satisfiability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
20	Curtis L. Ratzlaff, Lawrence T. Pillage	RICE: rapid interconnect circuit evaluation using AWE.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
20	Wing Ning Li, Andrew Lim 0001, Prathima Agrawal, Sartaj Sahni	On the circuit implementation problem.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
20	Krishna P. Belkhale, Prithviraj Banerjee	Parallel algorithms for VLSI circuit extraction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
20	Wen-Jeng Lue, Lawrence P. McNamee	Extracting Schematic-like Information from CMOS Circuit Net-lists.	DAC	1989	DBLP DOI BibTeX RDF
20	Donald M. Webber, Alberto L. Sangiovanni-Vincentelli	Circuit Simulation on the Connection Machine.	DAC	1987	DBLP DOI BibTeX RDF
19	Mei Xue, Jingsong He	A Circuit Generating Mechanism with Evolutionary Programming for Improving the Diversity of Circuit Topology in Population-Based Analog Circuit Design.	ICSI (1)	2013	DBLP DOI BibTeX RDF
19	Recai Kiliç	Chaos Synchronization in SC-CNN-Based Circuit and an Interesting Investigation: Can a SC-CNN-Based Circuit Behave Synchronously with the Original Chua's Circuit?	Int. J. Bifurc. Chaos	2004	DBLP DOI BibTeX RDF
19	Recai Kiliç	A Comparative Study on Realization of Chua's Circuit: Hybrid Realizations of Chua's Circuit Combining the Circuit Topologies Proposed for Chua's diode and inductor Elements.	Int. J. Bifurc. Chaos	2003	DBLP DOI BibTeX RDF
19	Jørgen Staunstrup, Stephen J. Garland, John V. Guttag	Mechanized Verification of Circuit Descriptions Using the Larch Prover.	TPCD	1992	DBLP BibTeX RDF
19	Paul B. Jackson	Nuprl and Its Use in Circuit Design.	TPCD	1992	DBLP BibTeX RDF
19	Jernej Olensek, Árpád Bürmen, Janez Puhan, Tadej Tuma	DESA: a new hybrid global optimization method and its application to analog integrated circuit sizing.	J. Glob. Optim.	2009	DBLP DOI BibTeX RDF	Analog integrated circuit sizing, Optimization, Simulated annealing, Differential evolution
19	Pedro Sousa, Carla Duarte, Nuno Horta	FUGA: a fuzzy-genetic analog circuit optimization kernel.	GECCO	2009	DBLP DOI BibTeX RDF	genetic algorithms, optimization, CAD, analog circuit, fuzzy model
19	Yan Li 0029, Vladimir Stojanovic	Yield-driven iterative robust circuit optimization algorithm.	DAC	2009	DBLP DOI BibTeX RDF	robust circuit optimization, variability, yield, analog circuits
19	Vladimir Kolesnikov, Thomas Schneider 0003	A Practical Universal Circuit Construction and Secure Evaluation of Private Functions.	Financial Cryptography	2008	DBLP DOI BibTeX RDF	SFE of private functions, universal circuit, privacy
19	Ci Lei, Dinesh Pamunuwa, Steven Bailey, Colin Lambert	Application of Molecular Electronics Devices in Digital Circuit Design.	NanoNet	2008	DBLP DOI BibTeX RDF	nanotechnology, circuit simulation, molecular electronics
19	Mithilesh Kumar 0002, Vineeta Chaube, Pavan Balaji, Wu-chun Feng, Hyun-Wook Jin	Making a Case for Proactive Flow Control in Optical Circuit-Switched Networks.	HiPC	2008	DBLP DOI BibTeX RDF	rate-based protocol, LambdaGrid, optical networks, circuit switched
19	Gustavo Wilke, Renan Fonseca, Cecilia Mezzomo, Ricardo Reis 0001	A novel scheme to reduce short-circuit power in mesh-based clock architectures.	SBCCI	2008	DBLP DOI BibTeX RDF	clock mesh, power, clock skew, short-circuit
19	Alodeep Sanyal, Sandip Kundu	A Built-in Test and Characterization Method for Circuit Marginality Related Failures.	ISQED	2008	DBLP DOI BibTeX RDF	Circuit Marginality, Pseudorandom Pattern Generator (PRPG), Multiple Input Signature Register (MISR), Fmax testing based on frequency shmoo, Built-In Self-Test (BIST), Design-for-Testability (DFT), Linear Feedback Shift Register (LFSR)
19	Charbel J. Akl, Magdy A. Bayoumi	Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family.	ISQED	2008	DBLP DOI BibTeX RDF	circuit family, low-power, high-speed
19	Hsin-Chou Chi, Chia-Ming Wu, Jun-Hui Lee	Integrated Mapping and Scheduling for Circuit-Switched Network-on-Chip Architectures.	DELTA	2008	DBLP DOI BibTeX RDF	network-on-chip architectures, scheduling, mapping, circuit-switched networks
19	Michal Koucký 0001	Circuit Complexity of Regular Languages.	CiE	2007	DBLP DOI BibTeX RDF	circuit complexity, regular languages
19	Mehmet Bayram Yildirim, Ekrem Duman, Dilek Duman	Dispatching Rules for Allocation of Component Types to Machines in the Automated Assembly of Printed Circuit Boards.	ISCIS	2006	DBLP DOI BibTeX RDF	Printed Circuit Board Assembly, Load Balancing, Heuristics
19	Farshad Safaei, Ahmad Khonsari, Mahmood Fathy, Mohamed Ould-Khaoua	Analysis of Circuit Switching for the Torus Interconnect Networks with Hot-Spot Traffic.	ICPP Workshops	2006	DBLP DOI BibTeX RDF	Hot-spot traffic, Queuing theory and Performance evaluation, Parallel computers, Interconnect networks, Torus, Circuit switching
19	Yvan Maidon, Thomas Zimmer, André Ivanov	An Analog Circuit Fault Characterization Methodology.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	analog circuit testing, analog fault diagnosis, analog fault characterization
19	Fengming Zhang, Rui Tang, Yong-Bin Kim	SET-based nano-circuit simulation and design method using HSPICE.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	SET circuit design, SET modeling, SET simulation with HSPICE