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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2225 occurrences of 1302 keywords
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Results
Found 4812 publication records. Showing 4812 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
17 | Aad P. A. van Moorsel, Yiqing Huang |
Reusable Software Components for Performability Tools and Their Utilization for Web-Based Configurable Tools. |
Computer Performance Evaluation (Tools) |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Wei-Kang Huang, M. Y. Zhang, Fred J. Meyer, Fabrizio Lombardi |
A XOR-Tree Based Technique for Constant Testability of Configurable FPGAs. |
Asian Test Symposium |
1997 |
DBLP DOI BibTeX RDF |
programmable system, diagnosis, FPGA testing, XOR |
17 | Seonil Choi, Viktor K. Prasanna, Yongwha Chung |
Configurable Hardware for Symbolic Search Operations. |
ICPADS |
1997 |
DBLP DOI BibTeX RDF |
|
17 | David Channon, David Koch |
Performance Analysis of Re-configurable Partitioned TLBs. |
HICSS (5) |
1997 |
DBLP DOI BibTeX RDF |
Computer Architecture, Memory Management, Partitioning Algorithm, Address Translation |
17 | Wei-Kang Huang, Fabrizio Lombardi |
An approach for testing programmable/configurable field programmable gate arrays. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
behavioral characterization, single fault detection, disjoint one-dimensional arrays, unilateral horizontal connections, common vertical input lines, array testing, logic blocks, field programmable gate arrays, field programmable gate arrays, VLSI, logic testing, integrated circuit testing, stuck-at fault, FPGA testing, functional fault, hybrid fault model |
17 | Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic |
Architecture of Centralized Field-Configurable Memory. |
FPGA |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Nina T. Bhatti, Richard D. Schlichting |
A System for Constructing Configurable High-Level Protocols. |
SIGCOMM |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Rick Amerson, Richard J. Carter, W. Bruce Culbertson, Philip Kuekes, Greg Snider |
Teramac-configurable custom computing. |
FCCM |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Alfred Strey, Narcís Avellana, Raul Holgado, Ramon Capillas, J. Alberto Fernández, Elena Valderrama |
A Configurable Parallel Neurocomputer. |
ANNES |
1995 |
DBLP DOI BibTeX RDF |
neural hardware, parallel computer, neurocomputer |
17 | Gordon J. Brebner |
Configurable array logic circuits for computing network error detection codes. |
J. VLSI Signal Process. |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Jeff Kramer, Anthony Finkelstein |
A Configurable Framework for Method and Tool Integration. |
Software Development Environments and CASE Technology |
1991 |
DBLP DOI BibTeX RDF |
|
17 | Tom Kean, John Gray |
Configurable hardware: Two case studies of micro-grain computation. |
J. VLSI Signal Process. |
1990 |
DBLP DOI BibTeX RDF |
|
15 | Krzysztof Kepa, Fearghal Morgan, Peter Athanas |
ERDB: An Embedded Routing Database for Reconfigurable Systems. |
FPL |
2011 |
DBLP DOI BibTeX RDF |
design integrity, security, FPGA, autonomic computing, partial reconfiguration, configurable systems |
15 | Wil M. P. van der Aalst |
Business Process Configuration in the Cloud: How to Support and Analyze Multi-tenant Processes? |
ECOWS |
2011 |
DBLP DOI BibTeX RDF |
configurable process models, cross-organizational process mining, causal nets, cloud computing |
15 | Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita |
High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only). |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
dopant-segregated schottky transistor, nonvolatile configurable memory |
15 | Roman L. Lysecky, Frank Vahid |
Design and implementation of a MicroBlaze-based warp processor. |
ACM Trans. Embed. Comput. Syst. |
2009 |
DBLP DOI BibTeX RDF |
soft processor cores, FPGA, dynamic optimization, hardware/software partitioning, configurable logic, Warp processors, just-in-time (JIT) compilation |
15 | André Stauffer, Joël Rossier |
Bio-inspired Self-Testing and Self-Organizing Bit Slice Processors. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
configurable molecule, cicatrization, test, configuration, regeneration |
15 | Michael P. Caffrey, Keith Morgan, Diane Roussel-Dupre, Scott Robinson, Anthony Nelson, Anthony Salazar, Michael J. Wirthlin, William Howes, Daniel Richins |
On-Orbit Flight Results from the Reconfigurable Cibola Flight Experiment Satellite (CFESat). |
FCCM |
2009 |
DBLP DOI BibTeX RDF |
FPGA, fault tolerant computing, configurable computing |
15 | Xiaohui Cheng, Yongjian Hu, Youmin Gong |
Design Methodology of Control System with Mutual Exclusion. |
PACIIA (2) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, Mutual Exclusion, Control System, Hardware/software Partition, Hardware/software Co-design, Configurable Logics |
15 | Jason Yu, Guy G. Lemieux, Christopher Eagleston |
Vector processing as a soft-core CPU accelerator. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
C2H, FPGA, configurable, embedded processor, application specific, soft processor, data-level parallelism |
15 | Antoine Gallais, Jean Carle |
Performance Evaluation and Enhancement of Surface Coverage Relay Protocol. |
Networking |
2008 |
DBLP DOI BibTeX RDF |
configurable localized algorithm, realistic physical layer, Wireless sensor networks, area coverage |
15 | Sean P. Sangster, John T. Blake |
Developing a reusable simulation model to improve access to diagnostic imaging clinics in Nova Scotia. |
SpringSim |
2008 |
DBLP DOI BibTeX RDF |
configurable simulation, diagnostic imaging, patient flow, reusable simulation, discrete event simulation |
15 | Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank Vahid |
A table-based method for single-pass cache optimization. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
configurable cache tuning, low energy, cache optimization |
15 | Juan A. Escalera, Manuel Ferre, Rafael Aracil, José Baca |
ROBMAT: Teleoperation of a Modular Robot for Collaborative Manipulation. |
KES (2) |
2007 |
DBLP DOI BibTeX RDF |
robot, Modular, teleoperation, self-configurable, human-interface |
15 | Nut Taesombut, Andrew A. Chien |
Evaluating the impacts of network information models on applications and network service providers. |
HPDC |
2007 |
DBLP DOI BibTeX RDF |
configurable optical network, lambda-grids, information model |
15 | Roman L. Lysecky, Greg Stitt, Frank Vahid |
Warp Processors. |
ACM Trans. Design Autom. Electr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
FPGA, dynamic optimization, hardware/software codesign, hardware/software partitioning, configurable logic, Warp processors, just-in-time (JIT) compilation |
15 | Arjen van Rhijn, Jurriaan D. Mulder |
Spatial input device structure and bimanual object manipulation in virtual environments. |
VRST |
2006 |
DBLP DOI BibTeX RDF |
configurable input device, multi-dimensional control, virtual reality, direct manipulation |
15 | Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers |
IEEE-Compliant IDCT on FPGA-Augmented TriMedia. |
J. VLSI Signal Process. |
2005 |
DBLP DOI BibTeX RDF |
inverse discrete cosine transform, field-programmable gate array, configurable computing, VLIW processor |
15 | Heidi E. Ziegler, Mary W. Hall |
Evaluating heuristics in automatically mapping multi-loop applications to FPGAs. |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
high-level and architectural synthesis, parallelizing compiler analysis techniques, synthesis techniques for configurable computing, FPGAs, pipelining, rapid prototyping, hardware design |
15 | Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan |
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation. |
FCCM |
2005 |
DBLP DOI BibTeX RDF |
standard hardware binary, FPGA, dynamic optimization, system-on-a-chip, platforms, codesign, hardware/software partitioning, configurable logic, Place and route, warp processors, just-in-time (JIT) compilation |
15 | Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry |
LAP: a logic activity packing methodology for leakage power-tolerant FPGAs. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
activity profile, basic logic elements (BLEs), configurable logic blocks (CLBs), sleep transistor (ST), sub-threshold leakage power, FPGA, packing |
15 | Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou |
A Low-Power Processor Architecture Optimized forWireless Devices. |
ASAP |
2005 |
DBLP DOI BibTeX RDF |
Pipeline depth, configurable pipeline, power-adaptive processors, Low power, asynchronous circuits |
15 | William D. Smith, Austars R. Schnore |
Towards an RCC-Based Accelerator for Computational Fluid Dynamics Applications. |
J. Supercomput. |
2004 |
DBLP DOI BibTeX RDF |
re-configurable computing applications, computational fluid dynamics |
15 | Joonseok Park, Pedro C. Diniz, K. R. Shesha Shayee |
Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
Performance analysis and modeling, loop transformations and high-level synthesis, Field-Programmable-Gate-Arrays (FPGAs), configurable computing |
15 | Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu 0001, Changkyu Kim, Jaehyuk Huh 0001, Nitya Ranganathan, Doug Burger, Stephen W. Keckler, Robert G. McDonald, Charles R. Moore |
TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP. |
ACM Trans. Archit. Code Optim. |
2004 |
DBLP DOI BibTeX RDF |
scalable and high-performance computing, Computer architecture, configurable computing |
15 | Andreas Dandalis, Viktor K. Prasanna |
An adaptive cryptographic engine for internet protocol security architectures. |
ACM Trans. Design Autom. Electr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
performance tradeoffs, reconfigurable components, cryptography, reconfigurable computing, AES, configurable, high performance, IPSec, reconfigurable systems, Adaptive computing |
15 | Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt |
Automatic Tuning of Two-Level Caches to Embedded Applications. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
cache exploration, embedded systems, low power, low energy, cache optimization, architecture tuning, cache hierarchy, Configurable cache |
15 | Timo Vogt, Norbert Wehn, Philippe Alves |
A multi-standard channel-decoder for base-station applications. |
SBCCI |
2004 |
DBLP DOI BibTeX RDF |
CDMA2k, convolutional decoder, hardware sharing, wireless, configurable, MAP, W-CDMA |
15 | Keith D. Underwood, K. Scott Hemmert |
Closing the Gap: CPU and FPGA Trends in Sustainable Floating-Point BLAS Performance. |
FCCM |
2004 |
DBLP DOI BibTeX RDF |
IEEE floating point, re-configurable computing, FPGA, arithmetic |
15 | Maya B. Gokhale, Christine Ahrens, Janette Frigo, Christophe Wolinski |
Communications Scheduling for Concurrent Processes on Reconfigurable Computers. |
FCCM |
2004 |
DBLP DOI BibTeX RDF |
Configurable System on a Chip, scheduling, FPGA, high level synthesis, reconfigurable computing, Cellular Array |
15 | Allen C. Cheng, Gary S. Tyson, Trevor N. Mudge |
FITS: framework-based instruction-set tuning synthesis for embedded application specific processors. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
16-bit ISA, instruction synthesis, low-power, energy efficient, embedded processor, reconfigurable processors, ASP, instruction encoding, configurable architecture, code density |
15 | Kiran Puttegowda, David I. Lehn, Jae H. Park, Peter M. Athanas, Mark T. Jones |
Context Switching in a Run-Time Reconfigurable System. |
J. Supercomput. |
2003 |
DBLP DOI BibTeX RDF |
virtual hardware, FPGA, run-time reconfiguration, configurable computing, context switching, multi-context |
15 | Jack Liu, Fred C. Chow, Timothy Kong, Rupan Roy |
Variable Instruction Set Architecture and Its Compiler Support. |
IEEE Trans. Computers |
2003 |
DBLP DOI BibTeX RDF |
Configurable code generation, variable instruction set, embedded processor, instruction scheduling, dictionary, enumeration, program representation, resource modeling |
15 | David Goodwin, Darin Petkov |
Automatic generation of application specific processors. |
CASES |
2003 |
DBLP DOI BibTeX RDF |
automatic instruction-set generation, ASIPs, configurable processors, extensible processors |
15 | Chuanjun Zhang, Frank Vahid |
Cache Configuration Exploration on Prototyping Platforms. |
IEEE International Workshop on Rapid System Prototyping |
2003 |
DBLP DOI BibTeX RDF |
embedded systems, low power, memory hierarchy, low energy, architecture tuning, Configurable cache, system-level exploration |
15 | Heidi E. Ziegler, Mary W. Hall, Pedro C. Diniz |
Compiler-generated communication for pipelined FPGA applications. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
high-level and architectural synthesis, parallelizing compiler analysis techniques, synthesis techniques for configurable computing, FPGAs, pipelining, rapid prototyping |
15 | Keith D. Cooper, Devika Subramanian, Linda Torczon |
Adaptive Optimizing Compilers for the 21st Century. |
J. Supercomput. |
2002 |
DBLP DOI BibTeX RDF |
configurable compilers, order of optimization, biased random search, optimizing compilers |
15 | Andreas Dandalis, Viktor K. Prasanna |
Run-time performance optimization of an FPGA-based deduction engine for SAT solvers. |
ACM Trans. Design Autom. Electr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
reconfigurable components, reconfigurable computing, configurable, high performance, Boolean satisfiability, reconfigurable systems, Adaptive computing, performance trade-offs |
15 | Jack Liu, Timothy Kong, Fred C. Chow |
Effective Compilation Support for Variable Instruction Set Architecture. |
IEEE PACT |
2002 |
DBLP DOI BibTeX RDF |
configurable code generation, variable instruction set, embedded processor, instruction scheduling, dictionary, enumeration, program representation, resource modeling |
15 | Owen G. McGrath |
Building an instructional portal: channeling the writing lab. |
SIGUCCS |
2002 |
DBLP DOI BibTeX RDF |
general presentation layer, instructional portal, on-line writing lab (OWL), user-configurable interfaces, channels |
15 | Jack Liu, Fred C. Chow |
A near-optimal instruction scheduler for a tightly constrained, variable instruction set embedded processor. |
CASES |
2002 |
DBLP DOI BibTeX RDF |
configurable code generation, variable instruction set, embedded processor, instruction scheduling, dictionary, enumeration, program representation, resource modeling |
15 | Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg |
A case for dynamic pipeline scaling. |
CASES |
2002 |
DBLP DOI BibTeX RDF |
configurable pipeline, fetch gating, power and energy management, shallow and deep pipelines, variable-depth pipeline, dynamic voltage scaling, clock gating |
15 | Dannie Lau, Aaron Schneider, Milos D. Ercegovac, John D. Villasenor |
A FPGA-based Library for On-Line Signal Processing. |
J. VLSI Signal Process. |
2001 |
DBLP DOI BibTeX RDF |
FFT, DSP, DCT, configurable computing, on-line arithmetic |
15 | Peter Bellows, Brad L. Hutchings |
Designing Run-Time Reconfigurable Systems with JHDL. |
J. VLSI Signal Process. |
2001 |
DBLP DOI BibTeX RDF |
FPGAs, image processing, CAD, configurable computing |
15 | Janette Frigo, Maya B. Gokhale, Dominique Lavenier |
Evaluation of the streams-C C-to-FPGA compiler: an applications perspective. |
FPGA |
2001 |
DBLP DOI BibTeX RDF |
FPGA design tools, FPGA, high-level synthesis, configurable computing, hardware-software co-design, silicon compiler |
15 | Olivier Hébert, Ivan C. Kraljic, Yvon Savaria |
A method to derive application-specific embedded processing cores. |
CODES |
2000 |
DBLP DOI BibTeX RDF |
custom core, soft core, system-on-a-chip, embedded core, configurable processor |
15 | Maya B. Gokhale, Janice M. Stone, Jeffrey M. Arnold, Mirek Kalinowski |
Stream-Oriented FPGA Computing in the Streams-C High Level Language. |
FCCM |
2000 |
DBLP DOI BibTeX RDF |
FPGA design tools, FPGA, high-level synthesis, configurable computing, hardware-software co-design, silicon compiler |
15 | Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya |
Quasi-Static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems. |
IEEE International Workshop on Rapid System Prototyping |
2000 |
DBLP DOI BibTeX RDF |
digital signal processing, rapid prototyping, dataflow, software synthesis, configurable computing |
15 | Helena Krupnova, Gabriele Saucier |
FPGA Technology Snapshot: Current Devices and Design Tools. |
IEEE International Workshop on Rapid System Prototyping |
2000 |
DBLP DOI BibTeX RDF |
Configurable Logic Block (CLB), System on a Programmable Chip (SOPC), FPGAs, routing, synthesis, placement, Rapid prototyping, floorplanning, timing optimization, macro block |
15 | Robert Rinker, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm, Bruce A. Draper |
Compiling Image Processing Applications to Reconfigurable Hardware. |
ASAP |
2000 |
DBLP DOI BibTeX RDF |
compilers, Configurable computing, image processing applications |
15 | Jack S. N. Jean, Karen A. Tomko, Vikram Yavagal, Jignesh Shah, Robert Cook |
Dynamic Reconfiguration to Support Concurrent Applications. |
IEEE Trans. Computers |
1999 |
DBLP DOI BibTeX RDF |
scheduling, field programmable gate array (FPGA), resource management, reconfiguration, Configurable computing |
15 | Matti A. Hiltunen, Richard D. Schlichting, Xiaonan Han, Melvin M. Cardozo, Rajsekhar Das |
Real-Time Dependable Channels: Customizing QoS Attributes for Distributed Systems. |
IEEE Trans. Parallel Distributed Syst. |
1999 |
DBLP DOI BibTeX RDF |
group multicast, Real-time, dependability, customization, configurable systems |
15 | Eric K. Pauer, Paul D. Fiore, John M. Smith |
Algorithm Analysis and Mapping Environment for Adaptive Computing Systems: Further Results. |
FCCM |
1999 |
DBLP DOI BibTeX RDF |
smart generators, FPGA, synthesis, VHDL, configurable computing, ACS, Ptolemy |
15 | Mark Jones 0002, Luke Scharf, Jonathan Scott, Chris Twaddle, Matthew Yaconis, Kuan Yao, Peter Athanas, Brian Schott |
Implementing an API for Distributed Adaptive Computing Systems. |
FCCM |
1999 |
DBLP DOI BibTeX RDF |
parallel computing, API, embedded computing, configurable computing, adaptive computing |
15 | Darren C. Cronquist, Chris Fisher, Miguel E. Figueroa, Paul Franklin, Carl Ebeling |
Architecture Design of Reconfigurable Pipelined Datapaths. |
ARVLSI |
1999 |
DBLP DOI BibTeX RDF |
High-speed computation, Pipelining, Signal processing, Reconfigurable architectures, Configurable computing |
15 | Michael Mrva, Klaus Buchenrieder, Rainer Kress 0002 |
A Scalable Architecture for Multi-threaded JAVA Applications. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
Java, configurable, multi-threaded, application-specific |
15 | Ray Bittner, Peter M. Athanas |
Wormhole Run-Time Reconfiguration. |
FPGA |
1997 |
DBLP DOI BibTeX RDF |
FPGA, VLSI, digital signal processing, data flow, configurable computing |
15 | Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara |
A Test Methodology for Interconnect Structures of LUT-based FPGAs. |
Asian Test Symposium |
1996 |
DBLP DOI BibTeX RDF |
Programmable Interconnect Structures, Cross Point Switch, Configurable Logic Block, FPGA, Test Pattern Generation |
13 | Konrad Voigt, Petko Ivanov, Andreas Rummler |
MatchBox: combined meta-model matching for semi-automatic mapping generation. |
SAC |
2010 |
DBLP DOI BibTeX RDF |
meta-model matching, mapping generation, model engineering |
13 | Alessandro Bozzon, Marco Brambilla 0001, Piero Fraternali, Pasquale Pigazzini |
Integration of a human face annotation technology in an audio-visual search engine platform. |
SAC |
2010 |
DBLP DOI BibTeX RDF |
audiovisual information retrieval, multimedia, architectures, search engine, web search, face detection, automatic video annotation |
13 | William Farr, Nicola Yuill, Eric Charles Harris, Steve Hinske |
In my own words: configuration of tangibles, object interaction and children with autism. |
IDC |
2010 |
DBLP DOI BibTeX RDF |
social interaction, configuration, tangibles, autism, object interaction |
13 | António Rodrigues, Nuno Roma, Leonel Sousa |
p264: open platform for designing parallel H.264/AVC video encoders on multi-core systems. |
NOSSDAV |
2010 |
DBLP DOI BibTeX RDF |
h.264, parallel systems, multi-core processors, video encoder |
13 | Benjamin Stopford, Steve Counsell, Emal Nasseri |
Simulating Software Evolution with Varying Numbers of Developers and Validation Using OSS. |
Australian Software Engineering Conference |
2009 |
DBLP DOI BibTeX RDF |
|
13 | Paul E. Marks, Cameron D. Patterson |
Data streaming and simd support for the microblaze architecture. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
streaming coprocessors, vector units, reconfigurability |
13 | Stephen Friedman, Allan Carroll, Brian Van Essen, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck |
SPR: an architecture-adaptive CGRA mapping tool. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
modulo graph, spr, static sharing, clustering, scheduling, routing, placement, pathfinder |
13 | Concepción Sanz, Manuel Prieto 0001, José Ignacio Gómez, Antonis Papanikolaou, Francky Catthoor |
System-level process variability compensation on memory organizations: on the scalability of multi-mode memories. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
13 | Yixin Diao, Xiaolei Hu, Asser N. Tantawi, Haishan Wu |
An adaptive feedback controller for SIP server memory overload protection. |
ICAC |
2009 |
DBLP DOI BibTeX RDF |
memory overload protection, modeling, adaptive control, workload characterization |
13 | Brent E. Nelson |
FPGA Design Productivity - A Discussion of the State of the Art and a Research Agenda. |
ARC |
2009 |
DBLP DOI BibTeX RDF |
|
13 | Toshinori Sato, Shingo Watanabe |
Uncriticality-directed scheduling for tackling variation and power challenges. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
13 | Yoonjin Kim, Rabi N. Mahapatra |
Hierarchical reconfigurable computing arrays for efficient CGRA-based embedded systems. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
coarse-grained reconfigurable architecture (CGRA), computing hierarchy, embedded systems |
13 | Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, Christian Schlegel |
A Compact and Accurate Gaussian Variate Generator. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Florian Gottschalk, Wil M. P. van der Aalst, Monique H. Jansen-Vullers, H. M. W. Verbeek |
Protos2CPN: using colored Petri nets for configuring and testing business processes. |
Int. J. Softw. Tools Technol. Transf. |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Nikolay Malitsky |
Processing heterogeneous abstract syntax trees with the mutable class pattern. |
OOPSLA Companion |
2008 |
DBLP DOI BibTeX RDF |
heterogeneous trees, mutable class pattern, OOP, AOP, visitor pattern |
13 | Maryam Moazeni, Alireza Vahdatpour, Karthik Gururaj, Majid Sarrafzadeh |
Communication bottleneck in hardware-software partitioning. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
FPGA, communication, hardware-software codesign |
13 | Maristela Holanda, Angelo Brayner, Sergio Fialho |
Introducing self-adaptability into transaction processing. |
SAC |
2008 |
DBLP DOI BibTeX RDF |
MANET and MDBC, scheduler, databases, concurrency control |
13 | Bin Wu, Shijun Liu, Lei Wu 0002 |
Dynamic Reliable Service Routing in Enterprise Service Bus. |
APSCC |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Florian Gottschalk, Wil M. P. van der Aalst, Monique H. Jansen-Vullers |
Mining Reference Process Models and Their Configurations. |
OTM Workshops |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Young-Su Kwon, Bontae Koo, Nak-Woong Eum |
Application-adaptive reconfiguration of memory address shuffler for FPGA-embedded instruction-set processor. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Limei Liu, Yantao Tian, Xiaoliang Huang |
A Method to Estimate the Basin of Attraction of the System with Impulse Effects: Application to the Biped Robots. |
ICIRA (1) |
2008 |
DBLP DOI BibTeX RDF |
System with Impulse Effects, Biped Robot, Basin of Attraction |
13 | Zhiyi Yu, Bevan M. Baas |
A low-area interconnect architecture for chip multiprocessors. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Yuanfang Zhang, Christopher D. Gill, Chenyang Lu 0001 |
Reconfigurable Real-Time Middleware for Distributed Cyber-Physical Systems with Aperiodic Events. |
ICDCS |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Ada S. Y. Poon |
An Energy-Efficient Reconfigurable Baseband Processor for Wireless Communications. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Nachiketh R. Potlapally, Srivaths Ravi 0001, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha |
Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro |
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs. |
J. Electron. Test. |
2007 |
DBLP DOI BibTeX RDF |
reliability, fault tolerant systems, SEU, SRAM-based FPGA |
13 | Wen-Hong Zhu, Tom Lamarche |
Modular Robot Manipulators Based on Virtual Decomposition Control. |
ICRA |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Akash Kumar 0001, Andreas Hansson 0001, Jos Huisken, Henk Corporaal |
Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Xiao Hu, Pengyong Ma, Shuming Chen |
Scheduling for Combining Traffic of On-Chip Trace Data in Embedded Multi-core Processor. |
ICESS |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Xiangjie Ma, Junpeng Mao, Yuxiang Hu, Julong Lan, Lian Guan, Baisheng Zhang |
Measurement of High-Speed IP Traffic Behavior Based on Routers. |
APPT |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Rakesh Reddy, Peter Petrov |
Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking systems. |
CASES |
2007 |
DBLP DOI BibTeX RDF |
real-time embedded systems, cache interference |
13 | Tom Lamarche, Wen-Hong Zhu |
A virtual decomposition control based communication network for modular robots applications. |
ICCCN |
2007 |
DBLP DOI BibTeX RDF |
|
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