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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2225 occurrences of 1302 keywords
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Results
Found 4812 publication records. Showing 4812 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
17 | Aad P. A. van Moorsel, Yiqing Huang |
Reusable Software Components for Performability Tools and Their Utilization for Web-Based Configurable Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer Performance Evaluation (Tools) ![In: Computer Performance Evaluation: Modelling Techniques and Tools, 10th International Conference, Tools '98, Palma de Mallorca, Spain, September 14-18, 1998, Proceedings, pp. 37-50, 1998, Springer, 3-540-64949-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Wei-Kang Huang, M. Y. Zhang, Fred J. Meyer, Fabrizio Lombardi |
A XOR-Tree Based Technique for Constant Testability of Configurable FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 248-253, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
programmable system, diagnosis, FPGA testing, XOR |
17 | Seonil Choi, Viktor K. Prasanna, Yongwha Chung |
Configurable Hardware for Symbolic Search Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1997 International Conference on Parallel and Distributed Systems (ICPADS '97), 11-13 December 1997, Seoul, Korea, Proceedings, pp. 122-131, 1997, IEEE Computer Society, 0-8186-8227-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
17 | David Channon, David Koch |
Performance Analysis of Re-configurable Partitioned TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (5) ![In: 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 7-10 January 1997, Maui, Hawaii, USA, pp. 168-177, 1997, IEEE Computer Society, 0-8186-7734-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Computer Architecture, Memory Management, Partitioning Algorithm, Address Translation |
17 | Wei-Kang Huang, Fabrizio Lombardi |
An approach for testing programmable/configurable field programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 450-455, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
behavioral characterization, single fault detection, disjoint one-dimensional arrays, unilateral horizontal connections, common vertical input lines, array testing, logic blocks, field programmable gate arrays, field programmable gate arrays, VLSI, logic testing, integrated circuit testing, stuck-at fault, FPGA testing, functional fault, hybrid fault model |
17 | Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic |
Architecture of Centralized Field-Configurable Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14, 1995, pp. 97-103, 1995, ACM, 0-89791-743-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Nina T. Bhatti, Richard D. Schlichting |
A System for Constructing Configurable High-Level Protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCOMM ![In: Proceedings of the ACM SIGCOMM 1995 Conference on Applications, Technologies, Architectures, and Protocols for Computer Communication, Cambridge, MA, USA, August 28 - September 1, 1995., pp. 138-150, 1995, ACM, 0-89791-711-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Rick Amerson, Richard J. Carter, W. Bruce Culbertson, Philip Kuekes, Greg Snider |
Teramac-configurable custom computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 3rd IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '95), 19-21 April 1995, Napa Valley, CA, USA, pp. 32-38, 1995, IEEE Computer Society, 0-8186-7086-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Alfred Strey, Narcís Avellana, Raul Holgado, Ramon Capillas, J. Alberto Fernández, Elena Valderrama |
A Configurable Parallel Neurocomputer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANNES ![In: 2nd New Zealand Two-Stream International Conference on Artificial Neural Networks and Expert Systems (ANNES '95), November 20-23, 1995, Dunedin, New Zealand, pp. 55-58, 1995, IEEE Computer Society, 0-8186-7174-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
neural hardware, parallel computer, neurocomputer |
17 | Gordon J. Brebner |
Configurable array logic circuits for computing network error detection codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 6(2), pp. 101-117, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Jeff Kramer, Anthony Finkelstein |
A Configurable Framework for Method and Tool Integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Software Development Environments and CASE Technology ![In: Software Development Environments and CASE Technology, European Symposium, Königswinter, Germany, June 17-19, 1991, Proceedings, pp. 233-257, 1991, Springer, 3-540-54194-2. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
17 | Tom Kean, John Gray |
Configurable hardware: Two case studies of micro-grain computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 2(1), pp. 9-16, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
15 | Krzysztof Kepa, Fearghal Morgan, Peter Athanas |
ERDB: An Embedded Routing Database for Reconfigurable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece, pp. 195-200, 2011, IEEE Computer Society, 978-1-4577-1484-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
design integrity, security, FPGA, autonomic computing, partial reconfiguration, configurable systems |
15 | Wil M. P. van der Aalst |
Business Process Configuration in the Cloud: How to Support and Analyze Multi-tenant Processes? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECOWS ![In: 9th IEEE European Conference on Web Services, ECOWS 2011, Lugano, Switzerland, September 14-16, 2011, pp. 3-10, 2011, IEEE, 978-1-4577-1532-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
configurable process models, cross-organizational process mining, causal nets, cloud computing |
15 | Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita |
High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 291, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
dopant-segregated schottky transistor, nonvolatile configurable memory |
15 | Roman L. Lysecky, Frank Vahid |
Design and implementation of a MicroBlaze-based warp processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 8(3), pp. 22:1-22:22, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
soft processor cores, FPGA, dynamic optimization, hardware/software partitioning, configurable logic, Warp processors, just-in-time (JIT) compilation |
15 | André Stauffer, Joël Rossier |
Bio-inspired Self-Testing and Self-Organizing Bit Slice Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings, pp. 427-432, 2009, IEEE Computer Society, 978-0-7695-3917-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
configurable molecule, cicatrization, test, configuration, regeneration |
15 | Michael P. Caffrey, Keith Morgan, Diane Roussel-Dupre, Scott Robinson, Anthony Nelson, Anthony Salazar, Michael J. Wirthlin, William Howes, Daniel Richins |
On-Orbit Flight Results from the Reconfigurable Cibola Flight Experiment Satellite (CFESat). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: FCCM 2009, 17th IEEE Symposium on Field Programmable Custom Computing Machines, Napa, California, USA, 5-7 April 2009, Proceedings, pp. 3-10, 2009, IEEE Computer Society, 978-0-7695-3716-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA, fault tolerant computing, configurable computing |
15 | Xiaohui Cheng, Yongjian Hu, Youmin Gong |
Design Methodology of Control System with Mutual Exclusion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACIIA (2) ![In: PACIIA 2008, Volume 2, 2008 IEEE Pacific-Asia Workshop on Computational Intelligence and Industrial Application, 19-20 December 2008, Wuhan, China, pp. 403-407, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, Mutual Exclusion, Control System, Hardware/software Partition, Hardware/software Co-design, Configurable Logics |
15 | Jason Yu, Guy G. Lemieux, Christopher Eagleston |
Vector processing as a soft-core CPU accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 222-232, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
C2H, FPGA, configurable, embedded processor, application specific, soft processor, data-level parallelism |
15 | Antoine Gallais, Jean Carle |
Performance Evaluation and Enhancement of Surface Coverage Relay Protocol. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networking ![In: NETWORKING 2008, Ad Hoc and Sensor Networks, Wireless Networks, Next Generation Internet , 7th International IFIP-TC6 Networking Conference, Singapore, May 5-9, 2008, Proceedings, pp. 124-134, 2008, Springer, 978-3-540-79548-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
configurable localized algorithm, realistic physical layer, Wireless sensor networks, area coverage |
15 | Sean P. Sangster, John T. Blake |
Developing a reusable simulation model to improve access to diagnostic imaging clinics in Nova Scotia. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SpringSim ![In: Proceedings of the 2008 Spring Simulation Multiconference, SpringSim 2008, Ottawa, Canada, April 14-17, 2008, pp. 539-544, 2008, SCS/ACM, 1-56555-319-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
configurable simulation, diagnostic imaging, patient flow, reusable simulation, discrete event simulation |
15 | Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank Vahid |
A table-based method for single-pass cache optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 71-76, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
configurable cache tuning, low energy, cache optimization |
15 | Juan A. Escalera, Manuel Ferre, Rafael Aracil, José Baca |
ROBMAT: Teleoperation of a Modular Robot for Collaborative Manipulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (2) ![In: Knowledge-Based Intelligent Information and Engineering Systems, 11th International Conference, KES 2007, XVII Italian Workshop on Neural Networks, Vietri sul Mare, Italy, September 12-14, 2007. Proceedings, Part II, pp. 1204-1213, 2007, Springer, 978-3-540-74826-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
robot, Modular, teleoperation, self-configurable, human-interface |
15 | Nut Taesombut, Andrew A. Chien |
Evaluating the impacts of network information models on applications and network service providers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPDC ![In: Proceedings of the 16th International Symposium on High-Performance Distributed Computing (HPDC-16 2007), 25-29 June 2007, Monterey, California, USA, pp. 215-216, 2007, ACM, 978-1-59593-673-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
configurable optical network, lambda-grids, information model |
15 | Roman L. Lysecky, Greg Stitt, Frank Vahid |
Warp Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(3), pp. 659-681, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FPGA, dynamic optimization, hardware/software codesign, hardware/software partitioning, configurable logic, Warp processors, just-in-time (JIT) compilation |
15 | Arjen van Rhijn, Jurriaan D. Mulder |
Spatial input device structure and bimanual object manipulation in virtual environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VRST ![In: Proceedings of the ACM Symposium on Virtual Reality Software and Technology, VRST 2006, Limassol, Cyprus, November 1-3, 2006, pp. 51-60, 2006, ACM, 1-59593-321-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
configurable input device, multi-dimensional control, virtual reality, direct manipulation |
15 | Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers |
IEEE-Compliant IDCT on FPGA-Augmented TriMedia. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 39(3), pp. 195-212, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
inverse discrete cosine transform, field-programmable gate array, configurable computing, VLIW processor |
15 | Heidi E. Ziegler, Mary W. Hall |
Evaluating heuristics in automatically mapping multi-loop applications to FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 184-195, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
high-level and architectural synthesis, parallelizing compiler analysis techniques, synthesis techniques for configurable computing, FPGAs, pipelining, rapid prototyping, hardware design |
15 | Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan |
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 17-20 April 2005, Napa, CA, USA, Proceedings, pp. 57-62, 2005, IEEE Computer Society, 0-7695-2445-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
standard hardware binary, FPGA, dynamic optimization, system-on-a-chip, platforms, codesign, hardware/software partitioning, configurable logic, Place and route, warp processors, just-in-time (JIT) compilation |
15 | Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry |
LAP: a logic activity packing methodology for leakage power-tolerant FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 257-262, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
activity profile, basic logic elements (BLEs), configurable logic blocks (CLBs), sleep transistor (ST), sub-threshold leakage power, FPGA, packing |
15 | Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou |
A Low-Power Processor Architecture Optimized forWireless Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece, pp. 185-190, 2005, IEEE Computer Society, 0-7695-2407-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Pipeline depth, configurable pipeline, power-adaptive processors, Low power, asynchronous circuits |
15 | William D. Smith, Austars R. Schnore |
Towards an RCC-Based Accelerator for Computational Fluid Dynamics Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 30(3), pp. 239-261, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
re-configurable computing applications, computational fluid dynamics |
15 | Joonseok Park, Pedro C. Diniz, K. R. Shesha Shayee |
Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(11), pp. 1420-1435, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Performance analysis and modeling, loop transformations and high-level synthesis, Field-Programmable-Gate-Arrays (FPGAs), configurable computing |
15 | Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu 0001, Changkyu Kim, Jaehyuk Huh 0001, Nitya Ranganathan, Doug Burger, Stephen W. Keckler, Robert G. McDonald, Charles R. Moore |
TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 1(1), pp. 62-93, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
scalable and high-performance computing, Computer architecture, configurable computing |
15 | Andreas Dandalis, Viktor K. Prasanna |
An adaptive cryptographic engine for internet protocol security architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 9(3), pp. 333-353, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
performance tradeoffs, reconfigurable components, cryptography, reconfigurable computing, AES, configurable, high performance, IPSec, reconfigurable systems, Adaptive computing |
15 | Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt |
Automatic Tuning of Two-Level Caches to Embedded Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 208-213, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
cache exploration, embedded systems, low power, low energy, cache optimization, architecture tuning, cache hierarchy, Configurable cache |
15 | Timo Vogt, Norbert Wehn, Philippe Alves |
A multi-standard channel-decoder for base-station applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 192-197, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
CDMA2k, convolutional decoder, hardware sharing, wireless, configurable, MAP, W-CDMA |
15 | Keith D. Underwood, K. Scott Hemmert |
Closing the Gap: CPU and FPGA Trends in Sustainable Floating-Point BLAS Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 20-23 April 2004, Napa, CA, USA, Proceedings, pp. 219-228, 2004, IEEE Computer Society, 0-7695-2230-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
IEEE floating point, re-configurable computing, FPGA, arithmetic |
15 | Maya B. Gokhale, Christine Ahrens, Janette Frigo, Christophe Wolinski |
Communications Scheduling for Concurrent Processes on Reconfigurable Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 20-23 April 2004, Napa, CA, USA, Proceedings, pp. 186-193, 2004, IEEE Computer Society, 0-7695-2230-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Configurable System on a Chip, scheduling, FPGA, high level synthesis, reconfigurable computing, Cellular Array |
15 | Allen C. Cheng, Gary S. Tyson, Trevor N. Mudge |
FITS: framework-based instruction-set tuning synthesis for embedded application specific processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 920-923, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
16-bit ISA, instruction synthesis, low-power, energy efficient, embedded processor, reconfigurable processors, ASP, instruction encoding, configurable architecture, code density |
15 | Kiran Puttegowda, David I. Lehn, Jae H. Park, Peter M. Athanas, Mark T. Jones |
Context Switching in a Run-Time Reconfigurable System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 26(3), pp. 239-257, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
virtual hardware, FPGA, run-time reconfiguration, configurable computing, context switching, multi-context |
15 | Jack Liu, Fred C. Chow, Timothy Kong, Rupan Roy |
Variable Instruction Set Architecture and Its Compiler Support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(7), pp. 881-895, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Configurable code generation, variable instruction set, embedded processor, instruction scheduling, dictionary, enumeration, program representation, resource modeling |
15 | David Goodwin, Darin Petkov |
Automatic generation of application specific processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003, pp. 137-147, 2003, ACM, 1-58113-676-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
automatic instruction-set generation, ASIPs, configurable processors, extensible processors |
15 | Chuanjun Zhang, Frank Vahid |
Cache Configuration Exploration on Prototyping Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 9-11 June 2003, San Diego, CA, USA, pp. 164-, 2003, IEEE Computer Society, 0-7695-1943-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
embedded systems, low power, memory hierarchy, low energy, architecture tuning, Configurable cache, system-level exploration |
15 | Heidi E. Ziegler, Mary W. Hall, Pedro C. Diniz |
Compiler-generated communication for pipelined FPGA applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 610-615, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
high-level and architectural synthesis, parallelizing compiler analysis techniques, synthesis techniques for configurable computing, FPGAs, pipelining, rapid prototyping |
15 | Keith D. Cooper, Devika Subramanian, Linda Torczon |
Adaptive Optimizing Compilers for the 21st Century. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 23(1), pp. 7-22, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
configurable compilers, order of optimization, biased random search, optimizing compilers |
15 | Andreas Dandalis, Viktor K. Prasanna |
Run-time performance optimization of an FPGA-based deduction engine for SAT solvers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(4), pp. 547-562, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
reconfigurable components, reconfigurable computing, configurable, high performance, Boolean satisfiability, reconfigurable systems, Adaptive computing, performance trade-offs |
15 | Jack Liu, Timothy Kong, Fred C. Chow |
Effective Compilation Support for Variable Instruction Set Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 22-25 September 2002, Charlottesville, VA, USA, pp. 56-67, 2002, IEEE Computer Society, 0-7695-1620-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
configurable code generation, variable instruction set, embedded processor, instruction scheduling, dictionary, enumeration, program representation, resource modeling |
15 | Owen G. McGrath |
Building an instructional portal: channeling the writing lab. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGUCCS ![In: Proceedings of the 30th annual ACM SIGUCCS conference on User services: Charting Bold Courses - New Worlds in User Services, Providence, Rhode Island, USA, November 20-23, 2002, pp. 199-203, 2002, ACM, 1-58113-564-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
general presentation layer, instructional portal, on-line writing lab (OWL), user-configurable interfaces, channels |
15 | Jack Liu, Fred C. Chow |
A near-optimal instruction scheduler for a tightly constrained, variable instruction set embedded processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 9-18, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
configurable code generation, variable instruction set, embedded processor, instruction scheduling, dictionary, enumeration, program representation, resource modeling |
15 | Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg |
A case for dynamic pipeline scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 1-8, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
configurable pipeline, fetch gating, power and energy management, shallow and deep pipelines, variable-depth pipeline, dynamic voltage scaling, clock gating |
15 | Dannie Lau, Aaron Schneider, Milos D. Ercegovac, John D. Villasenor |
A FPGA-based Library for On-Line Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 28(1-2), pp. 129-143, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
FFT, DSP, DCT, configurable computing, on-line arithmetic |
15 | Peter Bellows, Brad L. Hutchings |
Designing Run-Time Reconfigurable Systems with JHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 28(1-2), pp. 29-45, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
FPGAs, image processing, CAD, configurable computing |
15 | Janette Frigo, Maya B. Gokhale, Dominique Lavenier |
Evaluation of the streams-C C-to-FPGA compiler: an applications perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001, pp. 134-140, 2001, ACM, 1-58113-341-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
FPGA design tools, FPGA, high-level synthesis, configurable computing, hardware-software co-design, silicon compiler |
15 | Olivier Hébert, Ivan C. Kraljic, Yvon Savaria |
A method to derive application-specific embedded processing cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Eighth International Workshop on Hardware/Software Codesign, CODES 2000, San Diego, California, USA, 2000, pp. 88-92, 2000, ACM, 1-58113-268-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
custom core, soft core, system-on-a-chip, embedded core, configurable processor |
15 | Maya B. Gokhale, Janice M. Stone, Jeffrey M. Arnold, Mirek Kalinowski |
Stream-Oriented FPGA Computing in the Streams-C High Level Language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings, pp. 49-58, 2000, IEEE Computer Society, 0-7695-0871-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
FPGA design tools, FPGA, high-level synthesis, configurable computing, hardware-software co-design, silicon compiler |
15 | Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya |
Quasi-Static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), Paris, France, June 21-23, 2000, pp. 84-89, 2000, IEEE Computer Society, 0-7695-0668-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
digital signal processing, rapid prototyping, dataflow, software synthesis, configurable computing |
15 | Helena Krupnova, Gabriele Saucier |
FPGA Technology Snapshot: Current Devices and Design Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), Paris, France, June 21-23, 2000, pp. 200-, 2000, IEEE Computer Society, 0-7695-0668-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Configurable Logic Block (CLB), System on a Programmable Chip (SOPC), FPGAs, routing, synthesis, placement, Rapid prototyping, floorplanning, timing optimization, macro block |
15 | Robert Rinker, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm, Bruce A. Draper |
Compiling Image Processing Applications to Reconfigurable Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA, pp. 56-65, 2000, IEEE Computer Society, 0-7695-0716-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
compilers, Configurable computing, image processing applications |
15 | Jack S. N. Jean, Karen A. Tomko, Vikram Yavagal, Jignesh Shah, Robert Cook |
Dynamic Reconfiguration to Support Concurrent Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(6), pp. 591-602, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
scheduling, field programmable gate array (FPGA), resource management, reconfiguration, Configurable computing |
15 | Matti A. Hiltunen, Richard D. Schlichting, Xiaonan Han, Melvin M. Cardozo, Rajsekhar Das |
Real-Time Dependable Channels: Customizing QoS Attributes for Distributed Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 10(6), pp. 600-612, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
group multicast, Real-time, dependability, customization, configurable systems |
15 | Eric K. Pauer, Paul D. Fiore, John M. Smith |
Algorithm Analysis and Mapping Environment for Adaptive Computing Systems: Further Results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA, pp. 264-265, 1999, IEEE Computer Society, 0-7695-0375-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
smart generators, FPGA, synthesis, VHDL, configurable computing, ACS, Ptolemy |
15 | Mark Jones 0002, Luke Scharf, Jonathan Scott, Chris Twaddle, Matthew Yaconis, Kuan Yao, Peter Athanas, Brian Schott |
Implementing an API for Distributed Adaptive Computing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA, pp. 222-, 1999, IEEE Computer Society, 0-7695-0375-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
parallel computing, API, embedded computing, configurable computing, adaptive computing |
15 | Darren C. Cronquist, Chris Fisher, Miguel E. Figueroa, Paul Franklin, Carl Ebeling |
Architecture Design of Reconfigurable Pipelined Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 18th Conference on Advanced Research in VLSI (ARVLSI '99), 21-24 March 1999, Atlanta, GA, USA, pp. 23-41, 1999, IEEE Computer Society, 0-7695-0056-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
High-speed computation, Pipelining, Signal processing, Reconfigurable architectures, Configurable computing |
15 | Michael Mrva, Klaus Buchenrieder, Rainer Kress 0002 |
A Scalable Architecture for Multi-threaded JAVA Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 868-874, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Java, configurable, multi-threaded, application-specific |
15 | Ray Bittner, Peter M. Athanas |
Wormhole Run-Time Reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, FPGA 1997, Monterey, CA, USA, February 9-11, 1997, pp. 79-85, 1997, ACM, 0-89791-801-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
FPGA, VLSI, digital signal processing, data flow, configurable computing |
15 | Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara |
A Test Methodology for Interconnect Structures of LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 68-74, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Programmable Interconnect Structures, Cross Point Switch, Configurable Logic Block, FPGA, Test Pattern Generation |
13 | Konrad Voigt, Petko Ivanov, Andreas Rummler |
MatchBox: combined meta-model matching for semi-automatic mapping generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), Sierre, Switzerland, March 22-26, 2010, pp. 2281-2288, 2010, ACM, 978-1-60558-639-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
meta-model matching, mapping generation, model engineering |
13 | Alessandro Bozzon, Marco Brambilla 0001, Piero Fraternali, Pasquale Pigazzini |
Integration of a human face annotation technology in an audio-visual search engine platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), Sierre, Switzerland, March 22-26, 2010, pp. 839-843, 2010, ACM, 978-1-60558-639-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
audiovisual information retrieval, multimedia, architectures, search engine, web search, face detection, automatic video annotation |
13 | William Farr, Nicola Yuill, Eric Charles Harris, Steve Hinske |
In my own words: configuration of tangibles, object interaction and children with autism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IDC ![In: Interaction Design and Children, Proceedings of the 9th International Conference on Interaction Design and Children, IDC 2010, Barcelona, Spain, June 9-12, 2010, pp. 30-38, 2010, ACM, 978-1-60558-951-0. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
social interaction, configuration, tangibles, autism, object interaction |
13 | António Rodrigues, Nuno Roma, Leonel Sousa |
p264: open platform for designing parallel H.264/AVC video encoders on multi-core systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOSSDAV ![In: Network and Operating System Support for Digital Audio and Video, 20th International Workshop, NOSSDAV 2010, Amsterdam, The Netherlands, June 2-4, 2010, Proceedings, pp. 81-86, 2010, ACM, 978-1-4503-0043-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
h.264, parallel systems, multi-core processors, video encoder |
13 | Benjamin Stopford, Steve Counsell, Emal Nasseri |
Simulating Software Evolution with Varying Numbers of Developers and Validation Using OSS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Australian Software Engineering Conference ![In: 20th Australian Software Engineering Conference (ASWEC 2009), 14-17 April 2009, Gold Cost, Australia, pp. 13-22, 2009, IEEE Computer Society, 978-0-7695-3599-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
13 | Paul E. Marks, Cameron D. Patterson |
Data streaming and simd support for the microblaze architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 277, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
streaming coprocessors, vector units, reconfigurability |
13 | Stephen Friedman, Allan Carroll, Brian Van Essen, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck |
SPR: an architecture-adaptive CGRA mapping tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 191-200, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
modulo graph, spr, static sharing, clustering, scheduling, routing, placement, pathfinder |
13 | Concepción Sanz, Manuel Prieto 0001, José Ignacio Gómez, Antonis Papanikolaou, Francky Catthoor |
System-level process variability compensation on memory organizations: on the scalability of multi-mode memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 254-259, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
13 | Yixin Diao, Xiaolei Hu, Asser N. Tantawi, Haishan Wu |
An adaptive feedback controller for SIP server memory overload protection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICAC ![In: Proceedings of the 6th International Conference on Autonomic Computing, ICAC 2009, June 15-19, 2009, Barcelona, Spain, pp. 23-32, 2009, ACM, 978-1-60558-564-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
memory overload protection, modeling, adaptive control, workload characterization |
13 | Brent E. Nelson |
FPGA Design Productivity - A Discussion of the State of the Art and a Research Agenda. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 1, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
13 | Toshinori Sato, Shingo Watanabe |
Uncriticality-directed scheduling for tackling variation and power challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 820-825, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
13 | Yoonjin Kim, Rabi N. Mahapatra |
Hierarchical reconfigurable computing arrays for efficient CGRA-based embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 826-831, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
coarse-grained reconfigurable architecture (CGRA), computing hierarchy, embedded systems |
13 | Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, Christian Schlegel |
A Compact and Accurate Gaussian Variate Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(5), pp. 517-527, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Florian Gottschalk, Wil M. P. van der Aalst, Monique H. Jansen-Vullers, H. M. W. Verbeek |
Protos2CPN: using colored Petri nets for configuring and testing business processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 10(1), pp. 95-110, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Nikolay Malitsky |
Processing heterogeneous abstract syntax trees with the mutable class pattern. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OOPSLA Companion ![In: Companion to the 23rd Annual ACM SIGPLAN Conference on Object-Oriented Programming, Systems, Languages, and Applications, OOPSLA 2008, October 19-13, 2007, Nashville, TN, USA, pp. 697-702, 2008, ACM, 978-1-60558-220-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
heterogeneous trees, mutable class pattern, OOP, AOP, visitor pattern |
13 | Maryam Moazeni, Alireza Vahdatpour, Karthik Gururaj, Majid Sarrafzadeh |
Communication bottleneck in hardware-software partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 262, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, communication, hardware-software codesign |
13 | Maristela Holanda, Angelo Brayner, Sergio Fialho |
Introducing self-adaptability into transaction processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), Fortaleza, Ceara, Brazil, March 16-20, 2008, pp. 992-997, 2008, ACM, 978-1-59593-753-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
MANET and MDBC, scheduler, databases, concurrency control |
13 | Bin Wu, Shijun Liu, Lei Wu 0002 |
Dynamic Reliable Service Routing in Enterprise Service Bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APSCC ![In: Proceedings of the 3rd IEEE Asia-Pacific Services Computing Conference, APSCC 2008, Yilan, Taiwan, 9-12 December 2008, pp. 349-354, 2008, IEEE Computer Society, 978-0-7695-3473-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Florian Gottschalk, Wil M. P. van der Aalst, Monique H. Jansen-Vullers |
Mining Reference Process Models and Their Configurations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OTM Workshops ![In: On the Move to Meaningful Internet Systems: OTM 2008 Workshops, OTM Confederated International Workshops and Posters, ADI, AWeSoMe, COMBEK, EI2N, IWSSA, MONET, OnToContent + QSI, ORM, PerSys, RDDS, SEMELS, and SWWS 2008, Monterrey, Mexico, November 9-14, 2008. Proceedings, pp. 263-272, 2008, Springer, 978-3-540-88874-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Young-Su Kwon, Bontae Koo, Nak-Woong Eum |
Application-adaptive reconfiguration of memory address shuffler for FPGA-embedded instruction-set processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 209-214, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Limei Liu, Yantao Tian, Xiaoliang Huang |
A Method to Estimate the Basin of Attraction of the System with Impulse Effects: Application to the Biped Robots. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIRA (1) ![In: Intelligent Robotics and Applications, First International Conference, ICIRA 2008, Wuhan, China, October 15-17, 2008 Proceedings, Part I, pp. 953-962, 2008, Springer, 978-3-540-88512-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
System with Impulse Effects, Biped Robot, Basin of Attraction |
13 | Zhiyi Yu, Bevan M. Baas |
A low-area interconnect architecture for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2857-2860, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Yuanfang Zhang, Christopher D. Gill, Chenyang Lu 0001 |
Reconfigurable Real-Time Middleware for Distributed Cyber-Physical Systems with Aperiodic Events. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS ![In: 28th IEEE International Conference on Distributed Computing Systems (ICDCS 2008), 17-20 June 2008, Beijing, China, pp. 581-588, 2008, IEEE Computer Society, 978-0-7695-3172-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Ada S. Y. Poon |
An Energy-Efficient Reconfigurable Baseband Processor for Wireless Communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(3), pp. 319-327, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Nachiketh R. Potlapally, Srivaths Ravi 0001, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha |
Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(5), pp. 605-609, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro |
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(1), pp. 47-54, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
reliability, fault tolerant systems, SEU, SRAM-based FPGA |
13 | Wen-Hong Zhu, Tom Lamarche |
Modular Robot Manipulators Based on Virtual Decomposition Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: 2007 IEEE International Conference on Robotics and Automation, ICRA 2007, 10-14 April 2007, Roma, Italy, pp. 2235-2240, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Akash Kumar 0001, Andreas Hansson 0001, Jos Huisken, Henk Corporaal |
Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 117-122, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Xiao Hu, Pengyong Ma, Shuming Chen |
Scheduling for Combining Traffic of On-Chip Trace Data in Embedded Multi-core Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, [Third] International Conference, ICESS 2007, Daegu, Korea, May 14-16, 2007, Proceedings, pp. 67-79, 2007, Springer, 978-3-540-72684-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Xiangjie Ma, Junpeng Mao, Yuxiang Hu, Julong Lan, Lian Guan, Baisheng Zhang |
Measurement of High-Speed IP Traffic Behavior Based on Routers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 7th International Symposium, APPT 2007, Guangzhou, China, November 22-23, 2007, Proceedings, pp. 222-232, 2007, Springer, 978-3-540-76836-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Rakesh Reddy, Peter Petrov |
Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 198-207, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
real-time embedded systems, cache interference |
13 | Tom Lamarche, Wen-Hong Zhu |
A virtual decomposition control based communication network for modular robots applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCN ![In: Proceedings of the 16th International Conference on Computer Communications and Networks, IEEE ICCCN 2007, Turtle Bay Resort, Honolulu, Hawaii, USA, August 13-16, 2007, pp. 1321-1326, 2007, IEEE, 978-1-4244-1251-8. The full citation details ...](Pics/full.jpeg) |
2007 |
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