Search results for "finfet"

Hits ?▲	Authors	Title	Venue	Year	Link
14	Sina Bakhtavari Mamaghani, Mohammad Hossein Moaiyeri, Ghassem Jaberipur	Design of an efficient fully nonvolatile and radiation-hardened majority-based magnetic full adder using FinFET/MTJ.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
14	Darsen D. Lu, Mohan V. Dunga, Ali M. Niknejad, Chenming Hu, Fu-Xiang Liang, Wei-Chen Hung, Jia-Wei Lee, Chun-Hsiang Hsu, Meng-Hsueh Chiang	Compact Device Models for FinFET and Beyond.	CoRR	2020	DBLP BibTeX RDF
14	Chao-Chieh Li, Min-Shueh Yuan, Yu-Tso Lin, Chia-Chun Liao, Chih-Hsien Chang, Robert Bogdan Staszewski	A 0.2-V Three-Winding Transformer-Based DCO in 16-nm FinFET CMOS.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
14	Hussam Amrouch, Girish Pahwa, Amol D. Gaidhane, Chetan K. Dabhi, Florian Klemme, Om Prakash 0007, Yogesh Singh Chauhan	Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology.	IEEE Trans. Circuits Syst. I Regul. Pap.	2020	DBLP DOI BibTeX RDF
14	Jeongho Hwang, Sang-Hyeok Chu, Gyu-Seob Jeong, Yeojoon Youn, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong	A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
14	Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis	Multi-Level Design Influences on Robustness Evaluation of 7nm FinFET Technology.	IEEE Trans. Circuits Syst. I Regul. Pap.	2020	DBLP DOI BibTeX RDF
14	Victor M. van Santen, Hussam Amrouch, Pooja Kumari, Jörg Henkel	On the Workload Dependence of Self-Heating in FinFET Circuits.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
14	Neeraj Jain, Balwinder Raj	SOI FinFET for Computer Networks and Cyber Security Systems.	Handbook of Computer Networks and Cyber Security	2020	DBLP DOI BibTeX RDF
14	Ashiq A. Sakib, Abir A. Akib, Scott C. Smith	Implementation of FinFET Based Static NCL Threshold Gates: An Analysis of Design Choice.	MWSCAS	2020	DBLP DOI BibTeX RDF
14	Kyle Whittaker, Maher E. Rizkalla, Trond Ytterdal	A Low Power FinFET Charge Pump for Energy Harvesting Applications.	MWSCAS	2020	DBLP DOI BibTeX RDF
14	Yao-Feng Chang, James A. O'Donnell, Tony Acosta, Roza Kotlyar, Albert B. Chen, Pedro A. Quintero, Nathan Strutt, Oleg Golonzka, Chris Connor, Jeff Hicks	eNVM RRAM reliability performance and modeling in 22FFL FinFET technology.	IRPS	2020	DBLP DOI BibTeX RDF
14	Lyuan Xu, Jingchen Cao, John Brockman, Carlo Cazzaniga, Christopher Frost 0002, Shi-Jie Wen, Rita Fung, Bharat L. Bhuva	Thermal Neutron Induced Soft Errors in 7-nm Bulk FinFET Node.	IRPS	2020	DBLP DOI BibTeX RDF
14	Chen-Yi Su, Mark Armstrong, Sunny Chugh, Mohammed El-tanani, Hannes Greve, Hai Li, Mahjabin Maksud, Benjamin Orr, Christopher Perini, James Palmer, Leif Paulson, Stephen Ramey, James Waldemer, Yang Yang, Dave Young	Reliability Characterization for 12 V Application Using the 22FFL FinFET Technology.	IRPS	2020	DBLP DOI BibTeX RDF
14	Rui Zhang 0048, Zhaocheng Liu, Kexin Yang 0001, Taizhi Liu, Wenshan Cai, Linda Milor	Inverse Design of FinFET SRAM Cells.	IRPS	2020	DBLP DOI BibTeX RDF
14	Rakesh Ranjan, Charles B. LaRow, Ki-Don Lee, Minhyo Kang, Pavitra R. Perepa, Md. Shahriar Rahman, Bong Ki Lee, David Moreau, Carolyn Cariss-Daniels, Timothy Basford, Colby Callahan, Maihan Nguyen, Gil Heyun Choi, Hyunchul Sagong, HwaSung Rhee	Trap Density Modulation for IO FinFET NBTI Improvement.	IRPS	2020	DBLP DOI BibTeX RDF
14	Govind Bajpai, Aniket Gupta, Om Prakash 0007, Girish Pahwa, Jörg Henkel, Yogesh Singh Chauhan, Hussam Amrouch	Impact of Radiation on Negative Capacitance FinFET.	IRPS	2020	DBLP DOI BibTeX RDF
14	Jingchen Cao, Lyuan Xu, Shi-Jie Wen, Rita Fung, Balaji Narasimham, Lloyd W. Massengill, Bharat L. Bhuva	Temperature Dependence of Single-Event Transient Pulse Widths for 7-nm Bulk FinFET Technology.	IRPS	2020	DBLP DOI BibTeX RDF
14	Hai Jiang 0005, Hyun-Chul Sagong, Jinju Kim, Hyewon Shim, Yoohwan Kim, Junekyun Park, Taiki Uemura, Yongsung Ji, Taeyoung Jeong, Dongkyun Kwon, Hwasung Rhee, Sangwoo Pae, Brandon Lee	Advanced Self-heating Model and Methodology for Layout Proximity Effect in FinFET Technology.	IRPS	2020	DBLP DOI BibTeX RDF
14	Taiki Uemura, Byungjin Chung, Jeongmin Jo, Hai Jiang 0005, Yongsung Ji, Tae-Young Jeong, Rakesh Ranjan, Youngin Park, Kiil Hong, Seungbae Lee, Hwasung Rhee, Sangwoo Pae, Euncheol Lee, Jaehee Choi, Shota Ohnishi, Ken Machida	Investigating of SER in 28 nm FDSOI-Planar and Comparing with SER in Bulk-FinFET.	IRPS	2020	DBLP DOI BibTeX RDF
14	Taiki Uemura, Byungjin Chung, Jeongmin Jo, Hai Jiang 0005, Yongsung Ji, Tae-Young Jeong, Rakesh Ranjan, Seungbae Lee, Hwasung Rhee, Sangwoo Pae, Euncheol Lee, Jaehee Choi, Shota Ohnishi, Ken Machida	Backside Alpha-Irradiation Test in Flip-Chip Package in EUV 7 nm FinFET SRAM.	IRPS	2020	DBLP DOI BibTeX RDF
14	Guilherme Cardoso Medeiros, Cemil Cem Gürsoy, Lizhou Wu, Moritz Fieback, Maksim Jenihhin, Mottaqiallah Taouil, Said Hamdioui	A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs.	DATE	2020	DBLP DOI BibTeX RDF
14	Shayesteh Masoumian, Georgios N. Selimis, Roel Maes, Geert Jan Schrijen, Said Hamdioui, Mottaqiallah Taouil	Modeling Static Noise Margin for FinFET based SRAM PUFs.	ETS	2020	DBLP DOI BibTeX RDF
14	Man Zhang, Lijun Zhang, Yiping Zhang	Anti-SEU design of SRAM based on FinFET process.	IWCMC	2020	DBLP DOI BibTeX RDF
14	Victor M. van Santen, Paul R. Genssler, Om Prakash 0007, Simon Thomann, Jörg Henkel, Hussam Amrouch	Impact of Self-Heating on Performance, Power and Reliability in FinFET Technology.	ASP-DAC	2020	DBLP DOI BibTeX RDF
14	Sajjad Rostami Sani, Farheen Fatima Khan, Anas Razzaq, Andy Gean Ye	Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology.	FPL	2020	DBLP DOI BibTeX RDF
14	Rafael N. M. Oliveira, Fábio G. R. G. da Silva, Ricardo Reis 0001, Cristina Meinhardt	Mirror Full Adder SET Susceptibility on 7nm FinFET Technology.	ICECS	2020	DBLP DOI BibTeX RDF
14	Hao Yu, Chengxu Wang, Xiangshui Miao, Xingsheng Wang	A TCAD-based Study of NDR Effect in NC-FinFET.	ICTA	2020	DBLP DOI BibTeX RDF
14	Bo Xiang, Yongping Fan, James S. Ayers, James Shen, Dan Zhang	A 0.5V-to-0.9V 0.2GHz-to-5GHz Ultra-Low-Power Digitally-Assisted Analog Ring PLL with Less Than 200ns Lock Time in 22nm FinFET CMOS Technology.	CICC	2020	DBLP DOI BibTeX RDF
14	Sukjin Kim, Radhakrishnan Sithanandam, Woojin Seo, Mijin Lee, Sangyoung Cho, Juho Park, Hyukhoon Kwon, Namho Kim, Chanhee Jeon	Technology Scaling of ESD Devices in State of the Art FinFET Technologies.	CICC	2020	DBLP DOI BibTeX RDF
14	Hyung-Jin Lee, Steven Callender, Said Rami, Woorim Shin, Qiang Yu, Jose Mauricio Marulanda	Intel 22nm Low-Power FinFET (22FFL) Process Technology for 5G and Beyond.	CICC	2020	DBLP DOI BibTeX RDF
14	You Li, Meng Miao, Robert Gauthier 0002	ESD Protection Design Overview in Advanced SOI and Bulk FinFET Technologies.	CICC	2020	DBLP DOI BibTeX RDF
14	Peter Lawrence Brown, Matthew R. O'Shaughnessy, Christopher J. Rozell, Justin Romberg, Michael P. Flynn	A 17.8MS/s Neural-Network Compressed Sensing Radar Processor in 16nm FinFET CMOS.	CICC	2020	DBLP DOI BibTeX RDF
14	Somnath Kundu, Likai Chai, Kailash Chandrashekar, Stefano Pellerano, Brent R. Carlton	25.5 A Self-Calibrated 1.2-to-3.8GHz 0.0052mm2 Synthesized Fractional-N MDLL Using a 2b Time-Period Comparator in 22nm FinFET CMOS.	ISSCC	2020	DBLP DOI BibTeX RDF
14	Hugh Mair, Ericbill Wang, Ashish Nayak, Rolf Lagerquist, Loda Chou, Gordon Gammie, HsinChen Chen, Lee-Kee Yong, Manzur Rahman, Jenny Wiedemeier, Ramu Madhavaram, Alex Chiou, Blundt Li, Vincent Lin, Rory Huang, Michael Yanq, Achuta Thippana, Osric Su, S. A. Huang	2.5 A 7nm FinFET 2.5GHz/2.0GHz Dual-Gear Octa-Core CPU Subsystem with Power/Performance Enhancements for a Fully Integrated 5G Smartphone SoC.	ISSCC	2020	DBLP DOI BibTeX RDF
14	Tamer A. Ali 0001, Ehung Chen, Henry Park, Ramy Yousry, Yu-Ming Ying, Mohammed Abdullatif, Miguel Gandara, Chun-Cheng Liu, Po-Shuan Weng, Huan-Sheng Chen, Mohammad Elbadry, Qaiser Nehal, Kun-Hung Tsai, Kevin Tan, Yi-Chieh Huang, Chung-Hsien Tsai, Yuyun Chang, Yuan-Hao Tung	6.2 A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology.	ISSCC	2020	DBLP DOI BibTeX RDF
14	Byoung-Joo Yoo, Dong-Hyuk Lim, Hyonguk Pang, June-Hee Lee, Seung-Yeob Baek 0002, Naxin Kim, Dong-Ho Choi, Young-Ho Choi, Hyeyeon Yang, Taehun Yoon, Sang-Hyeok Chu, Kangjik Kim, Woochul Jung, Bong-Kyu Kim, Jaechol Lee, Gunil Kang, Sang-Hune Park, Michael Choi, Jongshin Shin	6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier.	ISSCC	2020	DBLP DOI BibTeX RDF
14	Bishnu Patra, Jeroen P. G. van Dijk, Sushil Subramanian, Andrea Corna, Xiao Xue 0004, Charles Jeon, Farhana Sheikh, Esdras Juarez Hernandez, Brando Perez Esparza, Huzaifa Rampurawala, Brent R. Carlton, Nodar Samkharadze, Surej Ravikumar, Carlos Nieva, Sungwon Kim, Hyung-Jin Lee, Amir Sammak, Giordano Scappucci, Menno Veldhorst, Lieven M. K. Vandersypen, Masoud Babaie, Fabio Sebastiano, Edoardo Charbon, Stefano Pellerano	19.1 A Scalable Cryo-CMOS 2-to-20GHz Digitally Intensive Controller for 4×32 Frequency Multiplexed Spin Qubits/Transmons in 22nm FinFET Technology for Quantum Computers.	ISSCC	2020	DBLP DOI BibTeX RDF
14	Jay Im, Kevin Zheng, Adam Chou, Lei Zhou, Jae Wook Kim, Stanley Chen, Yipeng Wang 0003, Hao-Wei Hung, Kee Hian Tan, Winson Lin, Arianne Roldan, Declan Carey, Ilias Chlis, Ronan Casey, Ade Bekele, Ying Cao 0010, David Mahashin, Hong Ahn, Hongtao Zhang 0002, Yohan Frans, Ken Chang	6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET.	ISSCC	2020	DBLP DOI BibTeX RDF
14	Robert Christy, Stuart Riches, Sujil Kottekkat, Prasanth Gopinath, Ketan Sawant, Anitha Kona, Rob Harrison	8.3 A 3GHz ARM Neoverse N1 CPU in 7nm FinFET for Infrastructure Applications.	ISSCC	2020	DBLP DOI BibTeX RDF
14	Ming-Da Tsai, Chien-Wei Tseng, Kuen-Jou Tsai, Shuja Andrabi, Pin-Cheng Huang, Federico Beffa, Yangjian Chen, Bernard Tenbroek	10.6 A 4G/5G Cellular Transmitter in 12nm FinFET with Harmonic Rejection.	ISSCC	2020	DBLP DOI BibTeX RDF
14	Qing Dong 0001, Mahmut E. Sinangil, Burak Erbagci, Dar Sun, Win-San Khwa, Hung-Jen Liao, Yih Wang, Jonathan Chang	15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications.	ISSCC	2020	DBLP DOI BibTeX RDF
14	Jonathan Chang, Yen-Huei Chen, Gary Chan, Hank Cheng, Po-Sheng Wang, Yangsyu Lin, Hidehiro Fujiwara, Robin Lee, Hung-Jen Liao, Ping-Wei Wang, Geoffrey Yeap, Quincy Li	15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications.	ISSCC	2020	DBLP DOI BibTeX RDF
14	Bart Philippe, Patrick Reynaert	24.7 A 15dBm 12.8%-PAE Compact D-Band Power Amplifier with Two-Way Power Combining in 16nm FinFET CMOS.	ISSCC	2020	DBLP DOI BibTeX RDF
14	Eric Groen, Charlie Boecker, Masum Hossain, Roxanne Vu, Socrates D. Vamvakos, Haidang Lin, Simon Li, Marcus van Ierssel, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Mohammad Hossein Taghavi, Nhat Nguyen, Shaishav Desai	6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET.	ISSCC	2020	DBLP DOI BibTeX RDF
14	Pietro Caragiulo, Oscar Elisio Mattia, Amin Arbabian, Boris Murmann	A Compact 14 GS/s 8-Bit Switched-Capacitor DAC in 16 nm FinFET CMOS.	VLSI Circuits	2020	DBLP DOI BibTeX RDF
14	Sangwook Han, Jaehyuk Jang, Jaeseung Lee, Daechul Jeong, Joonhee Lee, Jongsoo Lee, Chung Lau, Juyoung Han, Sung-Jun Lee, Jeongyeol Bae, Ikkyun Cho, Sang-Yun Lee, Shinwoong Kim, Jae Hoon Lee, Yanghoon Lee, Jaehong Jung, Junho Huh, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang	An RF Transceiver with Full Digital Interface Supporting 5G New Radio FR1 with 3.84Gbps DL/1.92Gbps UL and Dual-Band GNSS in 14nm FinFET CMOS.	VLSI Circuits	2020	DBLP DOI BibTeX RDF
14	Phil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Mark A. Anders 0001, Himanshu Kaul, Steven K. Hsu, Amit Agarwal 0001, Monodeep Kar, Seongjong Kim, Ram K. Krishnamurthy	A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS.	VLSI Circuits	2020	DBLP DOI BibTeX RDF
14	Yang You, Glen A. Wiedemeier, Chad Marquart, Chris Steffen, Erik English, Dereje Yilma, Thomas Pham, Venkat Nammi, Jeffrey Okyere, Nathan Blanchard, Akil Sutton, Ze Zhang, David Friend, Diego Barba, Tyler Bohlke, Michael Spear, Vikram Raj, James Crugnale, Daniel Dreps, Pier Andrea Francese, Marcel A. Kossel, Thomas Morf	A 25×50Gb/s 2.22pJ/b NRZ RX with Dual-Bank and 3-Tap Speculative DFE for Microprocessor Application in 7nm FinFET CMOS.	VLSI Circuits	2020	DBLP DOI BibTeX RDF
14	Jaydeep P. Kulkarni, Andres Malavasi, Charles Augustine, Carlos Tokunaga, Jim Tschanz, Muhammad M. Khellah, Vivek De	Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS.	VLSI Circuits	2020	DBLP DOI BibTeX RDF
14	Haidang Lin, Charles Boecker, Masum Hossain, Shankar Tangirala, Roxanne Vu, Socrates D. Vamvakos, Eric Groen, Simon Li, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Hossein Taghavi, Marcus van Ierssel, AdilHussain Maniyar, Adam Wodkowski, Nhat Nguyen, Shaishav Desai	A 4×112 Gb/s ADC-DSP Based Multistandard Receiver in 7nm FinFET.	VLSI Circuits	2020	DBLP DOI BibTeX RDF
14	Yoshisato Yokoyama, Miki Tanaka, Koji Tanaka, Masao Morimoto, Makoto Yabuuchi, Yuichiro Ishii, Shinji Tanaka	A 29.2 Mb/mm2 Ultra High Density SRAM Macro using 7nm FinFET Technology with Dual-Edge Driven Wordline/Bitline and Write/Read-Assist Circuit.	VLSI Circuits	2020	DBLP DOI BibTeX RDF
14	Shilpi Birla, Neeraj Kumar Shukla, Neha Singh, M. Ram Kumar Raja	Performance Analysis of 8T FinFET SRAM Bit-Cell for Low-power Applications.	ICCCS	2020	DBLP DOI BibTeX RDF
14	Rania H. Mekky, Guillaume Fortin, Michael Venditti, Stephane Leclerc	A Multi-Range Duty Cycle Correction Circuit for Multi-Standard Transceivers in 7 nm FinFET.	ISCAS	2020	DBLP DOI BibTeX RDF
14	Farid Kenarangi, Inna Partin-Vaisband	Leveraging Independent Double-Gate FinFET Devices for Machine Learning Classification.	ISCAS	2020	DBLP DOI BibTeX RDF
14	Ragh Kuttappa, Baris Taskin	FinFET - Based Low Swing Rotary Traveling Wave Oscillators.	ISCAS	2020	DBLP DOI BibTeX RDF
14	Deepthi Amuru, Mohammed Salman Ahmed 0002, Zia Abbas	An Efficient Gradient Boosting Approach for PVT Aware Estimation of Leakage Power and Propagation Delay in CMOS/FinFET Digital Cells.	ISCAS	2020	DBLP DOI BibTeX RDF
14	Leonardo B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis 0001	Pros and Cons of ST and SIG FinFET Inverters for Low Power Designs.	ISCAS	2020	DBLP DOI BibTeX RDF
14	Yan Zheng, Fan Ye 0001, Junyan Ren	A 13 Bit 100 MS/s SAR ADC with 74.57 dB SNDR in 14-nm CMOS FinFET.	ISCAS	2020	DBLP DOI BibTeX RDF
14	Zahira Perez, Javier Mesalles, Hector Villacorta, Fabian Vargas 0001, Víctor H. Champac	Analysis and detection of hard-to-detect full open defects in FinFET based SRAM cells.	LATS	2020	DBLP DOI BibTeX RDF
14	Thiago Copetti, Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Said Hamdioui, Leticia Bolzani Poehls, Tiago R. Balen	Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects.	LATS	2020	DBLP DOI BibTeX RDF
14	Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis	Work-Function Fluctuation Impact on the SET Response of FinFET-based Majority Voters.	LATS	2020	DBLP DOI BibTeX RDF
14	E. Ramkumar, D. Gracin, P. Rajkamal, Bhuvana B. P., V. S. Kanchana Bhaaskaran	Design and Analysis of Low Power and High Speed FinFET based Hybrid Full Adder/Subtractor Circuit (FHAS).	iSES	2020	DBLP DOI BibTeX RDF
14	Motoi Ichihashi, Jia Zeng, Youngtag Woo, Xuelian Zhu, Chenchen Wang, James Mazza	Performance Boost Scheme with Activated Dummy Fin in 12-nm FinFET Technology for High-Performance Logic Application.	ISQED	2020	DBLP DOI BibTeX RDF
14	Pradeep K, Mohith B, Manjunath K. P, Sunita M. S	Comparative analysis of FinFET and Planar MOSFET SRAMs.	ISOCC	2020	DBLP DOI BibTeX RDF
14	Minji Lee, Changseok Choi, Donghyeon Seo, Byeongjun Bang, Yongseok Kang, Woohyun Paik	Improving Analysis Coverage for Dynamic IR Drop Sign-off in FinFET SoC Design.	ISOCC	2020	DBLP DOI BibTeX RDF
14	K. Sarangam, N. Bheema Rao	A FinFET based 2nd-Order Fully Differential Passive Sigma Delta Modulator for Low Power ADC.	ICCCNT	2020	DBLP DOI BibTeX RDF
14	Naheem Olakunle Adesina, Ashok Srivastava	A 250 MHz-to-1.6 GHz Phase Locked Loop Design in Hybrid FinFET-Memristor Technology.	UEMCON	2020	DBLP DOI BibTeX RDF
14	Mayank Raj, Yohan Frans, Ping-Chuan Chiang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, Jimmy Grayson, Marc Epitaux, Ken Chang	50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET.	ECOC	2020	DBLP DOI BibTeX RDF
14	M. Aditya, Rishu Chaujar	A Novel GAA Hollow Cavity FinFET based biosensor for Cancer protein marker sensing.	MOCAST	2020	DBLP DOI BibTeX RDF
14	Parag Upadhyaya, Chi Fung Poon, Siok-Wei Lim, Junho Cho, Arianne Roldan, Wenfeng Zhang, Jin Namkoong, Toan Pham, Bruce Xu, Winson Lin, Hongtao Zhang 0002, Nakul Narang, Kee Hian Tan, Geoff Zhang, Yohan Frans, Ken Chang	A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
14	Angie Wang, Woo-Rham Bae, Jaeduk Han, Stevo Bailey, Orhan Ocal, Paul Rigge, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje Nikolic	A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
14	Luke Wang, Yingying Fu, Marc-Andre LaCroix, Euhan Chong, Anthony Chan Carusone	A 64-Gb/s 4-PAM Transceiver Utilizing an Adaptive Threshold ADC in 16-nm FinFET.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
14	Steven Bailey, Paul Rigge, Jaeduk Han, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards, Jonathan Bachrach, Elad Alon, Borivoje Nikolic	A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
14	Umanath Kamath, Edward Cullen, Tao Yu, John Jennings, Susan Wu, Peng Lim, Brendan Farley, Robert Bogdan Staszewski	A 1-V Bandgap Reference in 7-nm FinFET With a Programmable Temperature Coefficient and Inaccuracy of ±0.2% From -45°C to 125°C.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
14	Zheng Guo, Daeyeon Kim, Satyanand Nalam, Jami Wiedemer, Xiaofei Wang, Eric Karl	A 23.6-Mb/mm $^{2}$ SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low-Voltage Applications.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
14	Jihwan Kim, Ajay Balankutty, Rajeev K. Dokania, Amr Elshazly, Hyung Seok Kim, Sandipan Kundu, Dan Shi, Skyler Weaver, Kai Yu 0016, Frank O'Mahony	A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
14	Steven Callender, Stefano Pellerano, Christopher D. Hull	An $E$ -Band Power Amplifier With 26.3% PAE and 24-GHz Bandwidth in 22-nm FinFET CMOS.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
14	Jongwoo Lee, Kiyong Son, Hyungsun Lim, Daechul Jeong, Ilyong Jong, Sanghyun Baek, Jae Hoon Lee, Ronghua Ni, Yongrong Zuo, Chih-Wei Yao, Seungchan Heo, Sangwook Han, Thomas Byunghak Cho, Inyup Kang, Joonhee Lee, Byoungjoong Kang, Jeongyeol Bae, Jaehyuk Jang, Seunghyun Oh, Ji-Soo Chang, Sanghoon Kang	A Sub-6-GHz 5G New Radio RF Transceiver Supporting EN-DC With 3.15-Gb/s DL and 1.27-Gb/s UL in 14-nm FinFET CMOS.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
14	Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Ram K. Krishnamurthy	A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
14	Kai Xu, Feng-Wei Kuo, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen 0001, Robert Bogdan Staszewski	A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
14	Leila Bagheriye, Siroos Toofan, Roghayeh Saeidi, Farshad Moradi	Highly stable, low power FinFET SRAM cells with exploiting dynamic back-gate biasing.	Integr.	2019	DBLP DOI BibTeX RDF
14	Yu-Fan Chiang, Wei-Yu Chien, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin, Ya-Chin King	FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems.	Integr.	2019	DBLP DOI BibTeX RDF
14	Michail Noltsis, Eleni Maragkoudaki, Dimitrios Rodopoulos, Francky Catthoor, Dimitrios Soudris	Failure probability of a FinFET-based SRAM cell utilizing the most probable failure point.	Integr.	2019	DBLP DOI BibTeX RDF
14	Mahmoud S. Badran, Hanady Hussien Issa, Saleh M. Eisa, Hani Fikry Ragai	Low Leakage Current Symmetrical Dual-k 7 nm Trigate Bulk Underlap FinFET for Ultra Low Power Applications.	IEEE Access	2019	DBLP DOI BibTeX RDF
14	Freddy Forero, Hector Villacorta, Michel Renovell, Víctor H. Champac	Modeling and Detectability of Full Open Gate Defects in FinFET Technology.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
14	Abdullah Guler, Niraj K. Jha	Three-Dimensional Monolithic FinFET-Based 8T SRAM Cell Design for Enhanced Read Time and Low Leakage.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
14	Daniel Kraak, Mottaqiallah Taouil, Innocent Agbo, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor	Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
14	Randy W. Mann, Meixiong Zhao, Sanjay Parihar, Qun Gao, Ankur Arya, Carl Radens, Shesh Mani Pandey, Joseph Versaggi, Jack M. Higman, Rick Carter	An Extrinsic Device and Leakage Mechanism in Advanced Bulk FinFET SRAM.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
14	Vijay Kumar Magraiya, Tarun Kumar Gupta	ONOFIC Pull-Up Approach in Domino Logic Circuits Using FinFET for Subthreshold Leakage Reduction.	Circuits Syst. Signal Process.	2019	DBLP DOI BibTeX RDF
14	Jay Pathak, Anand D. Darji	Assessment of interface traps in In0.53Ga0.47As FinFET with gate-to-source/drain underlap for sub-14 nm technology node to impede short channel effect.	IET Circuits Devices Syst.	2019	DBLP DOI BibTeX RDF
14	Spandana Rachamalla, Shashidhar Reddy, Arun Joseph	Heterogeneity aware power abstractions for dynamic power dominated FinFET-based microprocessors.	IET Comput. Digit. Tech.	2019	DBLP DOI BibTeX RDF
14	V. M. Senthilkumar, A. Muruganandham, S. Ravindrakumar, N. S. Gowri Ganesh	FINFET operational amplifier with low offset noise and high immunity to electromagnetic interference.	Microprocess. Microsystems	2019	DBLP DOI BibTeX RDF
14	J. K. Kasthuri Bha, P. Aruna Priya	Low power & high gain differential amplifier using 16 nm FinFET.	Microprocess. Microsystems	2019	DBLP DOI BibTeX RDF
14	V. M. Senthilkumar, S. Ravindrakumar, D. Nithya, N. V. Kousik	A vedic mathematics based processor core for discrete wavelet transform using FinFET and CNTFET technology for biomedical signal processing.	Microprocess. Microsystems	2019	DBLP DOI BibTeX RDF
14	Sandeep Garg, Tarun Kumar Gupta	A New Technique for Designing Low-Power High-Speed Domino Logic Circuits in FinFET Technology.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
14	Vijay Kumar Magraiya, Tarun Kumar Gupta	ONOFIC-based leakage reduction technique for FinFET domino circuits.	Int. J. Circuit Theory Appl.	2019	DBLP DOI BibTeX RDF
14	Sandeep Garg, Tarun Kumar Gupta	FDSTDL: Low-power technique for FinFET domino circuits.	Int. J. Circuit Theory Appl.	2019	DBLP DOI BibTeX RDF
14	G. Cardoso Medeiros, E. Brum, Leticia Bolzani Poehls, Thiago Copetti, Tiago R. Balen	Evaluating the Impact of Temperature on Dynamic Fault Behaviour of FinFET-Based SRAMs with Resistive Defects.	J. Electron. Test.	2019	DBLP DOI BibTeX RDF
14	Wei-feng Lü, Liang Dai	Impact of work-function variation on analog figures-of-merits for high-k/metal-gate junctionless FinFET and gate-all-around nanowire MOSFET.	Microelectron. J.	2019	DBLP DOI BibTeX RDF
14	Chengying Han, Xuejie Shi, Qiyu Huang	Optimization of short channel effect and external resistance on small size FinFET for different threshold voltage flavors and supply voltages.	Microelectron. J.	2019	DBLP DOI BibTeX RDF