Search results for "timing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
27	Rajeev Murgai	Net Buffering in the Presence of Multiple Timing Views.	VLSI Design	2004	DBLP DOI BibTeX RDF
27	Ashwin K. Kumaraswamy, Ahmet T. Erdogan, Indrajit Atluri	Development of Timing Driven IP Design Flow based on Physical Knowledge Synthesis.	IWSOC	2004	DBLP DOI BibTeX RDF
27	Ken S. Stevens, Ran Ginosar, Shai Rotem	Relative timing [asynchronous design].	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
27	Hai Zhou 0001	Timing Verification with Crosstalk for Transparently Latched Circuits.	DATE	2003	DBLP DOI BibTeX RDF
27	David Guerrero Martos, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán 0001	Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits.	PATMOS	2003	DBLP DOI BibTeX RDF
27	Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Alex Kondratyev, Luciano Lavagno, Ken S. Stevens, Alexander Taubin, Alexandre Yakovlev	Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
27	H. Chang, Eugene Shragowitz, Jian Liu, Habib Youssef, Bing Lu, Suphachai Sutanthavibul	Net criticality revisited: an effective method to improve timing in physical design.	ISPD	2002	DBLP DOI BibTeX RDF	criticality metrics, net delay bound, routing, placement
27	Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh	Timing-driven placement using design hierarchy guided constraint generation.	ICCAD	2002	DBLP DOI BibTeX RDF
27	Paul Kartschoke, Shervin Hojat	Techniques that Improved the Timing Convergence of the Gekko PowerPC Microprocessor.	ISQED	2001	DBLP DOI BibTeX RDF
27	Johan Agat	Transforming Out Timing Leaks.	POPL	2000	DBLP DOI BibTeX RDF
27	Shervin Hojat, Paul Kartschoke	Techniques for Improving Timing Convergence of Advanced Microprocessors.	EUROMICRO	2000	DBLP DOI BibTeX RDF
27	Bruno Franzini, Cristiano Forzan, Davide Pandini, Primo Scandolara, Alessandro Dal Fabbro	Crosstalk Aware Static Timing Analysis: A Two Step Approach.	ISQED	2000	DBLP DOI BibTeX RDF
27	Shih-Lian T. Ou, Massoud Pedram	Timing-driven placement based on partitioning with dynamic cut-net control.	DAC	2000	DBLP DOI BibTeX RDF
27	David L. Harris, Mark Horowitz, Dean Liu	Timing analysis including clock skew.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
27	Hyosoon Lee, Heonshik Shin, Sang Lyul Min	Worst Case Timing Requirement of Real-Time Tasks with Time Redundancy.	RTCSA	1999	DBLP DOI BibTeX RDF	Fault Tolerance, Real-Time Scheduling, Rollback Recovery, Time Redundancy
27	Yuji Kukimoto, Robert K. Brayton	Timing-safe false path removal for combinational modules.	ICCAD	1999	DBLP DOI BibTeX RDF
27	S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, Donald Cottrell, David Mallis, S. DasGupta, Joseph Morrell, Amrich Chokhavtia	CHDStd - application support for reusable hierarchical interconnect timing views.	ISPD	1998	DBLP DOI BibTeX RDF
27	Peter A. Walker, Sumit Ghosh	On the nature and inadequacies of transport timing delay constructs in VHDL descriptions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
27	Kris Gaj, Eby G. Friedman, Marc J. Feldman	Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
27	Kathi Fisler	Containing of Regular Languages in Non-Regular Timing Diagram Languages is Decidable.	CAV	1997	DBLP DOI BibTeX RDF
27	Pierre Girodias, Eduard Cerny	Interface timing verification with delay correlation using constraint logic programming.	ED&TC	1997	DBLP DOI BibTeX RDF
27	Pranav Ashar, Sharad Malik	Functional timing analysis using ATPG.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
27	Costas Courcoubetis, Werner Damm, Bernhard Josko	Verification of timing Properties of VHDL.	CAV	1993	DBLP DOI BibTeX RDF
27	Nicholas Weiner, Alberto L. Sangiovanni-Vincentelli	Timing Analysis in a Logic Synthesis Environment.	DAC	1989	DBLP DOI BibTeX RDF
27	Michael Burstein, Mary N. Youssef	Timing influenced layout design.	DAC	1985	DBLP DOI BibTeX RDF
27	Dimitrios Karayiannis, Spyros Tragoudas	Uniform area timing-driven circuit implementation.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	circuit module, cell library, input-output paths, overall area, timing-driven circuit implementation, computational complexity, heuristics, CAD, delays, timing, sequential circuits, sequential circuits, NP-hard, directed graphs, combinational circuits, combinational circuits, logic CAD, polynomial time algorithm, directed acyclic graphs, circuit CAD, cellular arrays, propagation delay
26	Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown	Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
26	Liuqing Yang 0001, Georgios B. Giannakis, Ananthram Swami	Noncoherent Ultra-Wideband (De)Modulation.	IEEE Trans. Commun.	2007	DBLP DOI BibTeX RDF
26	Sangho Ahn, Sanghun Kim, Hyoung-Kee Choi, Sun Yong Kim, Seokho Yoon	A Novel Frequency Offset Estimation Algorithm Using Differential Combining for OFDM-Based WLAN Systems.	International Conference on Computational Science (4)	2007	DBLP DOI BibTeX RDF	frequency offset estimation, WLAN, OFDM
26	Min (Leon) Li, Tanja Van Achteren, Erik Brockmeyer, Francky Catthoor	Statistical Performance Analysis and Estimation of Coarse Grain Parallel Multimedia Processing System.	IEEE Real Time Technology and Applications Symposium	2006	DBLP DOI BibTeX RDF
26	Katsunori Kitano, Hiroshi Okamoto, Tomoki Fukai	Time representing cortical activities: two models inspired by prefrontal persistent activity.	Biol. Cybern.	2003	DBLP DOI BibTeX RDF
26	Amanda R. Bolbecker, Zixi Cheng, Gerald S. Wasserman	Time versus size: which characteristic of a neural response carries more information?	Biol. Cybern.	2003	DBLP DOI BibTeX RDF
26	Bill Halpin, Naresh Sehgal, C. Y. Roger Chen	Detailed Placement with Net Length Constraints.	IWSOC	2003	DBLP DOI BibTeX RDF
26	Michael D. Moffitt, David A. Papa, Zhuo Li 0001, Charles J. Alpert	Path smoothing via discrete optimization.	DAC	2008	DBLP DOI BibTeX RDF	static timing analysis, timing-driven placement
26	Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy	Fsimac: a fault simulator for asynchronous sequential circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	Fsimac, gate-level fault simulator, Muller C-elements, complex domino gates, high-speed design, min-max timing analysis, min-max rime stamps, CA-BIST, waveform model, logic testing, built-in self test, timing, cellular automata, Cellular Automata, sequential circuits, iterative methods, fault simulation, fault simulator, asynchronous circuits, stuck-at faults, iterations, delay faults, combinational logic, feedback loops, pseudo-random tests, gate-delay faults, asynchronous sequential circuits
26	Hoon Chang, Jacob A. Abraham	An Efficient Critical Path Tracing Algorithm for Designing High Performance Vlsi Systems.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	timing analysis, automatic test generation, timing verification
26	Oscar González 0002, H. Shrikumar, John A. Stankovic, Krithi Ramamritham	Adaptive fault tolerance and graceful degradation under dynamic hard real-time scheduling.	RTSS	1997	DBLP DOI BibTeX RDF	adaptive fault tolerance, dynamic hard real-time scheduling, static redundancy allocation, variable environments, redundancy strategy, radar tracking software, AWACS, early warning aircraft, timing-centric performance metric, quality of service, fault tolerant computing, timing constraints, temporal constraints, resource constraints, QoS guarantees, graceful degradation
26	Scott Dawson, Farnam Jahanian, Todd Mitton	Fault injection experiments on real-time protocols using ORCHESTRA.	HASE	1996	DBLP DOI BibTeX RDF	fault injection experiments, ORCHESTRA software fault injection environment, Unix sockets, Real Time Mach, fault injection mechanism, timing intrusiveness, fault tolerance, software fault tolerance, timing behavior, real time protocols, operating system support
26	Neil C. Audsley, I. J. Bate, Alan Burns 0001	Putting fixed priority scheduling theory into engineering practice for safety critical applications.	IEEE Real Time Technology and Applications Symposium	1996	DBLP DOI BibTeX RDF	aircraft computers, engineering practice, industrial safety-critical hard real-time systems, class A systems, civil aircraft software standard DO178B, evidence gathering, technical benefits, evidence presentation, scheduling, real-time systems, timing, certification, safety-critical software, fixed-priority scheduling, aerospace computing, certification authorities, software standards, timing requirements
26	Chris J. Myers, Peter A. Beerel, Teresa H.-Y. Meng	Technology mapping of timed circuits.	ASYNC	1995	DBLP DOI BibTeX RDF	gate library, C-elements, ATACS, timing, logic design, logic CAD, asynchronous circuits, asynchronous circuits, timing information, AND gates, synthesis tool, OR gates, timed circuits
26	H. A. Xie, Kevin E. Forward, K. M. Adams, Suthikshn Kumar	An SBus Multi-Tracer and its applications.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	SBus Multi Tracer, SBus monitoring board, logic analyzer, bus analyzer, trace length, board memory, multi occurrences, trigger patterns, multiple partitions, tracing memory, systematic timing information, pattern occurrences, triggering patterns, SUN SPARC station, field programmable gate arrays, Field Programmable Gate Array, FPGA, logic testing, automatic test equipment, system buses, timing diagrams, computerised monitoring
26	Rainer Leupers, Peter Marwedel	Time-constrained code compaction for DSPs.	ISSS	1995	DBLP DOI BibTeX RDF	code generation techniques, digital signal processing algorithms, encoding restrictions, exact timing behavior, hard real-time constraints, integer programming model, local code compaction, programmable DSP, rigid heuristics, time-constrained code compaction, real-time systems, timing, integer programming, instruction-level parallelism, source coding, automatic programming, digital signal processing chips, side-effects
26	Jay K. Adams, John Alan Miller, Donald E. Thomas	Execution-time profiling for multiple-process behavioral synthesis.	ICCD	1995	DBLP DOI BibTeX RDF	execution-time profiling, multiple-process behavioral synthesis, back-annotating, source description, behavioral simulation model, annotated behavioral simulation, high level synthesis, high-level synthesis, timing, timing, logic CAD, digital simulation, circuit analysis computing, hardware design, software profiling, register-transfer level model
26	George S. Avrunin, James C. Corbett, Laura K. Dillon, Jack C. Wileden	Automated Derivation of Time Bounds in Uniprocessor Concurrent Systems.	IEEE Trans. Software Eng.	1994	DBLP DOI BibTeX RDF	time bound derivation, uniprocessor concurrent systems, concurrent software system, single processor, arbitrary scheduling, integer programming methods, constrained expression toolset, very large state spaces, scheduling, real-time systems, lower bounds, concurrency control, integer programming, systems analysis, upper bounds, timing analysis, concurrent systems, linear inequalities, timing properties, finite state systems, complex real-time systems
26	Alan C. Shaw	Reasoning About Time in Higher-Level Language Software.	IEEE Trans. Software Eng.	1989	DBLP DOI BibTeX RDF	higher-level language software, program elements, time-related statements, timing invariants, periodic processes, real-time systems, real-time, formal specification, synchronization, specification, lower bounds, delay, concurrent programs, synchronisation, upper bounds, assertions, deadlines, execution times, computer times, formal logic, Hoare logic, timing bounds, sequential programs
25	Luís Guerra e Silva, Joel R. Phillips, L. Miguel Silveira	Speedpath analysis under parametric timing models.	DAC	2010	DBLP DOI BibTeX RDF	parametric timing models, speedpath analysis
25	Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang	Lens aberration aware placement for timing yield.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Layout, design for manufacturing, lithography, timing yield
25	Luca Sterpone	Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs.	ARC	2009	DBLP DOI BibTeX RDF	fault tolerance, FPGA, Single Event Upset, Triple Modular Redundancy, Timing-driven Placement
25	Nuno Laranjeiro, Marco Vieira, Henrique Madeira	Predicting Timing Failures in Web Services.	DASFAA Workshops	2009	DBLP DOI BibTeX RDF	timing failures, web services, prediction, detection
25	Peng Sun, Rong Luo	Closed-form solution for timing analysis of process variations on SWCNT interconnect.	SLIP	2009	DBLP DOI BibTeX RDF	interconnect, process variation, timing analysis, carbon nanotube, closed-form
25	Guihai Yan, Yinhe Han 0001, Hui Liu, Xiaoyao Liang, Xiaowei Li 0001	MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency.	ISLPED	2009	DBLP DOI BibTeX RDF	efficiency, DVFS, timing adaptability
25	Sherief Reda, Aung Si, R. Iris Bahar	Reducing the leakage and timing variability of 2D ICcs using 3D ICs.	ISLPED	2009	DBLP DOI BibTeX RDF	3D integrated circuit, timing, variability, leakage
25	Abigail Morrison, Markus Diesmann, Wulfram Gerstner	Phenomenological models of synaptic plasticity based on spike timing.	Biol. Cybern.	2008	DBLP DOI BibTeX RDF	Simulation, Modeling, Learning, Spike-timing dependent plasticity, Short term plasticity
25	Yi Wang, Xuan Zeng 0001, Jun Tao 0001, Hengliang Zhu, Xu Luo, Changhao Yan, Wei Cai 0003	Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model.	ISQED	2008	DBLP DOI BibTeX RDF	adaptive stochastic collocation method, max, process variations, statistical static timing analysis
25	Amit Goel, Sarma B. K. Vrudhula	Statistical waveform and current source based standard cell models for accurate timing analysis.	DAC	2008	DBLP DOI BibTeX RDF	statistical waveform models, process variations, timing analysis
25	Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao	Dose map and placement co-optimization for timing yield enhancement and leakage power reduction.	DAC	2008	DBLP DOI BibTeX RDF	dose map, placement, timing yield, leakage power reduction
25	S. Raja 0002, F. Varadi, Murat R. Becer, Joao Geada	Transistor level gate modeling for accurate and fast timing, noise, and power analysis.	DAC	2008	DBLP DOI BibTeX RDF	gate modeling, timing, statistical, crosstalk, multi threaded
25	Vineeth Veetil, Dennis Sylvester, David T. Blaauw	Efficient Monte Carlo based incremental statistical timing analysis.	DAC	2008	DBLP DOI BibTeX RDF	Monte Carlo, variance reduction, statistical timing
25	Antonio Fernández 0001, Ernesto Jiménez, Michel Raynal, Gilles Trédan	A Timing Assumption and a t-Resilient Protocol for Implementing an Eventual Leader Service in Asynchronous Shared Memory Systems.	ISORC	2007	DBLP DOI BibTeX RDF	Timer property, Timing assumptions, Fault-tolerance, Shared memory, System model, Asynchronous system, Process crash, Atomic register, Omega, Eventual leader
25	Yoshihiro Miyake, Koji Takano	Internal Timing Mechanism for Real-Time Coordination - Two Types of Control in Synchronized Tapping.	HCI (8)	2007	DBLP DOI BibTeX RDF	Timing control, Synchronized tapping, Attentional resources
25	Kai Zhu 0001	Post-route LUT output polarity selection for timing optimization.	FPGA	2007	DBLP DOI BibTeX RDF	optimization, timing, polarity, FPGA lookup table
25	Bahador Bakhshi, Babak Sadeghiyan	A Timing Attack on Blakley's Modular Multiplication Algorithm, and Applications to DSA.	ACNS	2007	DBLP DOI BibTeX RDF	Blakley’s algorithm, modular multiplication, timing attack, DSA
25	Jianfeng Hu, Tiejun Lv	Low-complexity frequency-domain algorithm for UWB timing.	Mobility Conference	2007	DBLP DOI BibTeX RDF	the multipath channel, timing, DFT, ultra wideband, frequency-domain
25	Limin Shen, Shangping Ren, Feng Li 0017, Yunfeng Mu	A Time and Interaction Model for Open Distributed Timing Computation.	ICA3PP	2007	DBLP DOI BibTeX RDF	distributed timing computation, real-time, event, separation of concerns, message, coordination model
25	Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu 0002, Chung-Kuan Cheng, Michael D. Hutton	Efficient static timing analysis using a unified framework for false paths and multi-cycle paths.	ASP-DAC	2006	DBLP DOI BibTeX RDF	biclique covering, false subgraphs, multi-cycle subgraphs, static timing analysis, time shifting
25	Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir	Refined statistical static timing analysis through.	DAC	2006	DBLP DOI BibTeX RDF	delay correlations, Bayesian learning, statistical timing
25	Huaizhi Wu, Martin D. F. Wong, I-Min Liu	Timing-constrained and voltage-island-aware voltage assignment.	DAC	2006	DBLP DOI BibTeX RDF	voltage assignment, low power, timing, voronoi diagram
25	Ian Broster, Alan Burns 0001, Guillermo Rodríguez-Navas	Timing Analysis of Real-Time Communication Under Electromagnetic Interference.	Real Time Syst.	2005	DBLP DOI BibTeX RDF	TTCAN, probabilistic timing analysis, electromagnetic interference, bus guardian, babbling idiot, dependability, faults, Controller Area Network, CAN
25	Jung Youp Lee, Seok Won Jung, Jongin Lim 0001	Detecting Trapdoors in Smart Cards Using Timing and Power Analysis.	TestCom	2005	DBLP DOI BibTeX RDF	Trapdoor, Smart Card, Timing Analysis, Power Analysis
25	Yuzheng Ding, Peter Suaris, Nan-Chi Chou	The effect of post-layout pin permutation on timing.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA, placement, logic synthesis, timing optimization
25	Kei Ohnishi, Kaori Yoshida	Evolutionary change in developmental timing.	GECCO	2005	DBLP DOI BibTeX RDF	developmental timing, genotype-phenotype-mapping
25	Jianzu Wu, Huiyu Xuan	Optimal Timing of Firms' R&D Investment Under Asymmetric Duopoly: A Real Options and Game-Theoretic Approach.	AAIM	2005	DBLP DOI BibTeX RDF	Optimal timing, R&D Investment, Asymmetric Duopoly, Game Theory, Real Options
25	Vishal Khandelwal, Ankur Srivastava 0001	A general framework for accurate statistical timing analysis considering correlations.	DAC	2005	DBLP DOI BibTeX RDF	correlation, variability, statistical timing
25	Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen	Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining.	DAC	2004	DBLP DOI BibTeX RDF	interconnect pipelining, statistical timing analysis
25	Baosheng Wang, Yong B. Cho, Sassan Tabatabaei, André Ivanov	Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	Timing specifications testing, Test Environment, Tester OTA and yield, High-speed interconnect testing, Yield analysis
25	Kaijian Shi, Graig Godwin	Hybrid hierarchical timing closure methodology for a high performance and low power DSP.	DAC	2003	DBLP DOI BibTeX RDF	chip integration, methodology, DSP, timing closure, placement optimization
25	Zhouyue Pi, Urbashi Mitra	On Blind Timing Acquisition and Channel Estimation for Wideband Multiuser DS-CDMA Systems.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	timing acquisition, multiuser systems, blind algorithms, synchronization, wideband CDMA, channel estimation, QR decompositions, multipath fading, DS-CDMA
25	Emmanuelle Anceaume, Eric Mourgaya	Unreliable Distributed Timing Scrutinizer: Adapting Asynchronous Algorithms to the Environment.	Symposium on Object-Oriented Real-Time Distributed Computing	2002	DBLP DOI BibTeX RDF	performance failures, unreliable distributed timing detector, stable network, asynchronous system
25	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Optimal Timing for Skew-Tolerant High-Speed Domino Logic.	ISVLSI	2002	DBLP DOI BibTeX RDF	keeper, optimal timing, noise, skew, domino logic, dynamic circuit
25	Werner Schindler	A Combined Timing and Power Attack.	Public Key Cryptography	2002	DBLP DOI BibTeX RDF	Montgomery's algorithm, Timing attack, power attack
25	Kouichi Sakurai, Tsuyoshi Takagi	A Reject Timing Attackon an IND-CCA2 Public-Key Cryptosystem.	ICISC	2002	DBLP DOI BibTeX RDF	EPOC-2, reject function, Manger's attack, factoring, timing attack, chosen ciphertext attack
25	Minsoo Ryu, Jungkeun Park, Seongsoo Hong	Timing Constraint Remapping to Achieve Time Equi-Continuity in Distributed Real-Time Systems.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	timing constraint transformation, real-time scheduling, clock synchronization, Distributed real-time system
25	Andrés Terrasa, Ana García-Fornes, Vicente J. Botti	Including user-defined timing exception support in FRTL.	RTCSA	2000	DBLP DOI BibTeX RDF	user-defined timing exception support, FRTL, flexible hard real-time systems, task deadlines, Flexible Real-Time Linux, CPU consumption, real-time systems, Unix, exception handling, worst-case execution time, operating systems (computers), run-time system, feasibility test
25	Narendra V. Shenoy, Mahesh A. Iyer, Robert F. Damiano, Kevin Harer, Hi-Keung Tony Ma, Paul Thilking	A Robust Solution to the Timing Convergence Problem in High-Performance Design.	ICCD	1999	DBLP DOI BibTeX RDF	timing convergence, maximum capacitance, synthesis, placement, design-rules
25	V. Chandramouli, Jesse Whittemore, Karem A. Sakallah	AFTA: A Formal Delay Model for Functional Timing Analysis.	DATE	1998	DBLP DOI BibTeX RDF	timed-automamata, timing analysis, states, delay model, timers
25	Supratik Chakraborty, David L. Dill	More Accurate Polynomial-Time Min-Max Timing Simulation.	ASYNC	1997	DBLP DOI BibTeX RDF	Uncertain component delays, min-max timing simulation, thirteen-valued signal algebra, polynomial-time algorithm
25	Rathish Jayabharathi, Kyung Tek Lee, Jacob A. Abraham	A Novel Solution for Chip-Level Functional Timing Verification.	VTS	1997	DBLP DOI BibTeX RDF	Chip-level Functional Timing Verification, Formal Verification techniques, Critical Path Analysis
25	David B. Stewart, Pradeep K. Khosla	Policy-independent real-time operating system mechanisms for timing error detection, handling and monitoring.	HASE	1996	DBLP DOI BibTeX RDF	supervisory programs, policy independent real time operating system mechanisms, timing error detection, estimated worst case execution times, missed deadline, policy independent mechanisms, real time task monitoring, reschedule operation, monitoring mechanism, 6 ms, 1 Kbyte, hard real time systems, scheduling policies, context switch, error handling
24	Ji Chan Maeng, Jung-Il Kwon, Min-Kyu Sin, Minsoo Ryu	RT-replayer: a record-replay architecture for embedded real-time software debugging.	SAC	2009	DBLP DOI BibTeX RDF	instruction hooking, virtual timestamps, real-time, debugging, timing, embedded, replay, record
24	Hosung (Leo) Kim, John Lillis	A framework for layout-level logic restructuring.	ISPD	2008	DBLP DOI BibTeX RDF	logic resynthesis, timing optimization
24	Ben Lickly, Isaac Liu, Sungjun Kim, Hiren D. Patel, Stephen A. Edwards, Edward A. Lee	Predictable programming on a precision timed architecture.	CASES	2008	DBLP DOI BibTeX RDF	pipeline, memory hierarchy, timing predictability
24	Karthik Lakshmanan, Raj Rajkumar	Distributed Resource Kernels: OS Support for End-To-End Resource Isolation.	IEEE Real-Time and Embedded Technology and Applications Symposium	2008	DBLP DOI BibTeX RDF	distributed real-time, resource kernels, timing guarantees, operating system abstractions, resource reservation, performance isolation
24	Samrat S. Batth, Elisangela Rodrigues Vieira, Ana R. Cavalli, M. Ümit Uyar	Specification of Timed EFSM Fault Models in SDL.	FORTE	2007	DBLP DOI BibTeX RDF	Timing Fault Models, Hit-or-Jump, SDL, Extended Finite State Machines
24	Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm	Worst-case circuit delay taking into account power supply variations.	DAC	2004	DBLP DOI BibTeX RDF	voltage fluctuations, static timing analysis, power grid
24	Jindrich Zejda, Paul Frain	General framework for removal of clock network pessimism.	ICCAD	2002	DBLP DOI BibTeX RDF	clock network reconvergence, voltage and temperature delay variation, process, static timing analysis, deep sub-micron
24	Michael Ward, Neil C. Audsley	Hardware implementation of the Ravenscar Ada tasking profile.	CASES	2002	DBLP DOI BibTeX RDF	FPGA, timing, hardware compilation
24	Hans Eisenmann, Frank M. Johannes	Generic Global Placement and Floorplanning.	DAC	1998	DBLP DOI BibTeX RDF	verification, timing, design methodology, microprocessor
24	Michael Münch, Norbert Wehn, Manfred Glesner	An efficient ILP-based scheduling algorithm for control-dominated VHDL descriptions.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	scheduling, timing constraints, integer linear programming (ILP)
24	Tai M. Chung, Henry G. Dietz	Language Constructs and Transformation for Hard Real-time Systems.	Workshop on Languages, Compilers, & Tools for Real-Time Systems	1995	DBLP DOI BibTeX RDF	timing constraint, hard real-time, CHaRTS, real-time language
24	Po-Hao Wang, Shang-Jen Tsai, Rizal Tanjung, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen	Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors.	Integr.	2016	DBLP DOI BibTeX RDF