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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 3674 occurrences of 1433 keywords
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Results
Found 5812 publication records. Showing 5812 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
22 | Suboh A. Suboh, Mohamed Bakhouya, Tarek A. El-Ghazawi |
Simulation and Evaluation of On-Chip Interconnect Architectures: 2D Mesh, Spidergon, and WK-Recursive Network. |
NOCS |
2008 |
DBLP DOI BibTeX RDF |
System on Chip, Network on Chip, Modeling and simulation, On Chip Interconnects |
22 | Akiko Mineyama, Hiroyuki Ito, Takahiro Ishii, Kenichi Okada, Kazuya Masu |
LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Haile Yu |
FPGA interconnect sizing using extended logical effort model. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Hongbo Zeng, Jun Wang, Ge Zhang 0007, Weiwu Hu |
An interconnect-aware power efficient cache coherence protocol for CMPs. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Partha Pratim Pande, Amlan Ganguly, Benjamin Belzer, Alireza Nojeh, André Ivanov |
Novel interconnect infrastructures for massive multicore chips - an overview. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Jingye Xu, Abinash Roy, Masud H. Chowdhury |
Optimization technique for flip-flop inserted global interconnect. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Ethiopia Nigussie, Juha Plosila, Jouni Isoaho |
Area efficient delay-insensitive and differential current sensing on-chip interconnect. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Alexander D. Rast, Shufan Yang, Muhammad Mukaram Khan, Stephen B. Furber |
Virtual synaptic interconnect using an asynchronous network-on-chip. |
IJCNN |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk |
Global interconnections in FPGAs: modeling and performance analysis. |
SLIP |
2008 |
DBLP DOI BibTeX RDF |
FPGA, throughput, interconnection, wave-pipelined |
22 | Zhijian Lu, Wei Huang 0004, Mircea R. Stan, Kevin Skadron, John C. Lach |
Interconnect Lifetime Prediction for Reliability-Aware Systems. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
22 | James D. Ma, Rob A. Rutenbar |
Interval-Valued Reduced-Order Statistical Interconnect Modeling. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Wendemagegnehu T. Beyene |
Application of Artificial Neural Networks to Statistical Analysis and Nonlinear Modeling of High-Speed Interconnect Systems. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Martin Saint-Laurent |
A Model for Interlevel Coupling Noise in Multilevel Interconnect Structures. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Stephan Bourduas, Zeljko Zilic |
A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing. |
NOCS |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Dimitrios N. Serpanos, Wayne H. Wolf |
VLSI models of network-on-chip interconnect. |
VLSI-SoC |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Yasunao Katayama, Atsuya Okazaki |
Optical Interconnect Opportunities for Future Server Memory Systems. |
HPCA |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Nancy Ying Zhou, Zhuo Li 0001, Yuxin Tian, Weiping Shi, Frank Liu 0001 |
A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Xiaojun Yang, Dongdong Wu, Ninghui Sun |
Design of NIC Based on I/O Processor for Cluster Interconnect Network. |
IEEE NAS |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Gayatri Mehta, Justin Stander, Mustafa Baz, Brady Hunsaker, Alex K. Jones |
Interconnect Customization for a Coarse-grained Reconfigurable Fabric. |
IPDPS |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Fan Yang 0001, Xuan Zeng 0001, Yangfeng Su, Dian Zhou |
RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Ling Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng |
Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Mosin Mondal, Tamer Ragheb, Xiang Wu, Adnan Aziz, Yehia Massoud |
Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Jud Leonard, Avi Purkayastha, Matt Reilly, Tushar Mohan |
The software interface for a cluster interconnect based on the Kautz digraph. |
CLUSTER |
2007 |
DBLP DOI BibTeX RDF |
|
22 | I-Jye Lin, Tsui-Yee Ling, Yao-Wen Chang |
Statistical circuit optimization considering device andinterconnect process variations. |
SLIP |
2007 |
DBLP DOI BibTeX RDF |
gate and wire sizing, statistical optimization |
22 | Shuhei Amakawa, Takumi Uezono, Takashi Sato, Kenichi Okada, Kazuya Masu |
Adaptable wire-length distribution with tunable occupation probability. |
SLIP |
2007 |
DBLP DOI BibTeX RDF |
wire-length distribution, rent's rule |
22 | Pyoungwoo Min, Hyunbean Yi, Jaehoon Song, Sanghyeon Baeg, Sungju Park |
Efficient Interconnect Test Patterns for Crosstalk and Static Faults. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Jack R. Smith, Tian Xia, Charles E. Stroud |
An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults. |
J. Electron. Test. |
2006 |
DBLP DOI BibTeX RDF |
stuck-at faults, bridging faults, delay faults |
22 | Soroush Abbaspour, Hanif Fatemi, Massoud Pedram |
Non-gaussian statistical interconnect timing analysis. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera |
Interconnect RL extraction at a single representative frequency. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Kenta Yamada, Noriaki Oda |
Statistical corner conditions of interconnect delay (corner LPE specifications). |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Ahmad Khonsari, Mohamed Ould-Khaoua, Abbas Nayebi, Hamid Sarbazi-Azad |
The impacts of timing constraints on virtual channels multiplexing in interconnect networks. |
IPCCC |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Rod Fatoohi, Subhash Saini, Robert Ciotti |
Interconnect performance evaluation of SGI Altix 3700 BX2, Cray XI, Cray Opteron Cluster, and Dell PowerEdge. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Xiaoji Ye, Peng Li 0001, Frank Liu 0001 |
Practical variation-aware interconnect delay and slew analysis for statistical timing verification. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Vasilis F. Pavlidis, Eby G. Friedman |
Via placement for minimum interconnect delay in three-dimensional (3D) circuits. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai |
Quasi-One-Step Gauss-Jacobi Method for Large-Scale Interconnect Analysis via RLCG-MNA Formulation. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Laureline David, Stephane Martin, Corinne Cregut, Eric Balossier, Frederic Nyer, Fabrice Huret |
Pre-Layout Inductive Corners for Advanced Digital Design Interconnect: Modeling and Silicon Validation. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Simon Hollis, Simon W. Moore |
An Asynchronous Interconnect Architecture for Device Security Enhancement. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter |
Interconnect-Aware Coherence Protocols for Chip Multiprocessors. |
ISCA |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Dharin Shah, Kothamasu Siva, G. Girishankar, N. S. Nagaraj |
Optimizing Interconnect for Performance in Standard Cell Library. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Abinash Roy, Masud H. Chowdhury |
Impacts of Inductance on the Figures of Merit to Optimize Global Interconnect. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry |
POMR: a power-aware interconnect optimization methodology. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Renqiu Huang, Ranga Vemuri |
Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Grzegorz Tosik, Zbigniew Lisik, Malgorzata Langer, Janusz Wozny |
Simulation of Parasitic Interconnect Capacitance for Present and Future ICs. |
International Conference on Computational Science (1) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Brock J. LaMeres, Sunil P. Khatri |
Broadband Impedance Matching for Inductive Interconnect in VLSI Packages. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Guoqing Chen, Eby G. Friedman |
A Fourier series-based RLC interconnect model for periodic signals. |
ISCAS (4) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Meigen Shen, Li-Rong Zheng 0001, Esa Tjukanoff, Jouni Isoaho, Hannu Tenhunen |
Case study of interconnect analysis for standing wave oscillator design. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Res Saleh |
Effect of traffic localization on energy dissipation in NoC-based interconnect. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Mohammad S. Sharawi, Daniel N. Aloi |
An 800 Mbps system interconnect modeling and simulation for high speed computing. |
ISCAS (6) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang |
Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity. |
ISCAS (5) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip J. Restle, Mary Yvonne Lanzerotti |
Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
load capacitance, routing, application specific integrated circuit (ASIC), clock, power dissipation |
22 | Vishak Venkatraman, Wayne P. Burleson |
Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda |
Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Vinita V. Deodhar, Jeffrey A. Davis |
Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Lei Li, Zheng Cao, Mingyu Chen 0001, Jianping Fan 0002 |
A Reconfigurable Optical Interconnect System for DSAG. |
PDCAT |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Andrew Lines |
Asynchronous Interconnect for Synchronous SoC Design. |
IEEE Micro |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Arif Ishaq Abou-Seido, Brian Nowak, Chris Chong-Nuen Chu |
Fitted Elmore delay: a simple and accurate interconnect delay model. |
IEEE Trans. Very Large Scale Integr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Luca Daniel, Chin Siong Ong, Sok Chay Low, Kwok Hong Lee, Jacob K. White 0001 |
A multiparameter moment-matching model-reduction approach for generating geometrically parameterized interconnect performance models. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas |
Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Yang Jiangping, Li Guixiang, Wang Wanglei |
A model of VLSI interconnect test based on boundary scan. |
ICARCV |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Tsung-Hao Chen, Jeng-Liang Tsai, Tanay Karnik |
HiSIM: hierarchical interconnect-centric circuit simulator. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Hong Shin Jun, Sung Soo Chung, Sang H. Baeg |
Removing JTAG Bottlenecks in System Interconnect Test. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Marghoob Mohiyuddin, Amit Prakash, Adnan Aziz, Wayne H. Wolf |
Synthesizing interconnect-efficient low density parity check codes. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
error correcting codes, low-density parity-check codes, routing congestion |
22 | James D. Meindl |
Interconnect Opportunities for Gigascale Integration. |
IEEE Micro |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu 0001, Sung-Mo Kang |
Noise-aware interconnect power optimization in domino logic synthesis. |
IEEE Trans. Very Large Scale Integr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
22 | M. A. Azadpour, T. S. Kalkur |
A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect. |
IEEE Trans. Very Large Scale Integr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
22 | M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni |
A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Eugeni Isern 0001, Miquel Roca 0001, Francesc Moll |
Analysis of the Contribution of Interconnect Effects in the Energy Dissipation of VLSI Circuits. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Andrea Lodi 0002, Luca Ciccarelli, Andrea Cappelli, Fabio Campi, Mario Toma |
Decoder-Based Multi-Context Interconnect Architecture. |
ISVLSI |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Muddu |
A Novel Metric for Interconnect Architecture Performance. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Michael Bedford Taylor, Walter Lee, Saman P. Amarasinghe, Anant Agarwal |
Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture. |
HPCA |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao |
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Osvaldo Colavin, Davide Rizzo |
A scalable wide-issue clustered VLIW with a reconfigurable interconnect. |
CASES |
2003 |
DBLP DOI BibTeX RDF |
clustered VLIW, reconfigurable co-processor (RCP), modulo scheduling, IDCT |
22 | Mohamed A. Elgamel, Kannan S. Tharmalingam, Magdy A. Bayoumi |
Noise-constrained interconnect optimization for nanometer technologies. |
ISCAS (5) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Tianxu Zhao, Xuchao Duan, Yue Hao, Peijun Ma |
Reliability Estimation Model of ICs Interconnect Based on Uniform Distribution of Defects on a Chip. |
DFT |
2003 |
DBLP DOI BibTeX RDF |
interconnection lifetime, electromigration effect, defect |
22 | Takashi Sato, Hiroo Masuda |
Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay. |
ISQED |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Chung-Seok (Andy) Seo, Abhijit Chatterjee |
Free-Space Optical Interconnect for High-Performance MCM Systems. |
IWSOC |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Rajesh Kumar 0006 |
Interconnect and noise immunity design for the Pentium 4 processor. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang |
Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing. |
SLIP |
2003 |
DBLP DOI BibTeX RDF |
?-geometry routing, ?-geometry-driven placement, wirelength reduction estimation |
22 | Joni Dambre, Dirk Stroobandt, Jan Van Campenhout |
Fast estimation of the partitioning rent characteristic using a recursive partitioning model. |
SLIP |
2003 |
DBLP DOI BibTeX RDF |
a priori wire length prediction, recursive circuit partitioning, graph bipartitioning |
22 | Alan E. Charlesworth |
The Sun Fireplane Interconnect. |
IEEE Micro |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Jason Cong, David Zhigang Pan |
Wire width planning for interconnect performance optimization. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Stuart McCracken, Zeljko Zilic |
FPGA test time reduction through a novel interconnect testing scheme. |
FPGA |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng |
Physical Planning Of On-Chip Interconnect Architectures. |
ICCD |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Chu |
Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model. |
ICCD |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Charles E. Stroud, Jeremy Nall, Matthew Lashinsky, Miron Abramovici |
BIST-Based Diagnosis of FPGA Interconnect. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Hans Eberle, Nils Gura |
Separated high-bandwidth and low-latency communication in the cluster interconnect Clint. |
SC |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Yuanyuan Yang 0001, Jianchao Wang |
WDM Optical Interconnect Architectures Under Two Connection Models. |
Hot Interconnects |
2002 |
DBLP DOI BibTeX RDF |
optical inter-connects, permutation, network architectures, Wavelength-division-multiplexing (WDM), wavelength conversion |
22 | Steven L. Teig |
The X architecture: not your father's diagonal wiring. |
SLIP |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Jason Cong, Lei He 0001, Cheng-Kok Koh, David Zhigang Pan |
Interconnect sizing and spacing with consideration of couplingcapacitance. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Probir Sarkar, Cheng-Kok Koh |
Routability-driven repeater block planning for interconnect-centricfloorplanning. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Eun Jung Kim 0001, Ki Hwan Yum, Chita R. Das |
Calculation of Deadline Missing Probability in a QoS Capable Cluster Interconnect. |
NCA |
2001 |
DBLP DOI BibTeX RDF |
|
22 | W. J. Bainbridge, Stephen B. Furber |
Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding. |
ASYNC |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Doug Hale, Thomas J. Overbye |
Optimization and Visualization of the North American Eastern Interconnect Power Market. |
HICSS |
2001 |
DBLP DOI BibTeX RDF |
electric restructuring, OPF, power system visualization, power markets |
22 | Alan E. Charlesworth |
The sun fireplane system interconnect. |
SC |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Arifur Rahman, Shamik Das, Anantha P. Chandrakasan, Rafael Reif |
Wiring requirement and three-dimensional integration of field-programmable gate arrays. |
SLIP |
2001 |
DBLP DOI BibTeX RDF |
3-D integrated circuits, FPGA, system-level modeling, wire-length |
22 | Sek M. Chai, Tarek M. Taha, D. Scott Wills, James D. Meindl |
Heterogeneous architecture models for interconnect-motivated system design. |
IEEE Trans. Very Large Scale Integr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Markus Fischer 0001, Ulrich Brüning 0001, Jörg Kluge, Lars Rzymianowicz, Patrick R. Schulz, Mathias Waack |
ATOLL, a New Switched, High Speed Interconnect in Comparison to Myrinet and SCI. |
IPDPS Workshops |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl |
Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion. |
ISLPED |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu 0001, Sung-Mo Kang |
Noise-aware power optimization for on-chip interconnect. |
ISLPED |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Jason Cong, David Zhigang Pan |
Interconnect Delay Estimation Models for Synthesis and Design Planning. |
ASP-DAC |
1999 |
DBLP DOI BibTeX RDF |
|
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