Search results for "subthreshold"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
15	Xiaoxia Wu, Feng Wang 0004, Yuan Xie 0001	Analysis of Subthreshold Finfet Circuits for Ultra-Low Power Design.	SoCC	2006	DBLP DOI BibTeX RDF
15	Kristian Granhaug, Snorre Aunet	Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates.	DFT	2006	DBLP DOI BibTeX RDF
15	Ryota Kobayashi, Shigeru Shinomoto	Predicting spike times from subthreshold dynamics of a neuron.	NIPS	2006	DBLP BibTeX RDF
15	Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri	A PLA based asynchronous micropipelining approach for subthreshold circuit design.	DAC	2006	DBLP DOI BibTeX RDF	micro-pipelining, asynchronous, PLA, sub-threshold
15	Alice Wang, Anantha P. Chandrakasan	A 180-mV subthreshold FFT processor using a minimum energy design methodology.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
15	Benton H. Calhoun, Alice Wang, Anantha P. Chandrakasan	Modeling and sizing for minimum energy operation in subthreshold circuits.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
15	Xuedong Zhang, Laurel H. Carney	Response Properties of an Integrate-and-Fire Model That Receives Subthreshold Inputs.	Neural Comput.	2005	DBLP DOI BibTeX RDF
15	Ofer Melamed, Gilad Silberberg, Henry Markram, Wulfram Gerstner, Magnus J. E. Richardson	Subthreshold cross-correlations between cortical neurons: A reference model with static synapses.	Neurocomputing	2005	DBLP DOI BibTeX RDF
15	Francisco Serra-Graells, José Luis Huertas	Low-Voltage CMOS subthreshold log-domain filtering.	IEEE Trans. Circuits Syst. I Regul. Pap.	2005	DBLP DOI BibTeX RDF
15	Aimad El Mourabit, Guo-Neng Lu, Patrick Pittet	Wide-Linear-Range Subthreshold OTA for Low-Power, Low-Voltage, and Low-Frequency Applications.	IEEE Trans. Circuits Syst. I Regul. Pap.	2005	DBLP DOI BibTeX RDF
15	Aimad El Mourabit, Guo-Neng Lu, Patrick Pittet	A low-frequency, sub 1.5-V micropower Gm-C filter based on subthreshold MIFG MOS transistors.	ESSCIRC	2005	DBLP DOI BibTeX RDF
15	Nikhil Jayakumar, Sunil P. Khatri	A variation tolerant subthreshold design approach.	DAC	2005	DBLP DOI BibTeX RDF	variation-toleran, self-adjusting, body-biasing, sub-threshold
15	Francisco Serra-Graells, Lluís Gómez, José Luis Huertas	A true-1-V 300-μW CMOS-subthreshold log-domain hearing-aid-on-chip.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
15	Siva G. Narendra, Vivek De, Shekhar Borkar, Dimitri A. Antoniadis, Anantha P. Chandrakasan	Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-μm CMOS.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
15	Rajeev R. Rao, Ashish Srivastava, David T. Blaauw, Dennis Sylvester	Statistical analysis of subthreshold leakage current for VLSI circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
15	Zhuoqin Yang, Qishao Lu, Huaguang Gu, Wei Ren	Gwn-Induced bursting, Spiking, and Random subthreshold Impulsing oscillation before Hopf bifurcations in the Chay Model.	Int. J. Bifurc. Chaos	2004	DBLP DOI BibTeX RDF
15	Giancarlo La Camera, Walter Senn, Stefano Fusi	Comparison between networks of conductance- and current-driven neurons: stationary spike rates and subthreshold depolarization.	Neurocomputing	2004	DBLP DOI BibTeX RDF
15	T. K. Chiang	A two-dimensional analytical subthreshold behavior model for short-channel AlGaAs/GaAs HFETs.	Microelectron. Reliab.	2004	DBLP DOI BibTeX RDF
15	Brigitte H. Boudreau, Kevin B. Englehart, Adrian D. C. Chan, Philip A. Parker	Reduction of stimulus artifact in somatosensory evoked potentials: segmented versus subthreshold training.	IEEE Trans. Biomed. Eng.	2004	DBLP DOI BibTeX RDF
15	Manoj Bikumandla, Jaime Ramírez-Angulo, Carlos Urquidi, Ramón González Carvajal, Antonio J. López-Martín	Biasing CMOS amplifiers using MOS transistors in subthreshold region.	IEICE Electron. Express	2004	DBLP DOI BibTeX RDF
15	Carlo Dallavalle	Adaptive Subthreshold Leakage Reduction Through N/P Wells Reverse Biasing.	PATMOS	2004	DBLP DOI BibTeX RDF
15	Aimad El Mourabit, Patrick Pittet, Guo-Neng Lu	A wide-linear range subthreshold OTA based on FGMOS transistor.	ICECS	2004	DBLP DOI BibTeX RDF
15	Benton H. Calhoun, Alice Wang, Anantha P. Chandrakasan	Device sizing for minimum energy operation in subthreshold circuits.	CICC	2004	DBLP DOI BibTeX RDF
15	Volkan Kursun, Eby G. Friedman	Energy efficient dual threshold voltage dynamic circuits employing sleep switches to minimize subthreshold leakage.	ISCAS (2)	2004	DBLP BibTeX RDF
15	Young-Jun Lee, Jihyun Lee, Yong-Bin Kim, Joseph Ayers, Alexander Volkovskii, Allen I. Selverston, Henry D. I. Abarbanel, Mikhail I. Rabinovich	Low power real time electronic neuron VLSI design using subthreshold technique.	ISCAS (4)	2004	DBLP BibTeX RDF
15	Gianluca Giustolisi, Gaetano Palumbo, M. Criscione, F. Cutri	A low-voltage low-power voltage reference based on subthreshold MOSFETs.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
15	Michele Migliore	On the Integration of Subthreshold Inputs from Perforant Path and Schaffer Collaterals in Hippocampal CA1 Pyramidal Neurons.	J. Comput. Neurosci.	2003	DBLP DOI BibTeX RDF
15	Sven Bestmann, Jürgen Baudewig, Hartwig R. Siebner, John C. Rothwell, Jens Frahm	Subthreshold high-frequency TMS of human primary motor cortex modulates interconnected frontal motor areas as detected by interleaved fMRI-TMS.	NeuroImage	2003	DBLP DOI BibTeX RDF
15	Michael Rudolph 0002, Alain Destexhe	Characterization of Subthreshold Voltage Fluctuations in Neuronal Membranes.	Neural Comput.	2003	DBLP DOI BibTeX RDF
15	Tetsuya Asai, Yusuke Kanazawa, Yoshihito Amemiya	A subthreshold MOS neuron circuit based on the Volterra system.	IEEE Trans. Neural Networks	2003	DBLP DOI BibTeX RDF
15	Jaime Ramírez-Angulo, Chandrika Durbha, Gladys Omayra Ducoudray, Ramón González Carvajal	Highly Linear Wide Input Range CMOS OTA Architectures Operating in Subthreshold and Strong Inversion.	VLSI	2003	DBLP BibTeX RDF
15	Arifur Rahman	Models for Full-Chip Power Dissipation in Field Programmable Gate Arrays and the Impact of Subthreshold Leakage Current.	VLSI	2003	DBLP BibTeX RDF
15	Gary B. Levy, William Evans, John Ebner, Patrick Farrell, Mike Hufford, Bryan H. Allison, David Wheeler, Haiqing Lin, Olivier Prache, Eric Naviasky	An 852×600 pixel OLED-on-silicon color microdisplay using CMOS subthreshold-voltage-scaling current drivers.	IEEE J. Solid State Circuits	2002	DBLP DOI BibTeX RDF
15	Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi 0001, Seongsoo Lee, Takayasu Sakurai	VTH-hopping scheme to reduce subthreshold leakage for low-power processors.	IEEE J. Solid State Circuits	2002	DBLP DOI BibTeX RDF
15	Juin J. Liou, R. Shireen, Adelmo Ortiz-Conde, Francisco J. García-Sánchez, Antonio Cerdeira, Xiaofang Gao, Xuecheng Zou, Ching-Sung Ho	Influence of polysilicon-gate depletion on the subthreshold behavior of submicron MOSFETs.	Microelectron. Reliab.	2002	DBLP DOI BibTeX RDF
15	Dorra Sellami Masmoudi, Amadou Tidjane Dieng, Mohamed Masmoudi	A subthreshold mode programmable implementation of the Gaussian function for RBF neural networks applications.	ISIC	2002	DBLP DOI BibTeX RDF
15	Christian K. Machens, Michael Wehr, Anthony M. Zador	Spectro-Temporal Receptive Fields of Subthreshold Responses in Auditory Cortex.	NIPS	2002	DBLP BibTeX RDF
15	Ru Huang, Weihai Bu, Xing Zhang 0002, Yangyuan Wang	Quasi-two-dimensional subthreshold current model of deep submicrometer SOI drive-in gate controlled hybrid transistors with lateral non-uniform doping profile.	Sci. China Ser. F Inf. Sci.	2001	DBLP DOI BibTeX RDF
15	Kirsten E. I. Deurloo, Jan Holsheimer, Piet Bergveld	The effect of subthreshold prepulses on the recruitment order in a nerve trunk analyzed in a simple and a realistic volume conductor model.	Biol. Cybern.	2001	DBLP DOI BibTeX RDF
15	Ludovic Alvado, Jean Tomas, Sylvie Renaud-Le Masson, Vincent Douence	Design of an analogue ASIC using subthreshold CMOS transistors to model biological neurons.	CICC	2001	DBLP DOI BibTeX RDF
15	Francisco Serra-Graells	All-MOS subthreshold log filters.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
15	James T. Kao	Subthreshold leakage control techniques for low power digital circuits.		2001	RDF
15	Peter N. Steinmetz, Amit Manwani, Christof Koch, Michael London, Idan Segev	Subthreshold Voltage Noise Due to Channel Fluctuations in Active Neuronal Membranes.	J. Comput. Neurosci.	2000	DBLP DOI BibTeX RDF
15	Tetsuya Asai, Tomoki Fukai, Shigeru Tanaka	A subthreshold MOS circuit for the Lotka-Volterra neural network producing the winners-share-all solution.	Neural Networks	1999	DBLP DOI BibTeX RDF
15	Rimon Ikeno, Hiroshi Ito, Kunihiro Asada	One-Dimensional Analysis of Subthreshold Characteristics of SOI-MOSFET Considering Quantum Mechanical Effects.	VLSI Design	1998	DBLP DOI BibTeX RDF
15	G. Meinhardt, U. Mortensen	Detection of aperiodic test patterns by pattern specific detectors revealed by subthreshold summation.	Biol. Cybern.	1998	DBLP DOI BibTeX RDF
15	Matthew G. Fishler	The transient far-field response of a discontinuous one-dimensional cardiac fiber to subthreshold stimuli.	IEEE Trans. Biomed. Eng.	1997	DBLP DOI BibTeX RDF
15	Gillian F. Marshall, Steve Collins	Fuzzy logic architecture using subthreshold analogue floating-gate devices.	IEEE Trans. Fuzzy Syst.	1997	DBLP DOI BibTeX RDF
15	André Longtin, Karin Hinzer	Encoding with bursting, subthreshold oscillations, and noise in mammalian cold receptors.	Neural Comput.	1996	DBLP DOI BibTeX RDF
15	Tomoki Fukai	Competition in the temporal domain among neural activities phase-locked to subthreshold oscillations.	Biol. Cybern.	1996	DBLP DOI BibTeX RDF
15	Dominique Coué, George Wilson	A four-quadrant subthreshold mode multiplier for analog neural-network applications.	IEEE Trans. Neural Networks	1996	DBLP DOI BibTeX RDF
15	Takeshi Sakata, Kiyoo Itoh 0001, Masashi Horiguchi, Masakazu Aoki	Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's.	IEEE J. Solid State Circuits	1994	DBLP DOI BibTeX RDF
15	Takeshi Sakata, Kiyoo Itoh 0001, Masashi Horiguchi, Masakazu Aoki	Subthreshold-current reduction circuits for multi-gigabit DRAM's.	IEEE J. Solid State Circuits	1994	DBLP DOI BibTeX RDF
15	Shanti S. Vedula, Fathi M. A. Salam, Gamze Erten	Subthreshold Analog Circuit for Computing the Maximum Principal Component of 3-D Data.	ISCAS	1994	DBLP DOI BibTeX RDF
15	Kewei Yang 0003, Richard C. Meitzler, Andreas G. Andreou	A Model for MOS Effective Channel Mobility with Emphasis in the Subthreshold and Transition Region.	ISCAS	1994	DBLP DOI BibTeX RDF
15	L. Song, Mohamed I. Elmasry, Anthony Vannelli	Analog neural network building blocks based on current mode subthreshold operation.	ISCAS	1993	DBLP BibTeX RDF
15	Andreas G. Andreou, Kwabena A. Boahen, Philippe O. Pouliquen, Aleksandra Pavasovic, Robert E. Jenkins, Kim Strohbehn	Current-mode subthreshold MOS circuits for analog VLSI neural systems.	IEEE Trans. Neural Networks	1991	DBLP DOI BibTeX RDF
15	Philip C. Chan, R. Liu, S. K. Lau, Mario Pinto-Guedes	A Subthreshold Conduction Model for Circuit Simulation of Submicron MOSFET.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1987	DBLP DOI BibTeX RDF
10	Yukihiro Nonaka, Hatsuo Hayashi	Spike-Timing-Dependent LTP/LTD Caused by Uncorrelated Signals through Medial and Lateral Perforant Pathways in the Dentate Granule Cell.	Brain-Inspired Information Technology	2010	DBLP DOI BibTeX RDF
10	Xuebei Yang, Jyotsna Chauhan, Jing Guo, Kartik Mohanram	Graphene tunneling FET and its applications in low-power circuit design.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	graphene nanoribbons, tunneling fets, low-power
10	Sreeharsha Tavva, Dhireesha Kudithipudi	Variation tolerant 9T SRAM cell design.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	bitline leakage, static random access memory (SRAM), process variations, static noise margin, embedded sram
10	Xiaochen Guo, Engin Ipek, Tolga Soyata	Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing.	ISCA	2010	DBLP DOI BibTeX RDF	STT-MRAM, power-efficiency
10	Shigeru Kubota, Kosuke Hamaguchi, Kazuyuki Aihara	Local excitation solutions in one-dimensional neural fields by external input stimuli.	Neural Comput. Appl.	2009	DBLP DOI BibTeX RDF	Local excitation, Neuroscience, Pattern formation, Neural field
10	Naofumi Katada, Haruhiko Nishimura	Stochastic Resonance in Recurrent Neural Network with Hopfield-Type Memory.	Neural Process. Lett.	2009	DBLP DOI BibTeX RDF	Hopfield-type memory, Neural network, Noise, Stochastic
10	Prateek Mishra, Anish Muttreja, Niraj K. Jha	Low-power FinFET circuit synthesis using multiple supply and threshold voltages.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	Low-power, linear programming, synthesis, TCMS
10	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction.	ASP-DAC	2009	DBLP DOI BibTeX RDF
10	Kiyoo Itoh 0001	Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era.	ISLPED	2009	DBLP DOI BibTeX RDF	0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet
10	Bao Liu 0001	Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolution.	ISQED	2009	DBLP DOI BibTeX RDF
10	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos, Priyadarsan Patra	A PVT aware accurate statistical logic library for high- metal-gate nano-CMOS.	ISQED	2009	DBLP DOI BibTeX RDF
10	Ji-Hye Bong, Yong-Jin Kwon, Kyeong-Sik Min, Sung-Mo Kang	New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMs.	ISQED	2009	DBLP DOI BibTeX RDF
10	Bradford E. Peercy	Initiation and propagation of a neuronal intracellular calcium wave.	J. Comput. Neurosci.	2008	DBLP DOI BibTeX RDF	Evanescent calcium wave, Calcium signaling, Hippocampal CA1 pyramidal cell, Mathematical model
10	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
10	Jie Gu 0003, John Keane 0001, Sachin S. Sapatnekar, Chris H. Kim	Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
10	Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, Tsai-Wen Cheng	A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
10	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	Input Vector Reordering for Leakage Power Reduction in FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
10	Andrew B. Kahng, Sudhakar Muddu, Puneet Sharma	Defocus-Aware Leakage Estimation and Control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
10	Jing Li 0073, Aditya Bansal, Swaroop Ghosh, Kaushik Roy 0001	An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	Low-temperature polycrystalline silicon (LTPS), grain boundary (GB), inherent variation, thin-film transistor (TFT), generic, reconfigurable, hybrid system, BIST, DFT, 3D integration
10	Jonathan Touboul, Romain Brette	Dynamics and bifurcations of the adaptive exponential integrate-and-fire model.	Biol. Cybern.	2008	DBLP DOI BibTeX RDF	Dynamical systems, Chaos, Bifurcations, Integrate-and-fire, Spiking neuron models
10	Tomasz Borejko, Witold A. Pleskacz	A Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature Variations.	DDECS	2008	DBLP DOI BibTeX RDF
10	Baozhen Chen, Chengwu Tao, Sumarlin William, Santosh Pandey	Biochemical sensing of charged polyelectrolytes with a novel CMOS floating-gate device architecture.	EIT	2008	DBLP DOI BibTeX RDF
10	Hushrav Mogal, Kia Bazargan	Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction.	ICCAD	2008	DBLP DOI BibTeX RDF
10	Manuel Carrasco-Robles, Luis Serrano	A novel CMOS current mode fully differential tanh (x) implementation.	ISCAS	2008	DBLP DOI BibTeX RDF
10	Roger Dura, Fabrice Mathieu, Liviu Nicu, Francesc Pérez-Murano, Francisco Serra-Graells	A 0.35µm 1.25V piezo-resistance digital ROIC for liquid dispensing MEMS.	ISCAS	2008	DBLP DOI BibTeX RDF
10	Sameer Somvanshi, Santhosh Kasavajjala	A low power sub-1 V CMOS voltage reference.	SoCC	2008	DBLP DOI BibTeX RDF
10	Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, Dionatan S. Moura, André Inácio Reis, Renato P. Ribas	Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	leakage estimation, logic design, cmos gates
10	Joseph F. Ryan 0002, Benton H. Calhoun	Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation.	ISQED	2008	DBLP DOI BibTeX RDF	Sub-threshold Circuits, Sub-Vt, Sense-Amplifiers, Variation, Offset
10	Yajie Chen, Liam McDaid, Steve Hall, Peter M. Kelly	A programmable facilitating synapse device.	IJCNN	2008	DBLP DOI BibTeX RDF
10	Yuanlin Lu, Vishwani D. Agrawal	Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation.	VLSI Design	2008	DBLP DOI BibTeX RDF
10	Juan Gao, Philip Holmes	On the dynamics of electrically-coupled neurons with inhibitory synapses.	J. Comput. Neurosci.	2007	DBLP DOI BibTeX RDF	Bifurcation diagrams, Electrical coupling, Inhibitory synapses, Integrate-and-fire models, Poincaré maps
10	Hongliang Chang, Sachin S. Sapatnekar	Prediction of leakage power under process uncertainties.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	process variation, yield, leakage, Circuit
10	Jonathan E. Rubin, Martin Wechselberger	Giant squid-hidden canard: the 3D geometry of the Hodgkin-Huxley model.	Biol. Cybern.	2007	DBLP DOI BibTeX RDF
10	Christoph Rasche	Neuromorphic Excitable Maps for Visual Processing.	IEEE Trans. Neural Networks	2007	DBLP DOI BibTeX RDF
10	Cosmin Popa	Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs.	PATMOS	2007	DBLP DOI BibTeX RDF
10	Hushrav Mogal, Kia Bazargan	Microarchitecture floorplanning for sub-threshold leakage reduction.	DATE	2007	DBLP DOI BibTeX RDF
10	Minh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis	High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process.	DSD	2007	DBLP DOI BibTeX RDF
10	Xavier Redondo, Jofre Pallares, Francisco Serra-Graells	A 1.2V 130µA 10-bit MOS-Only Log-Domain Sigma Delta Modulator.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Kyung Ki Kim, Yong-Bin Kim	Optimal Body Biasing for Minimum Leakage Power in Standby Mode.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Balaji Jayaraman, Navakanta Bhat	High Precision 16-bit Readout Gas Sensor Interface in 0.13µm CMOS.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Chiu-Hsien Chan, Jack Wills, Jeff LaCoss, John J. Granacki, John Choma Jr.	A Novel Variable-Gain Micro-Power Band-Pass Auto-Zeroing CMOS Amplifier.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Pablo Ituero, José L. Ayala, Marisa López-Vallejo	Leakage-based On-Chip Thermal Sensor for CMOS Technology.	ISCAS	2007	DBLP DOI BibTeX RDF