Search results for "LUT"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Yaseer Arafat Durrani, Teresa Riesgo	LUT-Based Power Macromodeling Technique for DSP Architectures.	ICECS	2007	DBLP DOI BibTeX RDF
17	Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan	Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs.	IPDPS	2007	DBLP DOI BibTeX RDF
17	Bo Ai 0001, Zhixing Yang, Changyong Pan, Taotao Zhang, Yong Wang 0013, Jianhua Ge	Improved LUT Technique for HPA Nonlinear Pre-Distortion in OFDM Systems.	Wirel. Pers. Commun.	2006	DBLP DOI BibTeX RDF
17	Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi	Compile-time area estimation for LUT-based FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Reconfigurable computing, compiler optimization, resource estimation
17	Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer	Regular Routing Architecture for a LUT-based MPGA.	ISVLSI	2006	DBLP DOI BibTeX RDF
17	Jason Cong, Kirill Minkovich	Optimality study of logic synthesis for LUT-based FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	optimization, logic synthesis, technology mapping, Boolean logic, FPGA lookup table
17	Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton	Improvements to technology mapping for LUT-based FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	area recovery, cut enumeration, lossless synthesis, FPGA, technology mapping
17	Hiroki Nakahara, Tsutomu Sasao	A Soft Error Tolerant LUT Cascade Emulator.	ATS	2006	DBLP DOI BibTeX RDF
17	Francisco-Javier Veredas, Hans-Jörg Pfleiderer	Power estimation of a LUT-based MPGA.	FPT	2006	DBLP DOI BibTeX RDF
17	Takakazu Kurokawa	Neural network approach to the optimal lut assignment in FPGA for parallel multipliers over GF(2n).	Artificial Intelligence and Soft Computing	2006	DBLP BibTeX RDF
17	Mei-Chun Lo, Chang-Lang Chen, Ruey-Kuen Perng, Zong-Xian Hsieh	The Characterisation of Colour Printing Devices via Physical, Numerical and LUT Models.	CGIV	2006	DBLP BibTeX RDF
17	Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura	A Design Algorithm for Sequential Circuits Using LUT Rings.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2005	DBLP DOI BibTeX RDF
17	Tomonori Izumi, Shin'ichi Kouyama, Hiroyuki Ochi, Yukihiro Nakamura	An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2005	DBLP DOI BibTeX RDF
17	Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi	SPFD-Based Flexible Transformation of LUT-Based FPGA Circuits.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2005	DBLP DOI BibTeX RDF
17	Hakim Khali, Yvon Savaria, Jean-Louis Houle	A system level implementation strategy and partitioning heuristic for LUT-based applications.	Comput. Electr. Eng.	2005	DBLP DOI BibTeX RDF
17	Sheng Bao, Shi Chen, Zhiqiang Jing, Ran Ren	A DNA Sequence Compression Algorithm Based on LUT and LZ77	CoRR	2005	DBLP BibTeX RDF
17	Steven A. Guccione	Microprocessors: The New LUT.	ERSA	2005	DBLP BibTeX RDF
17	Dong-Woo Kang, Yun-Tae Kim, Yang-Ho Cho, Kee-Hyon Park, Wonhee Choe, Yeong-Ho Ha	Color decomposition method for multiprimary display using 3D-LUT in linearized LAB space.	Color Imaging: Processing, Hardcopy, and Applications	2005	DBLP DOI BibTeX RDF
17	Andrea Lodi 0002, Luca Ciccarelli, Domenico Loparco, Roberto Canegallo, Roberto Guerrieri	Low leakage design of LUT-based FPGAs.	ESSCIRC	2005	DBLP DOI BibTeX RDF
17	Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera	A yield and speed enhancement scheme under within-die variations on 90nm LUT array.	CICC	2005	DBLP DOI BibTeX RDF
17	David B. Thomas, Wayne Luk	High Quality Uniform Random Number Generation Through LUT Optimised Linear Recurrences.	FPT	2005	DBLP BibTeX RDF
17	Sami Yehia, Nathan Clark, Scott A. Mahlke, Krisztián Flautner	Exploring the design space of LUT-based transparent accelerators.	CASES	2005	DBLP DOI BibTeX RDF	accelerator design, embedded processing, efficient computation
17	Sonia Saied Bouajina, Meriem Jaïdane-Saïdane, Slim Boumaiza, Fadhel M. Ghannouchi	A robust non-uniform LUT indexing method in digital predistortion linearization of RF power amplifiers.	EUSIPCO	2005	DBLP BibTeX RDF
17	Elias Ahmed, Jonathan Rose	The effect of LUT and cluster size on deep-submicron FPGA performance and density.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
17	Richard H. Turner, Roger F. Woods	Highly efficient, limited range multipliers for LUT-based FPGA architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
17	Ricardo L. de Queiroz, Patrick A. Stein	LUT filters for quantized processing of signals.	IEEE Trans. Signal Process.	2004	DBLP DOI BibTeX RDF
17	Chi-Chou Kao, Yen-Tai Lai	Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction.	ASP-DAC	2004	DBLP DOI BibTeX RDF
17	Michael Hübner 0001, Tobias Becker, Jürgen Becker 0001	Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration.	SBCCI	2004	DBLP DOI BibTeX RDF	virtex, dynamic partial reconfiguration
17	Paul Leventis, Brad Vest, Mike Hutton, David M. Lewis	MAX II: A low-cost, high-performance LUT-based CPLD.	CICC	2004	DBLP DOI BibTeX RDF
17	Holger Kropp	Quellenmodell-Architekturen redundanz-reduzierender Codierungsverfahren aus LUT-basierten FPGAs.		2004	RDF
17	Francisco Cardells-Tormo, Javier Valls-Coquillat	Area-optimized implementation of quadrature direct digital frequency synthesizers on LUT-based FPGAs.	IEEE Trans. Circuits Syst. II Express Briefs	2003	DBLP DOI BibTeX RDF
17	Minglu Jin, Sooyoung Kim, Do-Seob Ahn, Deockgil Oh, Jae Moung Kim	A fast LUT predistorter for power amplifier in OFDM systems.	PIMRC	2003	DBLP DOI BibTeX RDF
17	Seong Yong Ohm, Ki-Yeol Ryu, Kang Yi	Lower Bound Estimation on the Numbers of LUT Blocks and Micro-Registers for Time-Mulitplexed FPGA Synthesis.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
17	L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti 0001, Sivaprakasam Suresh	On-Line Location of Multiple Faults in LUT Based Reconfigurable Systems.	VLSI	2003	DBLP BibTeX RDF
17	Hao Li, Wai-Kei Mak, Srinivas Katkoori	Efficient LUT-based FPGA technology mapping for power minimization.	ASP-DAC	2003	DBLP DOI BibTeX RDF
17	Andrea Lodi 0002, Carlo Chiesa, Fabio Campi, Mario Toma	A flexible LUT-based carry chain for FPGAs.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
17	Simone G. O. Fiori	Hybrid independent component analysis by adaptive LUT activation function neurons.	Neural Networks	2002	DBLP DOI BibTeX RDF
17	Joerg Abke, Erich Barke	A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs .	DATE	2002	DBLP DOI BibTeX RDF
17	Richard H. Turner, Roger F. Woods, Tim Courtney	Multiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
17	Tim Courtney, Richard H. Turner, Roger F. Woods	Mapping Multi-Mode Circuits to LUT-Based FPGA Using Embedded MUXes.	FCCM	2002	DBLP DOI BibTeX RDF
17	Jason Helge Anderson, Farid N. Najm	Power-aware technology mapping for LUT-based FPGAs.	FPT	2002	DBLP DOI BibTeX RDF
17	Loïc Lagadec, Bernard Pottier, Oscar Villellas, Erwan Fabiani, Catherine Dezan	A LUT based Approach for High Level Synthesis on FPGAs.	IWLS	2002	DBLP BibTeX RDF
17	Alan Mishchenko, Tsutomu Sasao	Encoding of Boolean Functions and its Application to LUT Cascade Synthesis.	IWLS	2002	DBLP BibTeX RDF
17	Julian E. Bonilla, Victor Hugo Grisales, Miguel A. Melgarejo	Genetic Tuned FPGA Based PD Fuzzy LUT Controller.	FUZZ-IEEE	2001	DBLP DOI BibTeX RDF
17	Jian Qiao, Makoto Ikeda, Kunihiro Asada	Finding an optimal functional decomposition for LUT-based FPGA synthesis.	ASP-DAC	2001	DBLP DOI BibTeX RDF
17	Ricardo L. de Queiroz, Patrick Fleckenstein	Signal processing using LUT filters based on hierarchical VQ.	ICASSP	2001	DBLP DOI BibTeX RDF
17	Joerg Abke, Erich Barke	A New Placement Method for Direct Mapping into LUT-Based FPGAs.	FPL	2001	DBLP DOI BibTeX RDF
17	Michael Böhnel, Reinhold Weiss	Self-Stabilization Testing of LUT-Based FPGA Designs by Fault Injection.	IOLTW	2001	DBLP DOI BibTeX RDF
17	Shyue-Kung Lu, Jen-Sheng Shih	Testing Configurable LUT-Based FPGAs.	J. Inf. Sci. Eng.	2000	DBLP BibTeX RDF
17	Jason Cong, Yean-Yow Hwang	Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	computer-aided design of VSLI, FPGA, synthesis, system design, decomposition, technology mapping, simplification, programmable logic, logic optimization, delay minimization
17	Murat Mese, Palghat P. Vaidyanathan	Look up Table (LUT) Method for Image Halftoning.	ICIP	2000	DBLP DOI BibTeX RDF
17	Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya	An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation.	ASP-DAC	2000	DBLP DOI BibTeX RDF
17	Murat Mese, P. P. Vaidyanathan	Template selection for LUT inverse halftoning and application to color halftones.	ICASSP	2000	DBLP DOI BibTeX RDF
17	Murat Mese, Palghat P. Vaidyanathan	Look up table (LUT) inverse halftoning.	ISCAS	2000	DBLP DOI BibTeX RDF
17	Murat Mese, P. P. Vaidyanathan	Tree-structured method for improved LUT inverse halftoning.	EUSIPCO	2000	DBLP BibTeX RDF
17	Parag K. Lala, Alfred L. Burress	Self-Checking Logic Design for LUT-Based FPGAs.	FPGA	1999	DBLP DOI BibTeX RDF
17	Frank Heile, Andrew Leaver	Hybrid Product Term and LUT Based Architectures Using Embedded Memory Blocks.	FPGA	1999	DBLP DOI BibTeX RDF	product terms, RAM, heterogeneous architecture
17	André DeHon	Balancing Interconnect and Computation in a Reconfiguable Computing Array (or, why you don't really want 100% LUT utilization).	FPGA	1999	DBLP DOI BibTeX RDF
17	George A. Constantinides, Peter Y. K. Cheung, Wayne Luk	Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs.	FPL	1999	DBLP DOI BibTeX RDF
17	Joerg Abke, Erich Barke, Jörn Stohmann	A Universal Module Generator for LUT-Based FPGAs.	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	Multiplexor, Multiplexor Structure, FPGA, Technology Mapping, Module Generator
17	Manuel Jiménez, Chin-Long Wey, Michael A. Shanblatt	Mapping Multiplication Algorithms into a Family of LUT-based FPGAs (Abstract).	FPGA	1998	DBLP DOI BibTeX RDF
17	Peichen Pan, Chih-Chang Lin	A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF
17	Noriyoshi Itazaki, Fumiro Matsuki, Yasuyuki Matsumoto, Kozo Kinoshita	Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
17	Ricardo P. Jacobi	LogosPGA: Synthesis System for LUT Devices.	SBCCI	1998	DBLP DOI BibTeX RDF
17	Igor Lemberski	Modified Approach to Automata State Encoding for LUT FPGA Implementation.	EUROMICRO	1998	DBLP DOI BibTeX RDF
17	Amit Chowdhary, John P. Hayes	General Modeling and Technology-Mapping Technique for LUT-Based FPGAs.	FPGA	1997	DBLP DOI BibTeX RDF
17	Alexandre F. Tenca, Milos D. Ercegovac	Synchronous Up/Down Binary Counter for LUT FPGAs with Counting Frequency Independent of Counter Size.	FPGA	1997	DBLP DOI BibTeX RDF
17	Jie-Hong R. Jiang, Jing-Yang Jou, Juinn-Dar Huang, Jung-Shian Wei	BDD based lambda set selection in Roth-Karp decomposition for LUT architecture.	ASP-DAC	1997	DBLP DOI BibTeX RDF
17	Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara	Testing for the programming circuit of LUT-based FPGAs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	programming circuit, control circuit, configuration memory cell array, FPGA, fault model, SRAM, shift registers, shift registers, look-up table
17	Maurice Kilavuka Inuani, Jonathan Saul	Technology mapping of heterogeneous LUT-based FPGAs.	FPL	1997	DBLP DOI BibTeX RDF
17	Xiaochun Lin, Erik L. Dagless, Aiguo Lu	Technology mapping of LUT based FPGAs for delay optimisation.	FPL	1997	DBLP DOI BibTeX RDF
17	Shashidhar Thakur, D. F. Wong 0001	Simultaneous area and delay minimum K-LUT mapping for K-exact networks.	Integr.	1996	DBLP DOI BibTeX RDF
17	Peichen Pan, C. L. Liu 0001	Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance.	FPGA	1996	DBLP DOI BibTeX RDF	FPGAs, sequential circuits, retiming, technology mapping, look-up table, logic replication, clock period
17	Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses	The Wave Pipeline Effect on LUT-Based FPGA Architectures.	FPGA	1996	DBLP DOI BibTeX RDF
17	Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara	A Test Methodology for Interconnect Structures of LUT-based FPGAs.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	Programmable Interconnect Structures, Cross Point Switch, Configurable Logic Block, FPGA, Test Pattern Generation
17	Christian Legl, Klaus Eckl, Bernd Wurth	Performance-Directed Technology-Mapping for LUT-Based FPGAs - What Role Do Decomposition and Covering Play?	FPL	1996	DBLP DOI BibTeX RDF
17	Jason Cong, Yean-Yow Hwang	Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design.	DAC	1996	DBLP DOI BibTeX RDF
17	Christian Legl, Bernd Wurth, Klaus Eckl	A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs.	DAC	1996	DBLP DOI BibTeX RDF
17	Francisco Javier González-Serrano, Aníbal R. Figueiras-Vidal, Antonio Artés-Rodríguez	A fast LUT+CMAC data predistorter.	EUSIPCO	1996	DBLP BibTeX RDF
17	Toshiaki Miyazaki, Hiroshi Nakada, Akihiro Tsutsui, Kazuhisa Yamada, Naohisa Ohta	Performance improvement technique for synchronous circuits realized as LUT-based FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
17	Jason Cong, Yean-Yow Hwang	Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping.	FPGA	1995	DBLP DOI BibTeX RDF
17	A. R. Naseer, M. Balakrishnan, Anshul Kumar	Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs.	FPL	1995	DBLP DOI BibTeX RDF
17	Wen-Zen Shen, Juinn-Dar Huang, Shih-Min Chao	Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping.	DAC	1995	DBLP DOI BibTeX RDF
17	Jason Cong, Yuzheng Ding	On nominal delay minimization in LUT-based FPGA technology mapping.	Integr.	1994	DBLP DOI BibTeX RDF
17	Jason Cong, Yuzheng Ding, Tong Gao, Kuang-Chien Chen	LUT-based FPGA technology mapping under arbitrary net-delay models.	Comput. Graph.	1994	DBLP DOI BibTeX RDF
17	Toshiaki Miyazaki, Hiroshi Nakada, Akihiro Tsutsui, Kazuhisa Yamada, Naohisa Ohta	A Speed-Up Technique for Synchronous Circuits Realized as LUT-Based FPGAs.	FPL	1994	DBLP DOI BibTeX RDF
17	Jason Cong, Yuzheng Ding	Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs.	ICCAD	1993	DBLP DOI BibTeX RDF
17	Jason Cong, Yuzheng Ding	On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping.	DAC	1993	DBLP DOI BibTeX RDF
17	Narasimha B. Bhat, Dwight D. Hill	Routable Technologie Mapping for LUT FPGAs.	ICCD	1992	DBLP DOI BibTeX RDF
17	Hideto Motomura, Katsuhiro Kanamori, Teruo Fumoto, Hiroaki Kotera	Applications of the Color Conversion System Using the LUT and Interpolation to the Real-Time Color Recognition.	MVA	1992	DBLP BibTeX RDF
10	Edward A. Stott, Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung	Degradation in FPGAs: measurement and modelling.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, self test
10	Larkhoon Leem, James A. Weaver, Metha Jeeradit, James S. Harris Jr.	Nano-magnetic non-volatile CMOS circuits for nano-scale FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	spin-torque devices, fpga, spintronics
10	Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita	Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	overclocking, timing error detection, timing error recovery, fpga
10	Manu Jose, Yu Hu 0002, Rupak Majumdar, Lei He 0001	Rewiring for robustness.	DAC	2010	DBLP DOI BibTeX RDF	SPFD, FPGA, logic synthesis, soft errors, rewiring
10	Roberto Gutierrez, Javier Valls	Low-Power FPGA-Implementation of atan(Y/X) Using Look-Up Table Methods for Communication Applications.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	atan(Y/X), FPGA, Wireless communication, CORDIC
10	Jing-Ming Guo, Ming-Feng Wu	Improved Block Truncation Coding Based on the Void-and-Cluster Dithering Approach.	IEEE Trans. Image Process.	2009	DBLP DOI BibTeX RDF
10	Grzegorz Borowik, Tadeusz Luba, Bogdan J. Falkowski	Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories.	DDECS	2009	DBLP DOI BibTeX RDF
10	Stefan Kolodzinski, Edward Hrynkiewicz	An utilisation of Boolean differential calculus in variables partition calculation for decomposition of logic functions.	DDECS	2009	DBLP DOI BibTeX RDF
10	Kimmo U. Järvinen	On Repeated Squarings in Binary Fields.	Selected Areas in Cryptography	2009	DBLP DOI BibTeX RDF
10	Rajesh Amratlal Thakker, Chaitanya Sathe, Angada B. Sachid, Maryam Shojaei Baghini, V. Ramgopal Rao, Mahesh B. Patil	Automated design and optimization of circuits in emerging technologies.	ASP-DAC	2009	DBLP DOI BibTeX RDF